Output driving circuit

Abstract

The utility model provides an output driving circuit. The circuit comprises a first switch tube, a second switch tube, a first control logic unit coupled between a second power supply end and a grounding end, a power supply selection circuit coupled between the first power supply end and the second power supply end, an inverter, and a second control logic unit coupled between the second power supply end and the grounding end. And the power supply selection circuit provides a third power supply voltage to the outside according to the first power supply voltage of the first power supply end and the second power supply voltage of the second power supply end. And the inverter is powered by a third power supply voltage, and in the power-on process of the second power supply voltage of the second power supply end, the output voltage of the inverter is a control signal of the third power supply voltage, so that the first switching tube can be cut off. In this way, an overshoot current caused when the first power supply voltage is powered up earlier than the second power supply voltage can be prevented.

Description

Technical Field

[0001] The utility model relates to the field of circuit design, and in particular to an output driving circuit.

Background Art

[0002] Figure 1 Shown is an example of an IO (input / output) output driving circuit in the prior art. The output driving circuit includes a PMOS transistor M 11 , a first control logic unit for driving the PMOS (P-channel Metal Oxide Semiconductor) transistor M 11 , an NMOS (N-channel Metal Oxide Semiconductor) transistor M 12 , and a second control logic unit for driving the NMOS transistor M 12 . The source of the PMOS transistor M 11 is coupled to a first power supply voltage VDDIO, and the source of the NMOS transistor M 12 is coupled to the ground terminal. The first control logic unit and the second control logic unit are powered by a second power supply voltage VDD_EXT. The first power supply voltage VDDIO and the second power supply voltage VDD_EXT are different power supply sources.

[0003] The output driving circuit has a parasitic diode D P from the signal output terminal output to the second power supply voltage VDD_EXT. The anode of the parasitic diode D P is coupled to the signal output terminal, and the cathode of the parasitic diode D P is coupled to the second power supply voltage VDD_EXT. The parasitic diode D P may include the drain-body diode of the PMOS transistor in the output driving circuit.

[0004] However, when the output driving circuit is powered on, it is possible that the first power supply voltage VDDIO is powered on first, while the second power supply voltage VDD_EXT is powered on later. As Figure 1 shown, at this time, the first power supply voltage VDDIO is at a high level (such as 1.2V), while the second power supply voltage VDD_EXT is still at a low level. The first control logic unit will output a low level (such as 0V), so that the PMOS transistor M 11 will conduct. At the same time, since the second power supply voltage VDD_EXT is still at a low level at this time, this causes the parasitic diode D P to conduct, so that a large amount of current I1 flows from the first power supply voltage VDDIO through the parasitic diode D P to the second power supply voltage VDD_EXT.

[0005] Therefore, there is an urgent need to propose a new technical solution to solve the above problems.

Utility Model Content

[0006] One object of the present utility model is to provide an output driving circuit, which can prevent overshoot current caused when the first power supply voltage is powered on before the second power supply voltage.

[0007] According to one aspect of the present utility model, there is provided an output driving circuit, which includes: a first switching transistor, which includes a first connection end coupled to a first power supply terminal, a second connection end coupled to a signal output terminal, and a control end; a second switching transistor, which includes a first connection end coupled to a ground terminal, a second connection end coupled to the signal output terminal, and a control end; a first control logic unit coupled between a second power supply terminal and the ground terminal; a power supply selection circuit coupled between the first power supply terminal and the second power supply terminal, which provides a third power supply voltage according to a first power supply voltage of the first power supply terminal and a second power supply voltage of the second power supply terminal, wherein the first power supply voltage of the first power supply terminal is different from the second power supply voltage of the second power supply terminal; an inverter powered by the third power supply voltage, which includes an input end coupled to an output end of the first control logic unit and an output end coupled to the control end of the first switching transistor. During the power-on process of the second power supply voltage of the second power supply terminal, the output voltage of the inverter is a control signal of the third power supply voltage, which can make the first switching transistor turn off; a second control logic unit coupled between the second power supply terminal and the ground terminal, and an output end thereof is coupled to the control end of the second switching transistor.

[0008] Compared with the prior art, during the power-on process of the second power supply voltage of the second power supply terminal in the present utility model, the output voltage of the inverter is a control signal of the third power supply voltage, which can make the first switching transistor turn off, thereby preventing overshoot current caused when the first power supply voltage is powered on before the second power supply voltage.

Description of the Drawings

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Among them:

[0010] Figure 1 It is an example of an IO output driving circuit in the prior art;

[0011] Figure 2 It is a schematic circuit diagram of the output driving circuit in the first embodiment of the present utility model;

[0012] Figure 3 This is a schematic circuit diagram of the output driving circuit in the second embodiment of the present utility model.

Specific Embodiment

[0013] To make the above objects, features, and advantages of the present utility model more obvious and understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present utility model. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. In the present utility model, unless otherwise clearly defined and limited, the terms "connected", "connected to", "coupled", etc., which represent electrical connection terms, should be understood in a broad sense; for example, it may be a direct electrical connection or an indirect electrical connection through an intermediate medium, and the intermediate medium may be electronic components, functional circuits, etc. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0015] The present utility model provides an IO output driving circuit (hereinafter referred to as the output driving circuit) using a dual - power supply design, which can prevent the over - shoot current flowing from the first power supply voltage VDDIO to the second power supply voltage VDD_EXT caused by the parasitic diode when the first power supply voltage VDDIO is powered on before the second power supply voltage VDD_EXT.

[0016] Figure 2 This is a schematic circuit diagram of the output driving circuit 100 in the first embodiment of the present utility model. As Figure 2 shown, the output driving circuit includes: a first switching transistor, a second switching transistor, a first control logic unit, a power supply selection circuit 110, an inverter INV1, and a second control logic unit.

[0017] The first switching transistor includes a first connection end coupled to the first power supply terminal VDDIO, a second connection end coupled to the signal output terminal Output, and a control end. The second switching transistor includes a first connection end coupled to the ground terminal GND, a second connection end coupled to the signal output terminal Output, and a control end. In one embodiment, the first switching transistor is a PMOS transistor M 11 and the source of the PMOS transistor M 11 is the first connection end of the first switching transistor, the drain of the PMOS transistor M 11 is the second connection end of the first switching transistor, and the PMOS transistor M 11The gate of the first switch transistor is the control terminal of the first switch transistor; the second switch transistor is the NMOS transistor M 12 , the source of the NMOS transistor M 12 is the first connection terminal of the second switch transistor, and the drain of the NMOS transistor M 12 is the second connection terminal of the second switch transistor, and the gate of the NMOS transistor M 12 is the control terminal of the second switch transistor.

[0018] The first control logic unit is coupled between the second power supply terminal VDD_EXT and the ground terminal. The second control logic unit is coupled between the second power supply terminal VDD_EXT and the ground terminal, and its output terminal is coupled to the control terminal of the second switch transistor.

[0019] The power supply selection circuit 110 is coupled between the first power supply terminal VDDIO and the second power supply terminal VDD_EXT, and provides a third power supply voltage V according to the first power supply voltage VDDIO of the first power supply terminal and the second power supply voltage VDD_EXT of the second power supply terminal C , where the first power supply voltage VDDIO of the first power supply terminal is different from the second power supply voltage VDD_EXT of the second power supply terminal.

[0020] The inverter INV1 is powered by the third power supply voltage V C , and includes an input terminal coupled to the output terminal of the first control logic unit and an output terminal coupled to the control terminal of the first switch transistor. During the power-on process of the second power supply voltage of the second power supply terminal, the output voltage of the inverter INV1 is a control signal of the third power supply voltage V C , which can make the first switch transistor cut off. In this way, even if the first power supply voltage VDDIO is powered on earlier than the second power supply voltage VDD_EXT, the inverter INV1 will output a voltage of the third power supply voltage V C to make the first switch transistor cut off, thereby preventing a large current from flowing from the first power supply voltage VDDIO to the second power supply voltage VDD_EXT through the parasitic diode.

[0021] As Figure 2 shown, the output driving circuit 100 has a parasitic diode D from the signal output terminal output to the second power supply terminal VDD_EXT P , the anode of the parasitic diode D P is coupled to the signal output terminal output, and the cathode of the parasitic diode D P is coupled to the second power supply terminal VDD_EXT.

[0022] In one embodiment, at the end of the power-on of the second power supply voltage VDD_EXT at the second power supply terminal, the power supply selection circuit 110 guides the second power supply voltage VDD_EXT to its output terminal and outputs a third power supply voltage V through its output terminal C Preferably, the third power supply voltage V C can be based on being equal to the second power supply voltage VDD_EXT. Here, the third power supply voltage V C being based on being equal to the second power supply voltage VDD_EXT means that there may be a necessary voltage drop between the third power supply voltage V C and the second power supply voltage VDD_EXT, that is, the necessary voltage drop from the second power supply terminal to the output terminal of the power supply selection circuit 110. This voltage drop may be relatively small and can often be ignored. Of course, in other embodiments, at this time, the third power supply voltage V C can also be formed by the second power supply voltage VDD_EXT and the first power supply voltage VDDIO to form the third power supply voltage V C .

[0023] For example, after the second power supply voltage VDD_EXT is powered on to 3V, then the third power supply voltage V output by the power supply selection circuit 110 C can also be 3V. Regardless of whether the first power supply voltage VDDIO is 0V, 1V, 1.1V, 2V, etc. at this time, when the first control logic unit outputs a low level, the inverter INV1 can output a high level of 3V, so that the first switching tube can be turned off. At this time, if the first power supply voltage VDDIO at the first power supply terminal has also been powered on, for example, the first power supply voltage VDDIO is 1.2V, the output driving circuit 100 can work normally, that is, the first control logic unit can output a corresponding logic level according to the first input signal input1, and then output a control signal through the inverter INV1 to control the conduction or cut-off of the first switching tube; the second control logic unit outputs a corresponding logic level according to the second input signal input2 to control the conduction or cut-off of the second switching tube. When the first switching tube is conducting and the second switching tube is cut off, the signal output terminal output outputs a high level. When the first switching tube is cut off and the second switching tube is conducting, the signal output terminal output outputs a low level.

[0024] In one embodiment, when the first power supply voltage VDDIO at the first power supply terminal is higher than the second power supply voltage VDD_EXT at the second power supply terminal plus a predetermined threshold voltage, the power supply selection circuit 110 can guide the first power supply voltage VDDIO to its output terminal and output a third power supply voltage V through its output terminal C Preferably, the third power supply voltage V C can be based on being equal to the first power supply voltage VDDIO. Here, the third power supply voltage VC Based on the fact that being equal to the first power supply voltage VDDIO means the third power supply voltage V C There may be a necessary voltage drop between the first power supply voltage VDDIO, that is, the necessary voltage drop from the first power supply terminal to the output terminal of the power supply selection circuit 110. This voltage drop may be relatively small and can often be ignored. For example, the predetermined threshold voltage is the turn-on threshold voltage of the PMOS transistor. Of course, in other embodiments, at this time, the third power supply voltage V C can also be formed by the second power supply voltage VDD_EXT and the first power supply voltage VDDIO to form the third power supply voltage V C .

[0025] For example, assume that the first power supply voltage VDDIO has been powered on to 3V, while the second power supply voltage VDD_EXT has not been powered on, that is, the second power supply voltage VDD_EXT is 0V. At this time, the first power supply voltage VDDIO is higher than the second power supply voltage VDD_EXT plus the turn-on threshold voltage of the PMOS transistor. The power supply selection circuit 110 guides the first power supply voltage VDDIO to its output terminal and outputs the third power supply voltage V through its output terminal C , at this time, the third power supply voltage V C is approximately equal to 3V. Since the second power supply voltage VDD_EXT is 0V, the first control logic unit outputs a low level (0V). The inverter INV1 is powered by the third power supply voltage V C (3V). At this time, the inverter INV1 outputs a high level of 3V, and the first switching transistor is turned off. In this way, even if the first power supply voltage VDDIO is powered on earlier than the second power supply voltage VDD_EXT (for example, the first power supply voltage VDDIO is higher than the second power supply voltage VDD_EXT plus the predetermined threshold voltage), the inverter INV1 can output a high level to turn off the first switching transistor, which can prevent the overshoot current flowing from the first power supply voltage VDDIO to the second power supply voltage VDD_EXT caused by the parasitic diode when the first power supply voltage VDDIO is powered on earlier than the second power supply voltage VDD_EXT.

[0026] Such as Figure 2As shown, the power supply selection circuit 100 includes: a first switch unit M2 and a second switch unit M3 connected in series between a first power supply terminal VDDIO and a second power supply terminal VDD_EXT; a third switch unit M4 and a fourth switch unit M5 connected in series between the first power supply terminal VDDIO and a ground terminal GND. The control terminals of the first switch unit M2, the third switch unit M4, and the fourth switch unit M5 are coupled to the second power supply terminal VDD_EXT. The control terminal of the second switch unit M3 is coupled to an intermediate node B between the third switch unit M4 and the fourth switch unit M5. An intermediate node C between the first switch unit M2 and the second switch unit M3 is the output terminal of the power supply selection circuit 100 and provides a third power supply voltage V C .

[0027] Specifically, the second connection terminal of the first switch unit M2 is coupled to the first power supply terminal VDDIO, the first connection terminal of the first switch unit M2 is coupled to the intermediate node C, the second connection terminal of the second switch unit M3 is coupled to the second power supply terminal VDD_EXT, the first connection terminal of the second switch unit M3 is coupled to the intermediate node C, the first connection terminal of the third switch unit M4 is coupled to the first power supply terminal VDDIO, the second connection terminal of the third switch unit M4 is coupled to the intermediate node B, the first connection terminal of the fourth switch unit M5 is coupled to the second power supply terminal VDD_EXT, and the second connection terminal of the fourth switch unit M5 is coupled to the intermediate node B. Preferably, the first switch unit M2, the second switch unit M3, and the third switch unit M4 are PMOS transistors. The gate of the PMOS transistor is the control terminal, the source of the PMOS transistor is the first connection terminal of each switch unit, and the drain of the PMOS transistor is the second connection terminal of each switch unit. The fourth switch unit M5 is an NMOS transistor. The gate of the NMOS transistor is the control terminal, the source of the NMOS transistor is the first connection terminal of the fourth switch unit M5, and the drain of the NMOS transistor is the second connection terminal of the fourth switch unit M5.

[0028] The functions of the third switch unit M4 and the fourth switch unit M5 are to provide a bias voltage to the gate of the second switch unit M3. When the first power supply voltage VDDIO is higher than the second power supply voltage VDD_EXT plus the conduction threshold voltage of the PMOS transistor and the second power supply voltage VDD_EXT is lower than the conduction threshold voltage of the NMOS transistor, the third switch unit M4 conducts and the fourth switch unit M5 cuts off. At this time, the voltage of the intermediate node B is the first power supply voltage VDDIO. At the same time, the first switch unit M2 conducts and the second switch unit M3 cuts off, and the voltage of the intermediate stage C is the first power supply voltage VDDIO.

[0029] At the end of the power - on of the second power supply voltage VDD_EXT at the second power supply terminal, the second power supply voltage VDD_EXT will be higher than the turn - on threshold voltage of the NMOS transistor. Therefore, the fourth switching unit M5 is turned on, and the third switching unit M4 is turned off. The voltage of the intermediate node B is the second power supply voltage VDD_EXT. At the same time, the second switching unit M3 is turned on, and the first switching unit M2 is turned off. The voltage of the intermediate node C is the second power supply voltage VDD_EXT.

[0030] During the power - on process of the first power supply voltage VDDIO and the second power supply voltage VDD_EXT, there may sometimes be a situation where the third switching unit M4 and the fourth switching unit M5 are turned on simultaneously, and the first switching unit M2 and the second switching unit M2 are turned on simultaneously. For example, when the second power supply voltage VDD_EXT is higher than the turn - on threshold voltage of the NMOS transistor, and the first power supply voltage VDDIO is higher than the second power supply voltage VDD_EXT plus the turn - on threshold voltage of the PMOS transistor, the four switching units will be turned on simultaneously. In this case, the third power supply voltage V C is no longer determined solely by the first power supply voltage VDDIO or the second power supply voltage VDD_EXT, but is jointly determined by the first power supply voltage VDDIO and the second power supply voltage VDD_EXT. Therefore, Figure 3 In the second embodiment of the output driving circuit shown, the power supply selection circuit 110 further includes: a first resistor R1 connected in series between the first power supply terminal VDDIO and the third switching unit M4; a second resistor R2 connected in series between the first power supply terminal VDDIO and the first switching unit M2. In this way, during the power - on process of the first power supply voltage VDDIO and the second power supply voltage VDD_EXT, the current flowing through the third switching unit M4 and the first switching unit M2 can be reduced, and the energy consumption can be reduced.

[0031] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above - mentioned terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.

[0032] Although the embodiments of the present invention have been shown and described above, it can be understood that the above - mentioned embodiments are exemplary and should not be construed as limitations on the present invention. Those of ordinary skill in the art can make changes, modifications and variations to the above - mentioned embodiments within the scope of the present invention.

Claims

1. An output driving circuit, characterized in that, It includes: A first switching transistor, which includes a first connection end coupled to a first power supply terminal, a second connection end coupled to a signal output terminal, and a control end; A second switching transistor, which includes a first connection end coupled to a ground terminal, a second connection end coupled to the signal output terminal, and a control end; A first control logic unit coupled between a second power supply terminal and the ground terminal; A power supply selection circuit coupled between the first power supply terminal and the second power supply terminal, which provides a third power supply voltage according to a first power supply voltage of the first power supply terminal and a second power supply voltage of the second power supply terminal, wherein the first power supply voltage of the first power supply terminal is different from the second power supply voltage of the second power supply terminal; An inverter powered by the third power supply voltage, which includes an input end coupled to an output end of the first control logic unit and an output end coupled to the control end of the first switching transistor. During the power-on process of the second power supply voltage of the second power supply terminal, the output voltage of the inverter is a control signal of the third power supply voltage, which can make the first switching transistor cut off; A second control logic unit coupled between the second power supply terminal and the ground terminal, and an output end of the second control logic unit is coupled to the control end of the second switching transistor.

2. The output driving circuit according to claim 1, wherein At the end of the power-on of the second power supply voltage of the second power supply terminal, the power supply selection circuit guides the second power supply voltage to its output end and outputs the third power supply voltage through its output end; When the first power supply voltage of the first power supply terminal is higher than the second power supply voltage of the second power supply terminal plus a predetermined threshold voltage, the power supply selection circuit guides the first power supply voltage to its output end and outputs the third power supply voltage through its output end.

3. The output driving circuit according to claim 2, wherein The predetermined threshold voltage is the turn-on threshold voltage of a PMOS transistor.

4. The output driving circuit according to claim 1, characterized in that, The output driving circuit has a parasitic diode from the signal output terminal to the second power supply terminal. The anode of the parasitic diode is coupled to the signal output terminal, and the cathode of the parasitic diode is coupled to the second power supply terminal.

5. The output driving circuit according to claim 1, wherein After the power-on is completed, the first control logic unit outputs a corresponding logic level according to a first input signal, and then outputs a control signal through the inverter to control the conduction or cut-off of the first switching transistor. The second control logic unit outputs a corresponding logic level according to a second input signal to control the conduction or cut-off of the second switching transistor. When the first switching transistor is conducting and the second switching transistor is cut off, the signal output terminal outputs a high level. When the first switching transistor is cut off and the second switching transistor is conducting, the signal output terminal outputs a low level.

6. The output driving circuit according to claim 1, wherein The first switching transistor is a PMOS transistor. The source of the PMOS transistor is the first connection end of the first switching transistor. The drain of the PMOS transistor is the second connection end of the first switching transistor. The gate of the PMOS transistor is the control end of the first switching transistor. The second switching transistor is an NMOS transistor. The source of the NMOS transistor is the first connection end of the second switching transistor, the drain of the NMOS transistor is the second connection end of the second switching transistor, and the gate of the NMOS transistor is the control end of the second switching transistor.

7. The output driving circuit according to claim 1, wherein The power supply selection circuit includes: a first switching unit and a second switching unit connected in series between the first power supply terminal and the second power supply terminal; a third switching unit and a fourth switching unit connected in series between the first power supply terminal and the ground terminal, wherein the control ends of the first switching unit, the third switching unit and the fourth switching unit are coupled to the second power supply terminal, and the control end of the second switching unit is coupled to the intermediate node B between the third switching unit and the fourth switching unit, the intermediate node C between the first switching unit and the second switching unit provides a third power supply voltage.

8. The output driving circuit according to claim 7, wherein the second connection end of the first switching unit is coupled to the first power supply terminal, the first connection end of the first switching unit is coupled to the intermediate node C, the second connection end of the second switching unit is coupled to the second power supply terminal, and the first connection end of the second switching unit is coupled to the intermediate node C, the first connection end of the third switching unit is coupled to the first power supply terminal, the second connection end of the third switching unit is coupled to the intermediate node B, the first connection end of the fourth switching unit is coupled to the second power supply terminal, and the second connection end of the fourth switching unit is coupled to the intermediate node B, the first switching unit, the second switching unit, and the third switching unit are PMOS transistors. The gate of the PMOS transistor is the control end, the source of the PMOS transistor is the first connection end of each switching unit, and the drain of the PMOS transistor is the second connection end of each switching unit, the fourth switching unit is an NMOS transistor. The gate of the NMOS transistor is the control end, the source of the NMOS transistor is the first connection end of the fourth switching unit, and the drain of the NMOS transistor is the second connection end of the fourth switching unit.

9. The output driving circuit according to claim 7, wherein The power supply selection circuit further includes: a first resistor connected in series between the first power supply terminal and the third switching unit; a second resistor connected in series between the first power supply terminal and the first switching unit.

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