Semiconductor device structure capable of avoiding metal diffusion in annealing process

Abstract

The utility model provides a semiconductor device structure capable of avoiding metal diffusion in an annealing process. The semiconductor device structure comprises a substrate, a gallium nitride layer, an aluminum gallium nitride layer, a dielectric layer, a titanium metal layer, an aluminum metal layer and a titanium nitride layer. The gallium nitride layer is connected to the upper end of the substrate, and the aluminum gallium nitride layer is connected to the upper end of the gallium nitride layer. The dielectric layer is connected to the upper end of the aluminum gallium nitride layer, and a plurality of grooves are formed in the dielectric layer. The titanium metal layer is arranged in the groove of the dielectric layer, the titanium metal layer is used for forming metal transition, and the titanium metal layer protrudes out of the groove. And the aluminum metal layer is positioned at the upper end of the titanium metal layer and is connected with the titanium metal layer. The aluminum metal layers and the titanium metal layers form aluminum-titanium stacked metal layers, and a metal etching groove is formed between every two adjacent aluminum-titanium stacked metal layers. The metal etching groove is located at the upper end of the dielectric layer, and the titanium nitride layer is connected to the aluminum-titanium stacked metal layer and the dielectric layer.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, and particularly relates to a semiconductor device structure that can avoid metal diffusion during the annealing process. Background Art

[0002] In modern life, aluminum is widely used as a semiconductor wiring material due to its simple preparation and good electrical conductivity. In order to achieve the transition between non-metallic materials and metallic materials, materials such as titanium or cobalt can be coated on the contact surface first to form a silicide contact structure. In addition, the metal barrier layer can also protect the components from damage in each process. During the preparation process of semiconductor gallium nitride devices, in order to make the metal and the semiconductor form a good contact and reduce the contact resistance, usually after the metal pattern etching is completed, a one-step high-temperature rapid annealing is used for alloying treatment. For the metal titanium, the melting point of titanium is 1668 °C, so 850 °C is a commonly used effective alloy annealing temperature. The melting point of aluminum is about 660 °C. Using 850 °C for alloy annealing will exceed the melting point of aluminum, and aluminum is very likely to undergo lateral diffusion. The lateral diffusion of aluminum will cause the distance between metal wirings to become smaller, thus making the semiconductor device prone to leakage or even short-circuit risks.

[0003] Therefore, it is necessary to provide a semiconductor device structure that can avoid metal diffusion during the annealing process to solve the above technical problems. Summary of the Utility Model

[0004] The utility model provides a semiconductor device structure that can avoid metal diffusion during the annealing process, effectively solving the technical problem that aluminum metal is prone to lateral diffusion during the annealing process of semiconductor devices.

[0005] The utility model provides a semiconductor device structure that can avoid metal diffusion during the annealing process, which includes,

[0006] A substrate;

[0007] A gallium nitride layer, located at the upper end of the substrate and connected to the substrate;

[0008] An aluminum gallium nitride layer, located at the upper end of the gallium nitride layer and connected to the gallium nitride layer;

[0009] A dielectric layer, located at the upper end of the aluminum gallium nitride layer and connected to the aluminum gallium nitride layer. A plurality of grooves are provided on the dielectric layer;

[0010] A titanium metal layer, arranged in the grooves of the dielectric layer for forming a metal transition; wherein the titanium metal layer protrudes from the grooves;

[0011] An aluminum metal layer, located at the upper end of the titanium metal layer and connected to the titanium metal layer;

[0012] Among them, the aluminum metal layer and the titanium metal layer form an aluminum-titanium stacked metal layer, and a metal etching groove is provided between two adjacent aluminum-titanium stacked metal layers, and the metal etching groove is located at the upper end of the dielectric layer;

[0013] A titanium nitride layer is connected to the aluminum-titanium stacked metal layer and the dielectric layer.

[0014] Furthermore, the titanium nitride layer includes a connecting portion and an extending portion that are connected to each other. The connecting portion is in a lid shape and wraps around the aluminum-titanium stacked metal layer, and the connecting portion is connected to the aluminum-titanium stacked metal layer; the extending portion is located at both ends of the connecting portion, and the extending portion is connected to the dielectric layer, and there is a gap between two adjacent titanium nitride layers.

[0015] Furthermore, a limiting groove is provided in the middle of the titanium metal layer. The aluminum metal layer includes a limiting portion and a protruding portion that are connected to each other. The limiting portion is connected to the limiting groove, and the protruding portion protrudes from the limiting groove for stable connection between the titanium metal layer and the aluminum metal layer.

[0016] Furthermore, the width of the protruding portion is greater than the width of the limiting portion, which is used to increase the coverage area of the aluminum metal layer so as to effectively improve the conductivity of the semiconductor device.

[0017] Furthermore, the thickness of the titanium nitride layer is 200 Å - 1000 Å.

[0018] A semiconductor device structure that can avoid metal diffusion during the annealing process, which includes,

[0019] A substrate;

[0020] A gallium nitride layer is located at the upper end of the substrate and is connected to the substrate;

[0021] An aluminum gallium nitride layer is located at the upper end of the gallium nitride layer and is connected to the gallium nitride layer;

[0022] A dielectric layer is located at the upper end of the aluminum gallium nitride layer and is connected to the aluminum gallium nitride layer. A plurality of grooves are provided on the dielectric layer;

[0023] A titanium metal layer is provided in the groove of the dielectric layer for forming a metal transition; wherein the titanium metal layer protrudes from the groove;

[0024] An aluminum metal layer is connected to the upper end of the titanium metal layer and is connected to the titanium metal layer;

[0025] Among them, the aluminum metal layer and the titanium metal layer form an aluminum-titanium stacked metal layer, and a metal etching groove is provided between two adjacent aluminum-titanium stacked metal layers, and the metal etching groove is located at the upper end of the dielectric layer;

[0026] An aluminum nitride layer is connected to the metal etching groove and the aluminum metal layer.

[0027] Furthermore, the aluminum nitride layer includes a connecting portion and an extending portion that are connected to each other. The connecting portion is in a groove shape and is connected to the bottom wall and the side wall of the metal etching groove; the extending portions are located at both ends of the connecting portion, and the extending portions are connected to the aluminum metal layer, and a gap is provided between two adjacent aluminum nitride layers.

[0028] Furthermore, a limiting groove is provided in the middle of the titanium metal layer. The aluminum metal layer includes a limiting portion and a protruding portion that are connected to each other. The limiting portion is connected to the limiting groove, and the protruding portion protrudes out of the limiting groove for the titanium metal layer and the aluminum metal layer to be stably connected.

[0029] Furthermore, the width of the protruding portion is greater than the width of the limiting portion, which is used to increase the coverage area of the aluminum metal layer so as to effectively improve the conductivity of the semiconductor device.

[0030] Furthermore, the thickness of the aluminum nitride layer is 100 Å - 500 Å.

[0031] Compared with the prior art, the beneficial effects of the present utility model are as follows: The present utility model provides a semiconductor device structure that can avoid metal diffusion during the annealing process. The semiconductor device structure is provided with a titanium nitride layer or an aluminum nitride layer. The melting point of titanium nitride is 2947 °C, so the titanium nitride can withstand high temperatures. The titanium nitride layer can be used as a protective layer to wrap the aluminum metal layer, and then the titanium nitride layer protects the aluminum metal layer. When performing high-temperature alloy annealing at 850 °C, the titanium nitride layer can block the diffusion of the aluminum metal layer, so the aluminum metal layer will not undergo lateral diffusion. The melting point of aluminum nitride is 2500 °C, so the aluminum nitride can withstand high temperatures. The aluminum nitride layer can be used as a protective layer on the bottom wall and the side wall of the metal etching groove, and then the aluminum nitride layer protects the aluminum metal layer. When performing high-temperature alloy annealing at 850 °C, the aluminum nitride layer can block the diffusion of the aluminum metal layer, so the aluminum metal layer will not undergo lateral diffusion. It effectively solves the technical problem that the aluminum metal is prone to lateral diffusion during the annealing process of the semiconductor device. The semiconductor device structure meets the annealing process and will not undergo metal lateral diffusion, so the semiconductor device structure meets the process setting requirements. Therefore, the risk of leakage or even short circuit during the use of the semiconductor device is relatively low. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following briefly introduces the drawings required for use in the embodiments. The drawings in the following description are only the corresponding drawings of some embodiments of the present utility model.

[0033] Figure 1 The following is a schematic structural diagram of the first embodiment of the semiconductor device structure that can avoid metal diffusion during the annealing process according to the present utility model.

[0034] Figure 2 The following is a schematic structural diagram of the second embodiment of the semiconductor device structure that can avoid metal diffusion during the annealing process according to the present utility model.

[0035] In the figures, 10, semiconductor device structure; 11, substrate; 12, gallium nitride layer; 13, aluminum gallium nitride layer; 14, dielectric layer; 141, groove; 15, titanium metal layer; 151, limiting groove; 16, aluminum metal layer; 161, limiting portion; 162, protruding portion; 17, titanium nitride layer; 171, connecting portion; 172, extending portion; 18, metal etching groove;

[0036] 20, semiconductor device structure; 21, substrate; 22, gallium nitride layer; 23, aluminum gallium nitride layer; 24, dielectric layer; 241, groove; 25, titanium metal layer; 251, limiting groove; 26, aluminum metal layer; 261, limiting portion; 262, protruding portion; 27, aluminum nitride layer; 271, connecting portion; 272, extending portion; 28, metal etching groove. Detailed implementation manners

[0037] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present utility model.

[0038] The directional terms mentioned in the present utility model, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", "top" and "bottom", etc., are only with reference to the orientation of the accompanying drawings. The directional terms used are for explaining and understanding the present utility model, rather than for limiting the present utility model.

[0039] The terms "first", "second", etc. in the present utility model are only for descriptive purposes, and cannot be understood as indicating or implying relative importance, nor as a limitation on the sequence.

[0040] In the figures, units with similar structures are denoted by the same reference numerals.

[0041] Please refer to Figure 1 , the following is a detailed description of the specific structure of the first embodiment of the semiconductor device structure 10 that can avoid metal diffusion during the annealing process:

[0042] The present utility model provides a semiconductor device structure 10 that can avoid metal diffusion during the annealing process. The semiconductor device structure 10 includes a substrate 11, a gallium nitride layer 12, an aluminum gallium nitride layer 13, a dielectric layer 14, a titanium metal layer 15, an aluminum metal layer 16, and a titanium nitride layer 17. The gallium nitride layer 12 is located at the upper end of the substrate 11 and is connected to the substrate 11. The aluminum gallium nitride layer 13 is located at the upper end of the gallium nitride layer 12 and is connected to the gallium nitride layer 12. The dielectric layer 14 is located at the upper end of the aluminum gallium nitride layer 13 and is connected to the aluminum gallium nitride layer 13. A plurality of grooves 141 are provided on the dielectric layer 14. The titanium metal layer 15 is disposed in the grooves 141 of the dielectric layer 14 and can be used to form a metal transition. Moreover, the titanium metal layer 15 protrudes from the grooves 141. The aluminum metal layer 16 is located at the upper end of the titanium metal layer 15 and is connected to the titanium metal layer 15. Among them, the aluminum metal layer 16 and the titanium metal layer 15 form an aluminum-titanium stacked metal layer. A metal etching groove 18 is provided between two adjacent aluminum-titanium stacked metal layers, and the metal etching groove 18 is located at the upper end of the dielectric layer 14. The titanium nitride layer 17 is connected to the aluminum-titanium stacked metal layer and the dielectric layer 14, and the thickness of the titanium nitride layer 17 is 200 Å - 1000 Å.

[0043] Please refer to Figure 1 , the titanium nitride layer 17 includes a connecting portion 171 and an extending portion 172 that are connected to each other, and the connecting portion 171 is in a cap shape. The connecting portion 171 wraps around the aluminum-titanium stacked metal layer and is connected to the aluminum-titanium stacked metal layer. The extending portions 172 are located at both ends of the connecting portion 171 and are connected to the dielectric layer 14, and there is a gap between two adjacent titanium nitride layers 17. The melting point of titanium nitride is 2947 °C, so the titanium nitride can withstand high temperatures. The titanium nitride layer 17 can be used as a protective layer to wrap around the aluminum metal layer 16, and thus the titanium nitride layer 17 protects the aluminum metal layer 16. When performing an 850 °C alloy annealing at high temperature, the titanium nitride layer 17 can block the diffusion of the aluminum metal layer 16, so the aluminum metal layer 16 will not undergo lateral diffusion. The semiconductor device structure 10 meets the annealing process requirements and does not have metal lateral diffusion, so the semiconductor device structure 10 meets the process setting requirements.

[0044] Please refer to Figure 1, a limiting groove 151 is provided in the middle of the titanium metal layer 15. The aluminum metal layer 16 includes a limiting portion 161 and a protruding portion 162 that are connected to each other. The limiting portion 161 is connected to the limiting groove 151, and the protruding portion 162 protrudes from the limiting groove 151. Since the titanium metal layer 15 and the aluminum metal layer 16 are connected through the limiting groove 151 and the limiting portion 161, the titanium metal layer 15 and the aluminum metal layer 16 are firmly connected. The width of the protruding portion 162 is greater than the width of the limiting portion 161. Therefore, the aluminum metal layer 16 has a large covering area, and thus can effectively improve the conductivity of the semiconductor device.

[0045] The manufacturing process of the first embodiment of the present utility model is as follows: First, a user provides a substrate 11, and the user sets a gallium nitride layer 12 on the upper end of the substrate 11. Then, the user sets an aluminum gallium nitride layer 13 on the upper end of the gallium nitride layer 12. The user sets a dielectric layer 14 on the upper end of the aluminum gallium nitride layer 13, and the user sets a titanium metal layer 15 on the groove 141 of the dielectric layer 14 to form a metal transition. The user connects the limiting portion 161 of the aluminum metal layer 16 to the limiting groove 151 of the titanium metal layer 15, and the protruding portion 162 of the aluminum metal layer 16 protrudes from the limiting groove 151. Therefore, the aluminum metal layer 16 and the titanium metal layer 15 form an aluminum-titanium stacked metal layer. Moreover, a metal etching groove 18 is provided between two adjacent aluminum-titanium stacked metal layers. Then, the user connects a titanium nitride layer 17 to the aluminum-titanium stacked metal layer and the dielectric layer 14. The user can first perform a high-temperature alloy annealing operation at 850 °C on the semiconductor device structure 10, and the user can then perform a secondary photolithography and metal etching operation on the titanium nitride layer 17. Or, the user can first perform a secondary photolithography and metal etching operation on the titanium nitride layer 17, and then the user performs a high-temperature alloy annealing operation at 850 °C on the semiconductor device structure 10. Subsequently, the connecting portion 171 of the titanium nitride layer 17 wraps around the aluminum-titanium stacked metal layer, and the extending portions 172 at both ends of the connecting portion 171 are connected to the dielectric layer 14, and there is a gap between two adjacent titanium nitride layers 17. Thus, the user can manufacture the semiconductor device structure 10 of the first embodiment.

[0046] Please refer to Figure 2 , the following is a detailed description of the specific structure of the second embodiment of the semiconductor device structure 20 that can avoid metal diffusion during the annealing process:

[0047] The present utility model provides a semiconductor device structure 20 that can avoid metal diffusion during the annealing process. The semiconductor device structure 20 includes a substrate 21, a gallium nitride layer 22, an aluminum gallium nitride layer 23, a dielectric layer 24, a titanium metal layer 25, an aluminum metal layer 26, and a titanium nitride layer. The gallium nitride layer 22 is located at the upper end of the substrate 21 and is connected to the substrate 21. The aluminum gallium nitride layer 23 is located at the upper end of the gallium nitride layer 22 and is connected to the gallium nitride layer 22. The dielectric layer 24 is located at the upper end of the aluminum gallium nitride layer 23 and is connected to the aluminum gallium nitride layer 23. A plurality of grooves 241 are provided on the dielectric layer 24. The titanium metal layer 25 is disposed in the grooves 241 of the dielectric layer 24 and is used to form a metal transition. Moreover, the titanium metal layer 25 protrudes from the grooves 241. The aluminum metal layer 26 is connected to the upper end of the titanium metal layer 25 and is connected to the titanium metal layer 25. Among them, the aluminum metal layer 26 and the titanium metal layer 25 form an aluminum-titanium stacked metal layer. A metal etching groove 28 is provided between two adjacent aluminum-titanium stacked metal layers, and the metal etching groove 28 is located at the upper end of the dielectric layer 24. The aluminum nitride layer 27 is connected to the metal etching groove 28 and the aluminum metal layer 26, and the thickness of the aluminum nitride layer 27 is 100 Å - 500 Å.

[0048] Please refer to Figure 2 , the aluminum nitride layer 27 includes a connecting portion 271 and an extending portion 272 that are connected to each other, and the connecting portion 271 is in a groove shape. The connecting portion 271 is connected to the bottom wall and the side wall of the metal etching groove 28, and the extending portion 272 is located at both ends of the connecting portion 271. The extending portion 272 is connected to the aluminum metal layer 26, and a gap is provided between two adjacent aluminum nitride layers 27. The melting point of aluminum nitride is 2500 °C, so the aluminum nitride can withstand high temperatures. The aluminum nitride layer 27 can be used as a protective layer and is disposed on the bottom wall and the side wall of the metal etching groove 28. Furthermore, the aluminum nitride layer 27 protects the aluminum metal layer 26. During the high-temperature alloy annealing at 850 °C, the titanium nitride layer can block the diffusion of the aluminum metal layer 26, so the aluminum metal layer 26 will not undergo lateral diffusion. The semiconductor device structure 20 meets the annealing process and does not undergo metal lateral diffusion. Therefore, the semiconductor device structure 20 meets the process setting requirements.

[0049] Please refer to Figure 2 , a limiting groove 251 is provided in the middle of the titanium metal layer 25. The aluminum metal layer 26 includes a limiting portion 261 and a protruding portion 262 that are connected to each other. The limiting portion 261 is connected to the limiting groove 251, and the protruding portion 262 protrudes from the limiting groove 251. Since the titanium metal layer 25 and the aluminum metal layer 26 are connected through the limiting groove 251 and the limiting portion 261, the titanium metal layer 25 and the aluminum metal layer 26 are firmly connected. The width of the protruding portion 262 is greater than the width of the limiting portion 261. Therefore, the aluminum metal layer 26 has a large coverage area, and thus can effectively improve the conductivity of the semiconductor device.

[0050] The manufacturing process of the second embodiment of the present utility model is as follows: First, the user provides a substrate 21, and the user sets a gallium nitride layer 22 on the upper end of the substrate 21. Then, the user sets an aluminum gallium nitride layer 23 on the upper end of the gallium nitride layer 22. The user sets a dielectric layer 24 on the upper end of the aluminum gallium nitride layer 23, and the user sets a titanium metal layer 25 on the groove 241 of the dielectric layer 24 to form a metal transition. The user connects the limiting part 261 of the aluminum metal layer 26 with the limiting groove 251 of the titanium metal layer 25, and the protruding part 262 of the aluminum metal layer 26 protrudes from the limiting groove 251. Therefore, the aluminum metal layer 26 and the titanium metal layer 25 form an aluminum-titanium stacked metal layer. Moreover, a metal etching groove 28 is provided between two adjacent aluminum-titanium stacked metal layers. Then, the user connects the aluminum nitride layer 27 to the metal etching groove 28 and the aluminum metal layer 26. The user can first perform a high-temperature alloy annealing operation at 850 °C on the semiconductor device structure 20, and then the user can perform secondary photolithography and metal etching operations on the aluminum nitride layer 27. Or, the user can first perform secondary photolithography and metal etching operations on the aluminum nitride layer 27, and then the user performs a high-temperature alloy annealing operation at 850 °C on the semiconductor device structure 20. Subsequently, the connecting part 271 of the aluminum nitride layer 27 is connected to the bottom wall and the side wall of the metal etching groove 28, and the extending parts 272 at both ends of the connecting part 271 are connected to the aluminum metal layer 26, and a gap is provided between two adjacent aluminum nitride layers 27. Thus, the user can fabricate the semiconductor device structure 20 of this second embodiment.

[0051] The present utility model provides a semiconductor device structure that can avoid metal diffusion during the annealing process. The semiconductor device structure is provided with a titanium nitride layer or an aluminum nitride layer. The melting point of titanium nitride is 2947 °C, so the titanium nitride can withstand high temperatures. The titanium nitride layer can be used as a protective layer to wrap the aluminum metal layer, and thus the titanium nitride layer protects the aluminum metal layer. When performing a high-temperature alloy annealing at 850 °C, the titanium nitride layer can block the diffusion of the aluminum metal layer, so the aluminum metal layer will not undergo lateral diffusion. The melting point of aluminum nitride is 2500 °C, so the aluminum nitride can withstand high temperatures. The aluminum nitride layer can be used as a protective layer on the bottom wall and the side wall of the metal etching groove, and thus the aluminum nitride layer protects the aluminum metal layer. When performing a high-temperature alloy annealing at 850 °C, the aluminum nitride layer can block the diffusion of the aluminum metal layer, so the aluminum metal layer will not undergo lateral diffusion. It effectively solves the technical problem that the aluminum metal is prone to lateral diffusion during the annealing process of the semiconductor device. The semiconductor device structure satisfies the annealing process and will not undergo metal lateral diffusion, so the semiconductor device structure meets the process setting requirements. Therefore, the risk of leakage or even short circuit during the use of the semiconductor device is relatively low.

[0052] In summary, although the present utility model has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present utility model. Those of ordinary skill in the art can make various changes and modifications without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the scope defined by the claims.

Claims

1. A semiconductor device structure capable of avoiding metal diffusion during the annealing process, characterized in that, It includes, a substrate; a gallium nitride layer, located at the upper end of the substrate and connected to the substrate; a gallium aluminum nitride layer, located at the upper end of the gallium nitride layer and connected to the gallium nitride layer; a dielectric layer, located at the upper end of the gallium aluminum nitride layer and connected to the gallium aluminum nitride layer, with a plurality of grooves provided on the dielectric layer; a titanium metal layer, disposed in the grooves of the dielectric layer for forming a metal transition; wherein the titanium metal layer protrudes from the grooves; an aluminum metal layer, located at the upper end of the titanium metal layer and connected to the titanium metal layer; wherein, the aluminum metal layer and the titanium metal layer form an aluminum-titanium stacked metal layer, and a metal etching groove is provided between adjacent two aluminum-titanium stacked metal layers, and the metal etching groove is located at the upper end of the dielectric layer; a titanium nitride layer, connected to the aluminum-titanium stacked metal layer and the dielectric layer.

2. The semiconductor device structure capable of avoiding metal diffusion during the annealing process according to claim 1, wherein The titanium nitride layer includes a connecting portion and an extending portion connected to each other. The connecting portion is in a cap shape and wraps on the aluminum-titanium stacked metal layer and is connected to the aluminum-titanium stacked metal layer; the extending portion is located at both ends of the connecting portion and is connected to the dielectric layer, and a gap is provided between adjacent two titanium nitride layers.

3. The semiconductor device structure capable of avoiding metal diffusion during the annealing process according to claim 1, wherein A limiting groove is provided in the middle of the titanium metal layer. The aluminum metal layer includes a limiting portion and a protruding portion connected to each other. The limiting portion is connected to the limiting groove, and the protruding portion protrudes from the limiting groove.

4. The semiconductor device structure capable of avoiding metal diffusion during the annealing process according to claim 3, characterized in that, The width of the protruding portion is greater than the width of the limiting portion.

5. The semiconductor device structure capable of avoiding metal diffusion during the annealing process according to claim 1, wherein The thickness of the titanium nitride layer is 200 Å - 1000 Å.

6. A semiconductor device structure that can avoid metal diffusion during the annealing process, characterized in that, It includes, a substrate; a gallium nitride layer, located at the upper end of the substrate and connected to the substrate; a gallium aluminum nitride layer, located at the upper end of the gallium nitride layer and connected to the gallium nitride layer; a dielectric layer, located at the upper end of the gallium aluminum nitride layer and connected to the gallium aluminum nitride layer, with a plurality of grooves provided on the dielectric layer; a titanium metal layer, disposed in the grooves of the dielectric layer for forming a metal transition; wherein the titanium metal layer protrudes from the grooves; an aluminum metal layer, connected to the upper end of the titanium metal layer and connected to the titanium metal layer; wherein, the aluminum metal layer and the titanium metal layer form an aluminum-titanium stacked metal layer, and a metal etching groove is provided between adjacent two aluminum-titanium stacked metal layers, and the metal etching groove is located at the upper end of the dielectric layer; an aluminum nitride layer, connected to the metal etching groove and the aluminum metal layer.

7. The semiconductor device structure capable of avoiding metal diffusion during annealing according to claim 6, wherein The aluminum nitride layer includes a connecting portion and an extending portion connected to each other. The connecting portion is in a groove shape and is connected to the bottom wall and side wall of the metal etching groove; the extending portion is located at both ends of the connecting portion and is connected to the aluminum metal layer, and a gap is provided between adjacent two aluminum nitride layers.

8. The semiconductor device structure capable of avoiding metal diffusion during annealing according to claim 6, characterized in that, A limiting groove is provided in the middle of the titanium metal layer. The aluminum metal layer includes a limiting portion and a protruding portion connected to each other. The limiting portion is connected to the limiting groove, and the protruding portion protrudes from the limiting groove.

9. The semiconductor device structure capable of avoiding metal diffusion during annealing according to claim 8, wherein The width of the protruding portion is greater than the width of the limiting portion.

10. The semiconductor device structure capable of avoiding metal diffusion during the annealing process according to claim 6, characterized in that The thickness of the aluminum nitride layer is 100 Å - 500 Å.

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