Upgradable high-speed interconnection system

Abstract

The utility model discloses an upgradable high-speed interconnection system. The upgradable high-speed interconnection system comprises an FPGA (Field Programmable Gate Array) chip, an FPGA chip minimum working system, a PIN MAP package, a module, a Socket seat and a test bottom plate, the FPGA chip and the FPGA chip minimum working system are connected with the PIN MAP through PCB copper wires to form a high-speed interconnection module, and the PIN MAP of the high-speed interconnection module distributes high-speed signals, low-speed signals and power signals through reasonable layout; the external display of the high-speed interconnection module is standard Socket packaging, the high-speed interconnection module is connected with the test base plate through a Socket seat, and the test base plate comprises other required structures and interfaces except the minimum system. According to the scheme, the FPGA chip and the minimum working system of the FPGA chip are designed into the standard Socket interface module, so that the compatibility among the chips is realized.

Description

Technical Field

[0001] This application relates to the field of FPGA technology, and particularly to an upgradable high-speed interconnection system. Background Art

[0002] Various FPGAs or master control chips design products by directly soldering them onto the circuit board, resulting in a one-chip-one-board design. Updating and iterating products requires redeveloping the entire set of hardware, leading to high design difficulty, long design cycles, and high update and iteration costs.

[0003] Currently, various electronic systems, especially high-speed interconnection systems, often face difficulties in upgrading and expanding when meeting the requirements of rapid technological development. Most existing FPGA or master control chip designs adopt the direct soldering method, that is, the one-chip-one-board solution. Although this method is simple and direct, when upgrading the system, expanding functions, or performing maintenance, it often requires redesigning and developing the entire hardware system, resulting in increased costs, extended design cycles, and significantly reduced system flexibility and maintainability. In addition, due to the relatively traditional existing signal layout design, especially the failure to effectively isolate high-speed signals, low-speed signals, and power signals, signal interference is likely to occur, affecting the stability and performance of the system. Therefore, designing a high-speed interconnection module and system that supports multiple chip compatibility and has flexible upgrade and expansion capabilities has become an important requirement in the field of electronic systems. Summary of the Utility Model

[0004] Therefore, this application provides an upgradable high-speed interconnection system to solve the problem of high update and iteration costs existing in the prior art.

[0005] To achieve the above object, this application provides the following technical solutions:

[0006] An upgradable high-speed interconnection system, characterized by comprising an FPGA chip, the minimum operating system of the FPGA chip, a PIN MAP package, a module, a Socket socket, and a test circuit board;

[0007] The FPGA chip and the minimum operating system of the FPGA chip are connected to the PIN MAP through PCB copper wires to form a high-speed interconnection module. The PIN MAP of the high-speed interconnection module distributes high-speed signals, low-speed signals, and power signals through reasonable layout; the high-speed interconnection module externally shows a standard Socket package and is connected to the test circuit board through the Socket socket. The test circuit board includes other required structures and interfaces outside the minimum system.

[0008] Preferably, the PIN MAP satisfies the inclusion of the vast majority of interconnection protocols and resources. By separating the layouts of high-speed signals, low-speed signals, and power signals, it ensures that the MAP design at the bottom does not need to be changed when replacing the chip.

[0009] Preferably, the PIN layout of the high-speed signals follows the principles of optimal routing and optimal crosstalk. The high-speed differential line layouts are completely isolated to ensure that when updating and iterating to a higher-speed chip, the bottom MAP meets the signal requirements.

[0010] Preferably, the layout of the power signals is reasonably planned according to the principles of optimal power performance and reliability, while referring to the power consumption requirements to ensure the maintenance of system stability during the chip replacement process.

[0011] Preferably, by designing the FPGA or the main control chip into a standard Socket interface module, the system upgrade and expansion are realized. For the customer system upgrade, only the high-speed interconnection module needs to be replaced without replacing the test backplane;

[0012] The high-speed interconnection module is externally displayed as a standard Socket package, specifically using the standard SP3 package, and the pin arrangement is re-planned and laid out according to the internal pin map rules.

[0013] Preferably, when designing the test backplane, interfaces for future expansion requirements are reserved, which are suitable for future updated and higher-speed chips. The PCIE resources are designed as PCIE5.0 according to future expectations.

[0014] Preferably, the standard Socket interface design of the module supports the compatibility of multiple FPGAs or main control chips, and simplifies the system upgrade process through the standardized interface.

[0015] Compared with the prior art, the present application has at least the following beneficial effects:

[0016] The present application provides an upgradable high-speed interconnection system, which includes an FPGA chip, the minimum working system of the FPGA chip, a PIN MAP package, a module, a Socket socket, and a test baseboard; the FPGA chip and the minimum working system of the FPGA chip are connected to the PIN MAP through PCB copper wires to form a high-speed interconnection module, and the PIN MAP of the high-speed interconnection module distributes high-speed signals, low-speed signals, and power signals through reasonable layout; the high-speed interconnection module is externally displayed as a standard Socket package and is connected to the test baseboard through the Socket socket, and the test baseboard includes other required structures and interfaces outside the minimum system. This solution realizes the compatibility between chips by designing the FPGA chip and its minimum working system as a standard Socket interface module. This structure enables the system to be upgraded by simply replacing the high-speed interconnection module without replacing the test baseboard, reducing the cost and time of system upgrade. In addition, the reasonable PIN MAP layout ensures the reliability of signal transmission and system stability. Description of the Drawings

[0017] To more intuitively illustrate the prior art and the present application, exemplary drawings are given below. It should be understood that the specific shapes and structures shown in the drawings generally should not be regarded as limiting conditions when implementing the present application; for example, those skilled in the art are capable of making routine adjustments or further optimizations to the addition / deletion / attribution division of certain units (components), specific shapes, positional relationships, connection methods, dimensional proportional relationships, etc. based on the technical concept disclosed in the present application and the exemplary drawings.

[0018] Figure 1 It is a block diagram of the structural composition of an upgradable high-speed interconnection system provided by the present application;

[0019] Figure 2 It is a diagram of the minimum working system of the chip of an upgradable high-speed interconnection system provided by the present application;

[0020] Figure 3 It is a schematic diagram of the structure of an upgradable high-speed interconnection system provided by the present application. Detailed Description of the Embodiments

[0021] The following further details the present application through specific embodiments in conjunction with the drawings.

[0022] In the description of the present application: Unless otherwise specified, "a plurality of" means two or more. The terms "first", "second", "third", etc. in the present application are intended to distinguish the objects being referred to and do not have special significance in terms of technical connotations (for example, they should not be understood as emphasizing importance or order, etc.). Expressions such as "including", "comprising", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).

[0023] Terms such as "upper", "lower", "left", "right", "middle", etc. cited in this application are usually indications of the general relative position relationship for the convenience of intuitive understanding with reference to the attached drawings, and are not absolute limitations on the position relationship in the actual product.

[0024] Please refer to Figure 1 , this application provides an upgradable high-speed interconnection system, including an FPGA chip, the minimum working system of the FPGA chip, a PIN MAP package, a module, a Socket socket, and a test baseboard;

[0025] The FPGA chip and the minimum working system of the FPGA chip are connected to the PIN MAP through PCB copper wires to form a high-speed interconnection module. The PIN MAP of the high-speed interconnection module distributes high-speed signals, low-speed signals, and power signals through reasonable layout; the PIN MAP of the high-speed interconnection module is externally displayed as a standard Socket package and is connected to the test baseboard through a Socket socket. The test baseboard includes other required structures and interfaces outside the minimum system.

[0026] In this embodiment, the PIN MAP satisfies including the vast majority of interconnection protocols and resources. By separating the layout of high-speed signals, low-speed signals, and power signals, it is ensured that the MAP design at the bottom does not need to be changed when the chip is replaced.

[0027] In this embodiment, the PIN layout of the high-speed signals follows the principles of optimal routing and optimal crosstalk. The layout of high-speed differential lines is completely isolated to ensure that when updating and iterating to a higher-speed chip, the bottom MAP meets the signal requirements.

[0028] In this embodiment, the layout of the power signals is reasonably planned according to the principles of optimal power performance and reliability, and with reference to the power consumption requirements, to ensure the stability of the system during the chip replacement process.

[0029] In this embodiment, by designing the FPGA or the main control chip into a standard Socket interface module, the upgrade and expansion of the system are realized. For the customer system upgrade, only the high-speed interconnection module needs to be replaced without replacing the test baseboard;

[0030] The high-speed interconnection module is externally displayed as a standard Socket package, specifically using a standard SP3 package, and the pin arrangement is re-planned according to the internal pinmap rules.

[0031] In this embodiment, the test baseboard is designed with interfaces reserved for future expansion requirements, suitable for future updated higher-speed chips, and the PCIE resources are designed as PCIE5.0 according to future expectations.

[0032] In this embodiment, the standard Socket interface design of the module supports the compatibility of multiple FPGAs or master chips, and simplifies the system upgrade process through a standardized interface.

[0033] In this embodiment, by designing the FPGA chip and its minimum working system into a standard Socket interface module, the compatibility between chips is achieved. This structure enables the replacement of only the high-speed interconnection module during system upgrade without replacing the test baseboard, reducing the cost and time of system upgrade. In addition, a reasonable PIN MAP layout ensures the reliability of signal transmission and system stability.

[0034] In this embodiment, by separating the layout of high-speed signals, low-speed signals, and power supply signals, interference between signals is effectively reduced, improving the signal integrity and transmission efficiency of the system. This layout ensures that the system remains stable during high-speed operation, further enhancing the system's reliability.

[0035] In this embodiment, by optimizing the PIN layout of high-speed signals, the layout of high-speed differential lines is isolated, ensuring that when replacing a chip with a higher speed rate, the bottom PIN MAP design can still meet the signal transmission requirements. This improves the scalability of the system and makes hardware upgrade more convenient.

[0036] In this embodiment, by optimizing the layout of power supply signals according to the chip power consumption, it can ensure that the circuit remains stable and reliable during the process of chip replacement. This optimized design further improves the durability and long-term performance of the system.

[0037] In this embodiment, by designing the FPGA or master chip as a standard Socket interface module, the upgrade and expansion of the system become more flexible. Users only need to replace the module instead of the entire system, thereby reducing the upgrade cost and shortening the upgrade cycle.

[0038] When designing the test baseboard of this embodiment, future possible expansion interfaces are reserved, enabling the system to adapt to the requirements of future higher-speed rate chips, such as PCIE5.0. This reserved design improves the scalability of the system and ensures that the baseboard does not need to be redesigned and replaced when updating the chip in the future.

[0039] In this embodiment, through the standardized Socket interface design, the compatibility of multiple FPGAs or master chips is achieved, simplifying the system upgrade process. This standardized design reduces the complexity of system integration and improves the maintainability of the system, making chip replacement and upgrade more efficient.

[0040] The technical solution of this application, through modular design, signal separation layout, and standardized interfaces, not only realizes the flexible upgrade and expansion of the system, but also improves the signal integrity and reliability of the system, greatly reducing the costs of hardware replacement and maintenance.

[0041] As Figures 1-3 shown, this embodiment provides an upgradable high-speed interconnection system, which includes chips such as FPGAs, the minimum operating system of the chips, PIN MAP packaging, modules, Socket connectors, and test substrates and systems.

[0042] The FPGA chip and its minimum operating system are connected to the PIN MAP through PCB copper wires to form a high-speed interconnection module. (The PIN MAP meets most interconnection protocols and resources. By reasonably arranging and distributing various signals such as high-speed, low-speed, and power supplies, it will not change with the replacement of the chip, unless the requirements of the latest chip resources cannot be met. For example: high-speed IOs are reasonably distributed at the optimal wire-out positions, and differential lines are completely isolated, which can ensure that the bottom map is fully satisfied when updating and iterating to a higher-speed chip; the same is true for power supplies. When designing the bottom power supply layout, we determine the optimal layout based on the layout planning results of numerous chips and the size and power consumption of the chips, and can optimize the performance and reliability of the circuit.)

[0043] The high-speed interconnection module externally shows a standard Socket package and is connected to the test substrate through a Socket connector to form a system. We use standard SP3 and SP5 packages and re-plan the layout of the pin arrangements according to the internal pin map rules.

[0044] The test substrate includes all required structures and interfaces other than the minimum system.

[0045] By designing various FPGAs or main control chips into standard socket interface modules, the compatibility between chips is realized. For the customer system upgrade, only the module needs to be upgraded, greatly reducing the cost. At the same time, by carefully separating the layouts of high-speed, low-speed, and power pins, a high-efficiency and high-success-rate PCB design is achieved, reducing the design cycle and further reducing the cost, and supporting future upgrade requirements.

[0046] This embodiment adopts a standardized Socket interface design:

[0047] Adopting a standardized socket interface design supports the compatibility of multiple FPGAs or main control chips.

[0048] Through the standardized interface, the system upgrade and replacement processes are simplified.

[0049] Separation layout of high-speed, low-speed, and power pins:

[0050] In this embodiment, during PCB design, the layout of high-speed, low-speed, and power pins is separated to reduce signal interference and crosstalk. The layout of high-speed differential pins is planned according to principles such as optimal routing, optimal crosstalk, and the highest industry rate; the power supply is determined based on the results after a large number of layout plans, combined with power consumption, circuit performance, reliability, etc.

[0051] This embodiment improves signal integrity and system stability by optimizing the layout.

[0052] High-performance and high-efficiency PCB design:

[0053] Adopt an optimized layout design and manufacturing process to achieve high-performance and high-efficiency PCB design.

[0054] Reduce the manufacturing cost of the PCB and improve the overall performance of the system.

[0055] Modular design supporting future upgrades:

[0056] Design a modular structure that supports future upgrades to ensure that the system has good scalability and flexibility.

[0057] Through modular design, it is convenient to replace and upgrade subsequent hardware.

[0058] When it is necessary to upgrade some functions of the entire system, in fact, it is to upgrade the main chip and use the chip with the latest functions. Therefore, only the high-speed interconnection module needs to be updated. The corresponding test board does not need to be replaced and can continue to be used. For example, if the PCIE resource of the main chip is 3.0 when designing the system, the test board can be designed as PCIE5.0 according to future expectations during the design of the test board. If a higher-speed PCIE5.0 chip needs to be replaced later, only the high-speed interconnection chip needs to be updated. Designing the system through the concept of local replacement can reduce costs, shorten the later upgrade development cycle, and improve the success rate, etc.

[0059] The technical features of the above embodiments can be combined arbitrarily (as long as there is no contradiction in the combination of these technical features). For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope described in this specification.

Claims

1. An upgradable high-speed interconnect system, characterized in that, It includes an FPGA chip, the minimum working system of the FPGA chip, PIN MAP packaging, a module, a Socket socket, and a test baseboard; The FPGA chip and the minimum working system of the FPGA chip are connected to the PIN MAP through PCB copper wires to form a high-speed interconnection module. The PIN MAP of the high-speed interconnection module distributes high-speed signals, low-speed signals, and power signals through reasonable layout. The PIN MAP of the high-speed interconnection module is externally displayed as a standard Socket package and is connected to the test baseboard through the Socket socket. The test baseboard includes other required structures and interfaces outside the minimum system.

2. The upgradable high-speed interconnect system according to claim 1, wherein: The PIN MAP meets most interconnection protocols and resources. By separating the layouts of high-speed signals, low-speed signals, and power signals, it ensures that the MAP design at the bottom does not need to be changed when the chip is replaced.

3. The upgradable high-speed interconnection system according to claim 1, characterized in that: The PIN layout of the high-speed signals follows the principles of optimal wire routing and optimal crosstalk. The layout of high-speed differential lines is completely isolated to ensure that the bottom MAP meets the signal requirements when updating and iterating to a higher-rate chip.

4. The upgradable high-speed interconnect system according to claim 1, wherein: The layout of the power signals is reasonably planned according to the principles of optimal power performance and reliability, and with reference to the power consumption requirements, to ensure the system stability during the chip replacement process.

5. The upgradable high-speed interconnect system according to claim 1, wherein: By designing the FPGA or the main control chip into a standard Socket interface module, the system upgrade and expansion are realized. For the customer system upgrade, only the high-speed interconnection module needs to be replaced without replacing the test baseboard; The high-speed interconnection module is externally displayed as a standard Socket package, specifically using the standard SP3 package, and the pin arrangement is re-planned according to the internal pin map rules.

6. The upgradable high-speed interconnect system according to claim 1, wherein: When designing the test baseboard, interfaces for future expansion requirements are reserved, which is suitable for future chips with higher rates. The PCIE resources are designed as PCIE5.0 according to future expectations.

7. The upgradable high-speed interconnect system according to claim 1, wherein: The standard Socket interface design of the module supports the compatibility of multiple FPGA or main control chips, and simplifies the system upgrade process through the standardized interface.

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