Field programmable gate array (FPGA) function testing device
Through the modularly designed FPGA functional testing device, serial communication and computer testing software are used to solve the problems of incomplete coverage and high cost of FPGA chip functional testing, and efficient and accurate detection results are achieved, which are suitable for secondary screening of FPGA chips.
Patent Information
- Application Number
- CN202421432301.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-21
- Publication Date
- 2025-07-22
- Estimated Expiration
- 2034-06-21
AI Technical Summary
The existing technology is difficult to fully cover FPGA chip functional testing, and the testing equipment is costly and technical requirements, making it difficult to promote in military fields such as aerospace.
A FPGA functional testing device was designed, using serial communication method, through the modular design of the base plate and core board, combined with the STM32 development board and upper computer testing software, comprehensive inspection and real-time monitoring of FPGA functions are achieved, reducing equipment costs and technical requirements of operators.
It realizes efficient and accurate detection of FPGA functions, simplifies operational processes, reduces the cost and technical requirements of testing equipment, improves detection accuracy and efficiency, and is suitable for secondary screening of various FPGA chips.
Smart Images
Figure CN223139779U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip testing, in particular to a FPGA function testing device. Background Art
[0002] With the rapid development of electronic technology, large-scale integrated chips play an important role in modern science and industry, and are one of the key technologies to promote the continuous progress and innovation in information technology, communication technology, electronic technology and other fields. Chip test data cannot fully characterize the functional performance, quality reliability and environmental adaptability of the device, making it difficult to fully guide users and market promotion.
[0003] In order to use the chip with greater confidence, especially in the military fields such as aerospace, it is necessary to conduct secondary testing and screening of domestic FPGA chips. Traditional functional testing methods are mostly assisted by ATE test equipment. These tests are mainly aimed at FPGA electrical parameters and performance parameters, and cannot cover all FPGA functional tests. In addition, because expensive test equipment is required, a large amount of economic costs are invisibly generated. Secondly, there is also a functional testing method that uses software simulation by professional technicians. This method has too high technical requirements for technicians and is limited to small-scale chip use tests. Utility Model Content
[0004] The utility model provides an FPGA function test device, which can realize real-time monitoring of comprehensive detection results of FPGA functions, so as to monitor whether the FPGA functions are normal in a convenient, fast, efficient and accurate manner, improve the accuracy and efficiency of detection, and simplify the operation, reduce the cost of test equipment, and also reduce the technical requirements of operators.
[0005] In order to achieve the above-mentioned purpose, the utility model provides the following technical solutions: an FPGA functional testing device, comprising: a base plate, the base plate is provided with a single-board computer, and a first power interface, a serial interface and a connecting socket electrically connected to the single-board computer; a core board, the core board is provided with a chip under test, and a clock module, a storage unit, a configuration circuit, a second power interface, a JTAG interface and a connector electrically connected to the chip under test, the connector is adaptably connected to the connecting socket; the serial interface communicates with a host computer, and the first power interface and the second power interface are electrically connected to their respective power modules.
[0006] Preferably, the core board is arranged parallel to and above the base plate, and is fixedly connected to the base plate via copper pillars at four corners; insulating feet are respectively provided at the bottom of the base plate corresponding to each of the copper pillars.
[0007] Preferably, the serial interface is fixedly arranged at one end of the top of the base plate, and the first power interface is fixedly arranged at the end of the top of the base plate away from the serial interface.
[0008] Preferably, the single-board computer is an STM32 development board and is connected to the center of the top of the base plate through a socket.
[0009] Preferably, the chip under test is arranged at the center of the top of the core board through a connector; the clock module, the storage unit, the configuration circuit, and the second power interface are respectively arranged at the bottom of the core board, and the second power interface corresponds to the upper part of the first power interface; the JTAG interface is located at the top of the core board.
[0010] The beneficial effects of the present invention are as follows: The device adopts serial communication. During the test, the FPGA function test data is sent to the upper computer through the serial protocol for real-time display, and the test result is judged and the data is saved. The function status is displayed in real time through the information status display bar in the upper computer. Therefore, whether it is a technician or a worker, the chip function can be conveniently and quickly tested, and the test data can be saved for data recording and analysis. The waveforms of individual functions can also be displayed, and the results can be obtained at a glance, thus simplifying the operation, reducing the cost of the test equipment, and the technical requirements of the operators. In addition, since the core board and the base plate are separately powered by DC through their respective power modules, it is ensured that the two systems will not interfere with each other, so as to improve the power supply stability of the entire system. In addition, the first power interface and the second power interface are located at the rear of the device, while the serial interface is located at the front of the device. Therefore, the cables required during the test process of the device are reasonably planned, and it is also convenient to check each cable to avoid misconnection. The single-board computer and the base plate are designed to be separable, so a dedicated single-board computer can be customized for different specifications of the chips under test. In terms of the core board, all the components except the chip under test and the JTAG interface are hidden at its bottom, so as to avoid damaging the surrounding components when replacing the chip under test, thereby improving the reliability of the test equipment. Description of the Drawings
[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0012] Figure 1 It is a side view of the overall structure of the present invention;
[0013] Figure 2Schematic diagram of the top structure of the core board of the present utility model;
[0014] Figure 3 Schematic diagram of the bottom structure of the core board of the present utility model;
[0015] Figure 4 Schematic diagram of the top structure of the bottom board of the present utility model.
[0016] In the figure: 1. Bottom board; 2. Single board computer; 3. First power interface; 4. Serial interface; 5. Connection socket; 6. Core board; 7. Chip under test; 8. Clock module; 9. Storage unit; 10. Configuration circuit; 11. Second power interface; 12. JTAG interface; 13. Connector; 14. Copper pillar; 15. Insulating foot; 16. Socket; 17. Connector. Specific embodiments
[0017] Next, the technical solutions of the present utility model will be clearly and completely described in conjunction with the accompanying drawings of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.
[0018] According to Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, an FPGA function test device includes: a bottom board 1, the bottom board 1 is provided with a single board computer 2, as well as a first power interface 3, a serial interface 4 and a connection socket 5 that are electrically connected to the single board computer 2; a core board 6, the core board 6 is provided with a chip under test 7, as well as a clock module 8, a storage unit 9, a configuration circuit 10, a second power interface 11, a JTAG interface 12 and a connector 13 that are electrically connected to the chip under test 7, and the connector 13 is adaptively connected to the connection socket 5; the serial interface 4 communicates with a host computer, and the first power interface 3 and the second power interface 11 are respectively electrically connected to their respective power modules.
[0019] Among them, a test software is installed in the host computer. The test software uses the C++ language and customizes test items according to the functional characteristics of the FPGA under test chip 7 through the Visual Studio 2020 UI design software, such as serial port self-check, SPI function, IIC function, TH function, Multiplier function, Aurora 8B10B status, Multi-port memory Controller status, LMB BRAM status, LB bus status, and FIFO status, etc., and makes the functions to be tested into a status information display template, a waveform display interface, a serial port setting interface, etc. And the test software also designs the logic function of the FPGA according to the test requirements, including real-time monitoring of the comprehensive detection results of the FPGA function, so that it is applicable to various FPGA secondary screening and monitoring processes.
[0020] Since the test software and the FPGA logic are co-designed and use the serial port communication method, during the test process, the FPGA function test data is sent to the host computer through the serial port protocol for real-time display, and the test results are judged and the data is saved. The function status is displayed in real time through the information status display bar in the host computer. Therefore, whether it is a technician or a worker, the chip function can be tested conveniently and quickly, and the test data can be saved for data recording and analysis. The waveforms of individual functions can also be displayed, and the results can be obtained at a glance, thus simplifying the operation, reducing the cost of the test equipment, and the technical requirements of the operators. In addition, since the core board 6 and the bottom board 1 are independently powered by DC through their respective power modules, it is ensured that the two systems will not interfere with each other, so as to improve the stability of the power supply of the entire system.
[0021] The core board 6 is arranged parallel to the upper part of the bottom board 1 and is fixedly connected to the bottom board 1 through the copper columns 14 at the four corners; the bottom of the bottom board 1 is respectively provided with insulating feet 15 corresponding to each of the copper columns 14.
[0022] Through this setting, the core board 6 and the bottom board 1 are fixedly connected through four copper columns 14, so as to ensure the reliability of data communication between each board card, and the insulating feet 15 at the bottom avoid the short-circuit problem caused by the contact between the printed circuit solder joints at the bottom of the bottom board 1 and metal objects.
[0023] The serial interface 4 is fixedly arranged at one end of the top of the base plate 1, and the first power supply interface 3 is fixedly arranged at the end of the top of the base plate 1 far from the serial interface 4. The single board computer 2 is an STM32 development board and is connected to the center of the top of the base plate 1 through a socket 16. The chip under test 7 is arranged at the center of the top of the core board 6 through a connector 17; the clock module 8, the storage unit 9, the configuration circuit 10, and the second power supply interface 11 are respectively arranged at the bottom of the core board 6, and the second power supply interface 11 corresponds to the upper part of the first power supply interface 3; the JTAG interface 12 is located at the top of the core board 6.
[0024] Through the above settings, the first power supply interface 3 and the second power supply interface 11 are located at the rear of the device, while the serial interface 4 is located at the front of the device. Therefore, the cables required during the testing process of the device are reasonably planned, and it is also convenient to check each cable to avoid incorrect insertion. The single board computer 2 and the base plate 1 are of a detachable design, so a dedicated single board computer 2 can be customized for different specifications of the chip under test 7. In terms of the core board 6, the rest of the components except the chip under test 7 and the JTAG interface 12 are hidden at its bottom, so as to avoid damage to the surrounding components when replacing the chip under test 7, thereby improving the reliability of the testing device.
[0025] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims
1. An FPGA functional test device, characterized in that , including: A base plate (1), on which a single-board computer (2) is provided, as well as a first power interface (3), a serial interface (4) and a connection socket (5) electrically connected to the single-board computer (2); A core board (6), on which a chip under test (7) is provided, as well as a clock module (8), a storage unit (9), a configuration circuit (10), a second power interface (11), a JTAG interface (12) and a connector (13) electrically connected to the chip under test (7), and the connector (13) is adaptively connected to the connection socket (5); The serial interface (4) communicates with a host computer, and the first power interface (3) and the second power interface (11) are respectively electrically connected to their respective power modules.
2. The FPGA function test device according to claim 1, wherein: The core board (6) is arranged parallel above the base plate (1) and is fixedly connected to the base plate (1) through copper columns (14) at four corners; insulating feet (15) are respectively provided at the bottom of the base plate (1) corresponding to each of the copper columns (14).
3. The FPGA function test device according to claim 1, characterized in that: The serial interface (4) is fixedly arranged at one end of the top of the base plate (1), and the first power interface (3) is fixedly arranged at the end of the top of the base plate (1) far from the serial interface (4).
4. The FPGA function test device according to claim 1, wherein: The single-board computer (2) is an STM32 development board and is connected to the center of the top of the base plate (1) through a socket (16).
5. The FPGA function test device according to claim 1, characterized in that: The chip under test (7) is arranged at the center of the top of the core board (6) through a connector (17); the clock module (8), the storage unit (9), the configuration circuit (10), and the second power interface (11) are respectively arranged at the bottom of the core board (6), and the second power interface (11) corresponds to the upper part of the first power interface (3); the JTAG interface (12) is located at the top of the core board (6).