NFC voltage stabilizing circuit and NFC device

Abstract

The utility model provides an NFC (near field communication) voltage stabilizing circuit and NFC equipment, and relates to the technical field of NFC, the NFC voltage stabilizing circuit comprises an NFC card reader chip, an upper computer power supply input end and a power supply isolation circuit; the output end of the power supply isolation circuit is connected with the analog power supply end of the NFC card reader chip, and the input end of the power supply isolation circuit is connected with the power supply input end of the upper computer; and the power supply isolation circuit is configured to attenuate a waveform flowing to the power supply input end of the upper computer when the NFC card reader chip is started. According to the NFC voltage stabilizing circuit and the NFC equipment, the waveform generated when the NFC module is open can be isolated through the built-in power supply isolation circuit, and the crosstalk condition caused when the NFC equipment is open is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of NFC, and in particular to an NFC voltage stabilization circuit and an NFC device. Background Art

[0002] Near Field Communication (NFC) can exchange data when in close proximity to each other, and is widely used in various scenarios such as mobile payment, electronic ticketing, access control, mobile identity recognition, anti-counterfeiting, etc. When the NFC module starts up, the internal radio frequency part of the NFC module will transmit or receive a waveform of 13.56 MHz, thereby realizing short-distance data communication. Summary of the Utility Model

[0003] The inventors of this application noticed during research that the waveform generated when the NFC module starts up will be transmitted to the host computer connected to the NFC module through relevant circuits, thereby causing crosstalk to the host computer. In view of this, the purpose of the utility model is to provide an NFC voltage stabilization circuit and an NFC device, which isolate the waveform generated when the NFC module starts up through a built-in power isolation circuit, and improve the crosstalk situation caused when the NFC device starts up.

[0004] In a first aspect, an embodiment of the utility model provides an NFC voltage stabilization circuit, which includes an NFC reader chip, a host computer power input terminal, and a power isolation circuit; the output terminal of the power isolation circuit is connected to the analog power supply terminal of the NFC reader chip, and the input terminal of the power isolation circuit is connected to the host computer power input terminal; the power isolation circuit is configured to attenuate the waveform flowing to the host computer power input terminal when the NFC reader chip starts up.

[0005] In an embodiment, the NFC voltage stabilization circuit further includes a controller; the first control terminal of the controller is connected to the host computer power input terminal; the second control terminal of the controller is connected to the analog power supply terminal of the NFC reader chip through the power isolation circuit.

[0006] In an embodiment, the controller is configured to control the power isolation circuit to start to control the start-up of the NFC reader chip according to the first instruction sent by the host computer received by the first control terminal, and control the power isolation circuit to close to control the shutdown of the NFC reader chip according to the second instruction sent by the host computer received by the first control terminal.

[0007] In an embodiment, the NFC voltage stabilization circuit further includes: a filter; wherein, the input terminal of the filter is connected to the host computer power input terminal; the output terminal of the filter is connected to the input terminal of the power isolation circuit; and / or,

[0008] The NFC voltage stabilization circuit further includes: a voltage conversion circuit; wherein, the input end of the voltage conversion circuit is connected to the power input end of the host computer; the output end of the voltage conversion circuit is connected to the digital power supply end of the NFC reader chip.

[0009] In one embodiment, the NFC voltage stabilization circuit further includes a controller, wherein,

[0010] The filter is also connected to the first power supply end of the controller; and / or,

[0011] The output end of the voltage conversion circuit is also connected to the second power supply end of the controller; and / or,

[0012] The output end of the voltage conversion circuit is also connected to the clock power supply end of the controller.

[0013] In one embodiment, the NFC voltage stabilization circuit includes a first power supply link, a second power supply link and a third power supply link;

[0014] The first power supply link includes a filter and a power isolation circuit connected to the output end of the filter. The power input end of the host computer provides a first NFC chip power supply voltage to the analog power supply end of the NFC reader chip through the first power supply link;

[0015] The second power supply link includes a filter and a voltage conversion circuit connected to the output end of the filter. The power input end of the host computer provides a second NFC chip power supply voltage to the digital power supply end of the NFC reader chip through the second power supply link and provides a first controller voltage to the controller included in the NFC voltage stabilization circuit. The control end of the controller is connected to the power isolation circuit;

[0016] In the third power supply link, the power input end of the host computer is connected to the input end of the third power supply link to provide a second controller voltage to the controller through the third power supply link.

[0017] In one embodiment, the power isolation circuit is a BOOST circuit or a DC-DC circuit.

[0018] In one embodiment, a 6-pin BOOST boost chip is provided in the power isolation circuit;

[0019] The input end of the power isolation circuit is connected to the VCC power supply input pin of the boost chip; the output end of the power isolation circuit is connected to the VOUT power supply output pin of the boost chip;

[0020] The power isolation circuit includes a boost inductor; wherein, one end of the boost inductor is connected to the input end of the power isolation circuit; the other end of the boost inductor is connected to the SW conversion pin of the boost chip;

[0021] The power isolation circuit includes a first capacitor module and a second capacitor module; one end of the first capacitor module is connected to the input end of the power isolation circuit, and the other end of the first capacitor module is connected to the GND ground pin of the boost chip; one end of the second capacitor module is connected to the output end of the power isolation circuit, and the other end of the second capacitor module is connected to the FB feedback pin of the boost chip.

[0022] The BOOST boost chip also includes an EN enable pin connected to the controller.

[0023] In one embodiment, the first capacitor module in the power isolation circuit includes a first capacitor. One end of the first capacitor is connected to the input end of the power isolation circuit, and the other end of the first capacitor is connected to the GND ground pin of the boost chip and then grounded; the first capacitor module further includes a second capacitor, and the second capacitor is connected in parallel with the first capacitor;

[0024] The second capacitor module includes a third capacitor. One end of the third capacitor is respectively connected to the VOUT power supply output pin of the boost chip and the output end of the power isolation circuit, and the other end of the third capacitor is connected to the FB feedback pin of the boost chip and then grounded; the second capacitor module further includes a fourth capacitor, and the fourth capacitor is connected in parallel with the third capacitor.

[0025] In one embodiment, the power isolation circuit includes a first resistor and a second resistor; wherein, one end of the first resistor is connected to the VOUT power supply output pin of the boost chip; the other end of the first resistor is respectively connected to the FB feedback pin of the boost chip and one end of the second resistor; the other end of the second resistor is connected to the other end of the second capacitor module and then grounded.

[0026] In a second aspect, an embodiment of the present invention provides an NFC device, which includes the NFC voltage stabilization circuit mentioned in the first aspect; alternatively, the NFC device includes a host computer and the NFC voltage stabilization circuit mentioned in the first aspect above.

[0027] An NFC voltage stabilization circuit and an NFC device provided by an embodiment of the present invention. The NFC voltage stabilization circuit includes an NFC reader chip, a host computer power input end, and a power isolation circuit; the output end of the power isolation circuit is connected to the analog power supply end of the NFC reader chip, and the input end of the power isolation circuit is connected to the host computer power input end; the power isolation circuit is configured to attenuate the waveform flowing to the host computer power input end when the NFC reader chip starts up. The NFC voltage stabilization circuit and the NFC device can isolate the waveform generated when the NFC module starts up through the built-in power isolation circuit, and improve the crosstalk situation caused when the NFC device starts up.

[0028] Other features and advantages of the present utility model will be described in the subsequent specification, and in part, will be obvious from the specification, or can be understood by implementing the present utility model. The objectives and other advantages of the present utility model are achieved and obtained by the structures specifically pointed out in the specification, claims, and drawings.

[0029] To make the above objectives, features, and advantages of the present utility model more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, details are described as follows. Description of the Drawings

[0030] To more clearly illustrate the specific embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 Schematic diagram of the structure of the first NFC voltage stabilization circuit provided by an embodiment of the present utility model;

[0032] Figure 2 Schematic diagram of the structure of the second NFC voltage stabilization circuit provided by an embodiment of the present utility model;

[0033] Figure 3 Schematic diagram of the structure of the third NFC voltage stabilization circuit provided by an embodiment of the present utility model;

[0034] Figure 4 Schematic diagram of the structure of a power isolation circuit provided by an embodiment of the present utility model;

[0035] Figure 5 Schematic diagram of the structure of an NFC device provided by an embodiment of the present utility model.

[0036] Icons:

[0037] 100 - NFC reader chip; 200 - Host computer power input terminal; 300 - Power isolation circuit; 400 - Controller; 500 - Filter; 600 - Voltage conversion circuit; 700 - Host computer. Specific Embodiments

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present utility model clearer, the technical solutions of the present utility model will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are some, but not all, of the embodiments of the present utility model. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0039] NFC near-field communication can perform data exchange when in close proximity to each other and is widely used in various scenarios such as mobile payment, electronic ticketing, access control, mobile identity recognition, and anti-counterfeiting. When the NFC module starts up, the internal radio frequency part of the NFC module will transmit or receive a waveform of 13.56 MHz and transmit it to the entire NFC device through relevant circuits, causing crosstalk. Based on this, the embodiments of the present utility model provide an NFC voltage stabilization circuit and an NFC device, which can isolate the waveform generated when the NFC module starts up through a built-in power isolation circuit, improving the crosstalk situation caused when the NFC device starts up.

[0040] To facilitate the understanding of this embodiment, first, a detailed introduction to the first NFC voltage stabilization circuit disclosed in the embodiments of the present utility model will be given, specifically as Figure 1 shown. This NFC voltage stabilization circuit includes an NFC reader chip 100 (this NFC chip is used as a reader, so it is called an "NFC reader chip"), a host computer power input terminal 200, and a power isolation circuit 300; the output terminal of the power isolation circuit 300 is connected to the analog power supply terminal of the NFC reader chip 100, and the input terminal of the power isolation circuit 300 is connected to the host computer power input terminal 200; the power isolation circuit 300 is configured to attenuate the waveform flowing to the host computer power input terminal 200 when the NFC reader chip 100 starts. Specifically, the host computer power input terminal 200 is the port through which the host computer supplies power to the NFC voltage stabilization circuit; the power isolation circuit 300 can isolate the waveform generated when the NFC reader chip 100 starts up, improving the situation where the waveform is transmitted to the upper-level NFC device, thereby achieving the attenuation of the waveform when the NFC starts through the power isolation circuit 300, and thus reducing the crosstalk of the NFC startup to the host computer.

[0041] As Figure 2 shown in the structural schematic diagram of the second NFC voltage stabilization circuit, in one implementation, the NFC voltage stabilization circuit further includes a controller 400; the first control terminal of the controller 400 is connected to the host computer power input terminal 200; the second control terminal of the controller 400 is connected to the analog power supply terminal of the NFC reader chip 100 through the power isolation circuit 300.

[0042] The controller 400 is configured to control the power isolation circuit 300 to start according to the first instruction sent by the host computer received at the first control end, so as to control the NFC card reader chip 100 to start, and control the power isolation circuit 300 to close according to the second instruction sent by the host computer received at the first control end, so as to control the NFC card reader chip 100 to close.

[0043] Specifically, the first instruction and the second instruction sent by the host computer are used to control whether the NFC card reader chip 100 starts. The first instruction is used to control the power isolation circuit 300 to start, and then control the NFC card reader chip 100 to start, so as to execute the card swiping transaction process. At the end of the transaction, the second instruction is used to control the power isolation circuit 300 to close, and then control the NFC card reader chip 100 to close, so as to further reduce the crosstalk of the NFC card reader chip to the system.

[0044] In one embodiment, the NFC voltage stabilizing circuit further includes: a filter 500; wherein, the input end of the filter 500 is connected to the host computer power input end 200; the output end of the filter 500 is connected to the power input end of the power isolation circuit 300; and / or, the NFC voltage stabilizing circuit further includes: a voltage conversion circuit 600; wherein, the input end of the voltage conversion circuit 600 is connected to the host computer power input end 200; the output end of the voltage conversion circuit 600 is connected to the digital power supply end of the NFC card reader chip 100.

[0045] The filter 500 is used to convert the input voltage of the host computer power input end 200 into a first voltage, and perform a primary voltage conversion on the input voltage of the host computer power input end 200, so as to obtain a stable first voltage. For example, the voltage input through the host computer power input end 200 generates a first voltage after passing through the filter 500.

[0046] The voltage conversion circuit 600 is mainly used to perform a further voltage conversion on the first voltage, so as to obtain a more stable second voltage for supplying power to the NFC card reader chip 100. For example, after the voltage conversion circuit 600 inputs the first voltage, a more stable second voltage is obtained, and the second voltage is less than the first voltage.

[0047] The generated second voltage is also used to supply power to the controller 400, so as to supply power to the controller 400. In one embodiment, the filter 500 is also connected to the first power supply end of the controller 400; and / or, the output end of the voltage conversion circuit 600 is also connected to the second power supply end of the controller 400; and / or, the output end of the voltage conversion circuit 600 is also connected to the clock power supply end of the controller 400. At this time, the second voltage is used to supply power to the controller 400, and at the same time, it also supplies power to the clock power supply port VRTC of the controller 400.

[0048] Such asFigure 3 Schematic diagram of the third NFC voltage regulation circuit shown. In one embodiment, the NFC voltage regulation circuit includes a first power supply link, a second power supply link, and a third power supply link. Figure 3 It is described according to connection lines of different thicknesses.

[0049] The first power supply link includes a filter Filter and a power supply isolation circuit BOOST connected to the output end of the filter Filter. The host computer power input end provides a first NFC chip power supply voltage to the analog power supply end of the NFC reader chip (NFCChip) in the form of a USB-C interface through the first power supply link.

[0050] The second power supply link includes a filter Filter and a voltage conversion circuit LDO connected to the output end of the filter Filter. The host computer power input end provides a second NFC chip power supply voltage to the digital power supply end of the NFC reader chip in the form of a USB-C interface through the second power supply link, and provides a first controller voltage to the controller MCU included in the NFC voltage regulation circuit. The control end of the controller MCU is connected to the power supply isolation circuit BOOST.

[0051] In the third power supply link, the host computer power input end is connected to the input end of the third power supply link to provide a second controller voltage to the controller through the third power supply link.

[0052] In some embodiments, the power supply isolation circuit 300 is a BOOST circuit or a DC-DC circuit. The power supply isolation circuit 300 is a boost circuit, which converts a low-voltage input into a high-voltage output through internal control and regulation of the circuit.

[0053] In some embodiments, the voltage conversion circuit can be a low-dropout linear regulator or other circuits.

[0054] Specifically, the power supply isolation circuit 300 is as Figure 4 shown. A 6-pin BOOST boost chip U is provided in the power supply isolation circuit 300; the voltage input end VIN of the power supply isolation circuit 300 is connected to the VCC power supply input pin 6 of the boost chip U; the voltage output end Vout of the power supply isolation circuit 300 is connected to the VOUT power supply output pin 5 of the boost chip U; the BOOST boost chip also includes an EN enable pin connected to the controller.

[0055] The power supply isolation circuit 300 includes a boost inductor L; wherein, one end of the boost inductor L is connected to the input end of the power supply isolation circuit 300; the other end of the boost inductor L is connected to the SW conversion pin 1 of the boost chip U;

[0056] The power isolation circuit includes a first capacitor module and a second capacitor module; one end of the first capacitor module is connected to the input end of the power isolation circuit, and the other end of the first capacitor module is connected to the GND grounding pin of the boost chip; one end of the second capacitor module is connected to the output end of the power isolation circuit, and the other end of the second capacitor module is connected to the FB feedback pin of the boost chip.

[0057] Specifically, the first capacitor module in the power isolation circuit 300 includes a first capacitor C1; wherein, one end of the first capacitor C1 is connected to the input end of the power isolation circuit 300; the other end of the first capacitor C1 is connected to the GND grounding pin 2 of the boost chip and then grounded. The first capacitor module further includes a second capacitor C2; wherein, the second capacitor C2 is connected in parallel with the first capacitor C1.

[0058] The second capacitor module includes a third capacitor C3; wherein, one end of the third capacitor C3 is respectively connected to the VOUT power supply output pin 5 of the boost chip U and the output end of the power isolation circuit 300; the other end of the third capacitor C3 is connected to the FB feedback pin 4 of the boost chip U and then grounded. The second capacitor module further includes a fourth capacitor C4; wherein, the fourth capacitor C4 is connected in parallel with the third capacitor C3.

[0059] The power isolation circuit 300 includes a first resistor R1 and a second resistor R2; wherein, one end of the first resistor R1 is connected to the VOUT power supply output pin 5 of the boost chip U; the other end of the first resistor R1 is respectively connected to the FB feedback pin 4 of the boost chip U and one end of the second resistor R2; the other end of the second resistor R2 is connected to the other end of the third capacitor C3 and then grounded.

[0060] The EN enable pin 3 of the boost chip U is connected to a relevant enable signal, which will not be elaborated here.

[0061] In the specific implementation process, the upper computer power input end is provided with a connection component including but not limited to the USB-C interface type.

[0062] Specifically, Figure 4 VIN in it is powered by the USB-C interface, which is equivalent to the voltage after filtering and regulating the VCC of the USB. The working principle is to raise the low voltage of VIN to the high voltage of VOUT through the boost chip U. For example, boost the voltage VIN of about 5v to a stable voltage of 5.1v. VOUT is filtered and given to TVDD of the NFC, that is, the power supply of the NFC transmitter. TVDD is a power supply pin at the pin of the NFC chip. By connecting the power isolation circuit to TVDD of the NFC reader, the crosstalk at the start of the NFC can be isolated.

[0063] The voltage setting is selected according to the chip power supply range. The working principle is that the greater the power supply at the start of NFC field, the greater the output power, and the greater the NFC card swiping range and the field strength. The specific scenario achieved is as follows: when using an NFC device to swipe a card, the BOOST boost chip is controlled to start boosting, and the boost process is disconnected after the NFC device finishes swiping the card.

[0064] As can be seen from the NFC voltage stabilization circuit provided in the embodiments of the present invention, the NFC voltage stabilization circuit can isolate the waveform generated at the start of the NFC field through a power isolation circuit, improving the crosstalk situation caused when the NFC device starts.

[0065] The embodiments of the present invention provide an NFC device, which includes the NFC voltage stabilization circuit mentioned in the above embodiments; or, as Figure 5 shown, the NFC device includes a host computer 700 and the NFC voltage stabilization circuit mentioned in the above embodiments; specifically, the host computer 700 is connected to the power input terminal of the host computer, and the voltage output terminal of the power isolation circuit is connected to the RF power port of the NFC chip. Specifically, the signal transmission terminal of the host computer 700 is connected to the signal transmission terminal of the controller 400 in the NFC voltage stabilization circuit through a signal line, and the control terminal of the controller 400 is connected to the EN enable port included in the BOOST boost chip provided in the power isolation circuit 300, thereby realizing the transmission of signal instructions. See the Figure 5 dashed line in

[0066] The NFC voltage stabilization circuit in the NFC device provided by the embodiments of the present invention has the same implementation principle and technical effects as those of the foregoing NFC voltage stabilization circuit embodiments. For a brief description, for the parts not mentioned in the device embodiment, reference can be made to the corresponding content in the foregoing embodiments.

[0067] In several embodiments provided in the present application, it should be understood that the disclosed systems and devices can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed mutual coupling or direct coupling or communication connection can be through some communication interfaces, and the indirect coupling or communication connection of devices or units can be in electrical, mechanical or other forms.

[0068] The unit described as a separation component may or may not be physically separated. The component shown as a unit may or may not be a physical unit, that is, it may be located in one place or distributed over multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0069] In addition, in each embodiment of the present utility model, each functional unit may be integrated in a processing unit, may exist physically alone for each unit, or two or more units may be integrated in one unit.

[0070] If the described function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of the present utility model, in essence, or the part that contributes to the prior art or a part of this technical solution can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present utility model. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes.

[0071] Finally, it should be noted that: the above-described embodiments are only specific implementation manners of the present utility model, used to illustrate the technical solutions of the present utility model, rather than limiting it. The protection scope of the present utility model is not limited thereto. Although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: any person skilled in the art within the technical scope disclosed by the present utility model can still modify the technical solutions described in the foregoing embodiments or can easily think of changes, or perform equivalent replacements for some of the technical features; and these modifications, changes, or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model and should all be covered within the protection scope of the present utility model. Therefore, the protection scope of the present utility model shall be subject to the protection scope of the claims.

Claims

1. An NFC voltage stabilization circuit, characterized in that, The NFC voltage stabilization circuit includes an NFC reader chip, a host computer power input terminal, and a power isolation circuit; the output terminal of the power isolation circuit is connected to the analog power supply terminal of the NFC reader chip, and the input terminal of the power isolation circuit is connected to the host computer power input terminal; the power isolation circuit is configured to attenuate the waveform flowing to the host computer power input terminal when the NFC reader chip starts up.

2. The NFC voltage stabilizing circuit according to claim 1, wherein The NFC voltage stabilization circuit further includes a controller; the first control terminal of the controller is connected to the host computer power input terminal; the second control terminal of the controller is connected to the analog power supply terminal of the NFC reader chip through the power isolation circuit.

3. The NFC voltage stabilization circuit according to claim 2, wherein The controller is configured to control the power isolation circuit to start up to control the startup of the NFC reader chip according to the first instruction sent by the host computer received by the first control terminal, and control the power isolation circuit to shut down to control the shutdown of the NFC reader chip according to the second instruction sent by the host computer received by the first control terminal.

4. The NFC voltage stabilization circuit according to claim 1, characterized in that, The NFC voltage stabilization circuit further includes: a filter; wherein, the input terminal of the filter is connected to the host computer power input terminal; the output terminal of the filter is connected to the input terminal of the power isolation circuit; and / or, The NFC voltage stabilization circuit further includes: a voltage conversion circuit; wherein, the input terminal of the voltage conversion circuit is connected to the host computer power input terminal; the output terminal of the voltage conversion circuit is connected to the digital power supply terminal of the NFC reader chip.

5. The NFC voltage stabilizing circuit according to claim 4, wherein The NFC voltage stabilization circuit further includes a controller, wherein, The filter is further connected to the first power supply terminal of the controller; and / or, The output terminal of the voltage conversion circuit is further connected to the second power supply terminal of the controller; and / or, The output terminal of the voltage conversion circuit is further connected to the clock power supply terminal of the controller.

6. The NFC voltage stabilizing circuit according to any one of claims 1-5, characterized in that The NFC voltage stabilization circuit includes a first power supply link, a second power supply link, and a third power supply link, The first power supply link includes a filter and the power isolation circuit connected to the output terminal of the filter, and the host computer power input terminal provides a first NFC chip power supply voltage to the analog power supply terminal of the NFC reader chip through the first power supply link; The second power supply link includes the filter and a voltage conversion circuit connected to the output terminal of the filter, and the host computer power input terminal provides a second NFC chip power supply voltage to the digital power supply terminal of the NFC reader chip and provides a first controller voltage to the controller included in the NFC voltage stabilization circuit through the second power supply link, and the control terminal of the controller is connected to the power isolation circuit; In the third power supply link, the host computer power input terminal is connected to the input terminal of the third power supply link to provide a second controller voltage to the controller through the third power supply link.

7. The NFC voltage stabilizing circuit according to any one of claims 1-5, characterized in that, The power isolation circuit is a BOOST circuit or a DC-DC circuit.

8. The NFC voltage stabilizing circuit according to any one of claims 1-5, characterized in that, A 6-pin BOOST boost chip is provided in the power isolation circuit; The input end of the power isolation circuit is connected to the VCC power supply input pin of the boost chip; the output end of the power isolation circuit is connected to the VOUT power supply output pin of the boost chip; The power isolation circuit includes a boost inductor; wherein, one end of the boost inductor is connected to the input end of the power isolation circuit; the other end of the boost inductor is connected to the SW conversion pin of the boost chip; The power isolation circuit includes a first capacitor module and a second capacitor module; one end of the first capacitor module is connected to the input end of the power isolation circuit, and the other end of the first capacitor module is connected to the GND ground pin of the boost chip; one end of the second capacitor module is connected to the output end of the power isolation circuit, and the other end of the second capacitor module is connected to the FB feedback pin of the boost chip; The BOOST boost chip further includes an EN enable pin connected to the controller.

9. The NFC voltage stabilization circuit according to claim 8, wherein, Among them, The first capacitor module in the power isolation circuit includes a first capacitor, one end of the first capacitor is connected to the input end of the power isolation circuit, and the other end of the first capacitor is connected to the GND ground pin of the boost chip and then grounded; the first capacitor module further includes a second capacitor, and the second capacitor is connected in parallel with the first capacitor; The second capacitor module includes a third capacitor, one end of the third capacitor is respectively connected to the VOUT power supply output pin of the boost chip and the output end of the power isolation circuit, and the other end of the third capacitor is connected to the FB feedback pin of the boost chip and then grounded; the second capacitor module further includes a fourth capacitor, and the fourth capacitor is connected in parallel with the third capacitor; and / or, Wherein, the power isolation circuit includes a first resistor and a second resistor; one end of the first resistor is connected to the VOUT power supply output pin of the boost chip; the other end of the first resistor is respectively connected to the FB feedback pin of the boost chip and one end of the second resistor; the other end of the second resistor is connected to the other end of the second capacitor module and then grounded.

10. An NFC device, characterized in that, The NFC device includes the NFC voltage stabilization circuit according to any one of claims 1 to 9 above; or, the NFC device includes a host computer and the NFC voltage stabilization circuit according to any one of claims 1 to 9 above.

Images