Component patch structure with optimally designed component area, FPC (Flexible Printed Circuit) and display module

Abstract

The utility model relates to an element patch structure with an optimally designed element area, a flexible printed circuit (FPC) and a display module, the element patch structure comprises an FPC element area, one or more patch selection positions are arranged in the FPC element area, the element is an alternative circuit, no gap exists between common ends of two parallel circuits of the alternative circuit, and the two parallel circuits of the alternative circuit are connected in parallel. One alternative circuit is arranged in each patch selection position; and the common end is a shared connecting line or a shared connecting point which is respectively connected with the two parallel circuits. No gap exists between the common ends of the two parallel circuits of the either-or circuit, and the structure of the either-or circuit is that the two parallel circuits share one common end or the common ends of the two parallel circuits are stacked up and down. According to the utility model, by optimizing the element connection mode, the patch area is reduced, the patch selection position is prevented from exceeding the required FPC element area range, and the interference with the complete machine structure of a terminal product needing to be matched is avoided.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a component patch structure, an FPC and a display module with an optimized design of a component area. Background Art

[0002] In the design of FPC, in order to ensure that components can be accurately mounted, patch selection positions need to be reserved in the component area. The design of these reserved positions is to adapt to the possible deviations in the automated patching process, ensuring that the components can be correctly aligned and firmly pasted on the FPC.

[0003] See Figure 1 , in some display modules for multiple application scenarios, patch selection positions for a one - in - two circuit are reserved in the FPC component area 1. The one - in - two circuit needs to reserve two patch selection positions 2, that is, the two parallel circuits of the one - in - two circuit are respectively arranged in the two patch selection positions 2. Among them, the common terminals 31 of the two parallel circuits are arranged at intervals, resulting in the two patch selection positions 2 being likely to exceed the range of the FPC component area 1 required by the customer, causing interference with the overall structure of the terminal product to be matched.

[0004] In response to this, it is necessary to adopt a more refined layout design and use smaller components, but this may involve changing the component model or choosing a more compact package form, which conflicts with the set process requirements. Therefore, there is an urgent need for a solution to compress the area of the patch selection position area without changing the component model. Summary of the Utility Model

[0005] Aiming at the deficiencies of the prior art, the utility model provides a component patch structure, an FPC and a display module with an optimized design of a component area. By optimizing the connection mode of components, the patch area is reduced, so that the components can be correctly aligned and firmly pasted on the FPC, preventing the patch selection position from exceeding the required range of the FPC component area and avoiding interference with the overall structure of the terminal product to be matched.

[0006] The technical solution adopted by the utility model is as follows:

[0007] The utility model provides a component patch structure with an optimized design of a component area, including an FPC component area, in which one or more patch selection positions are provided. The component is a one - in - two circuit, and there is no gap between the common terminals of the two parallel circuits of the one - in - two circuit, so that one of the one - in - two circuits is arranged in each of the patch selection positions; the common terminal is a shared connection line or a shared connection point respectively connected to the two parallel circuits.

[0008] As a further improvement of the above - mentioned technical solution:

[0009] There is no gap between the common terminals of the two parallel circuits of the one - of - two circuit, and its structure is that the two parallel circuits share a common terminal.

[0010] There is no gap between the common terminals of the two parallel circuits of the one - of - two circuit, and its structure is that the common terminals of the two parallel circuits are stacked vertically.

[0011] Conductive adhesive is provided on the contact surface where the common terminals of the two parallel circuits are stacked vertically for bonding.

[0012] Welding is performed on the contact surface where the common terminals of the two parallel circuits are stacked vertically.

[0013] The FPC component area is rectangular, and the multiple patch selection positions are arranged at intervals along the length direction of the rectangle.

[0014] The width of the patch selection position is not greater than the width of the FPC component area.

[0015] Multiple FPC component areas are provided.

[0016] The present utility model also provides an FPC, including the component patch structure with optimized design of the component area.

[0017] The present utility model also provides a display module, including the above - mentioned FPC.

[0018] The beneficial effects of the present utility model are as follows:

[0019] Since there is a common terminal in the one - of - two circuit, in the prior art, the common terminals of the two circuits in the one - of - two circuit are usually arranged at intervals, resulting in occupying two patch reserved positions, and the width of the two patch reserved positions is likely to exceed the preset component area. The present utility model creatively overlaps the common terminals of the one - of - two circuit or only sets one common terminal for the two circuits to share, reducing the space of the patch reserved positions, avoiding the patch exceeding the FPC component area, thus meeting the component area limit requirements of the terminal whole machine and avoiding the structural interference problem of the whole machine.

[0020] The present utility model solves the problem of insufficient space in the component area without changing the component model or packaging form, on the basis of meeting the existing set process requirements, with simple structural design and good effects.

[0021] Other features and advantages of the present utility model will be described in the subsequent specification or understood by implementing the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the patch structure of components in the FPC component area in the prior art.

[0023] Figure 2Schematic diagram of the chip mounting structure of components in the FPC component area of this embodiment of the utility model.

[0024] In the figure: 1. FPC component area; 2. Chip mounting selection position; 31. Common terminal; 4. FPC; 5. TFT module. Specific embodiments

[0025] The following describes the specific embodiments of the utility model with reference to the accompanying drawings.

[0026] As Figure 2 shown, the optimized component chip mounting structure in the component area of this embodiment includes an FPC component area 1, in which there is one or more chip mounting selection positions 2. The component is a two-way selection circuit, and there is no gap between the common terminals 31 of the two parallel circuits of the two-way selection circuit, so that one two-way selection circuit is arranged in each chip mounting selection position 2; the common terminal 31 is a shared connection line or a shared connection point respectively connected to the two parallel circuits.

[0027] As a specific embodiment, there is no gap between the common terminals 31 of the two parallel circuits of the two-way selection circuit, and its structure is that the two parallel circuits share a common terminal 31.

[0028] As a specific embodiment, there is no gap between the common terminals 31 of the two parallel circuits of the two-way selection circuit, and its structure is that the common terminals 31 of the two parallel circuits are stacked up and down.

[0029] As a specific embodiment, conductive adhesive is provided on the contact surface where the common terminals 31 of the two parallel circuits are stacked up and down for bonding.

[0030] As a specific embodiment, welding is performed on the contact surface where the common terminals 31 of the two parallel circuits are stacked up and down.

[0031] As a specific embodiment, the FPC component area 1 is rectangular, and multiple chip mounting selection positions 2 are arranged at intervals along the length direction of the rectangle.

[0032] As a specific embodiment, the width of the chip mounting selection position 2 is not greater than the width of the FPC component area 1.

[0033] As a specific embodiment, the FPC component area 1 is arranged on the FPC 4 and includes multiple.

[0034] This embodiment also provides an FPC, including the optimized component chip mounting structure of the component area.

[0035] This embodiment also provides a display module, including the FPC 4, and the FPC 4 is connected below the TFT module 5.

[0036] Since there is a common terminal in the either-or circuit, this embodiment utilizes the common terminal for overlapping, reducing the total space of the FPC component area, thereby meeting the requirements of the component area limit of the terminal whole machine and avoiding the structural interference problem of the whole machine.

[0037] Those of ordinary skill in the art can understand that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A component mounting structure with optimized design of component areas, characterized in that, It includes an FPC component area (1) in which one or more chip selection positions (2) are provided. The component is a two-way selection circuit. There is no gap between the common terminals (31) of the two parallel circuits of the two-way selection circuit, so that one of the two-way selection circuits is provided in each chip selection position (2); the common terminal (31) is a shared connection line or a shared connection point respectively connected to the two parallel circuits.

2. The component patch structure with optimized design of the component area according to claim 1, characterized in that, There is no gap between the common terminals (31) of the two parallel circuits of the two-way selection circuit, and its structure is that the two parallel circuits share a common terminal (31).

3. The component patch structure with optimized design of the component area according to claim 1, characterized in that, There is no gap between the common terminals (31) of the two parallel circuits of the two-way selection circuit, and its structure is that the common terminals (31) of the two parallel circuits are stacked up and down.

4. The component patch structure with optimized design of the component area according to claim 3, characterized in that, Conductive adhesive is provided for bonding on the contact surface where the common terminals (31) of the two parallel circuits are stacked up and down.

5. The component patch structure with optimized design of the component area according to claim 3, characterized in that Welding is performed on the contact surface where the common terminals (31) of the two parallel circuits are stacked up and down.

6. The component patch structure with optimized design of the component area according to claim 1, characterized in that, The FPC component area (1) is rectangular, and the multiple chip selection positions (2) are arranged at intervals along the length direction of the rectangle.

7. The component patch structure with optimized design of the component area according to claim 6, characterized in that The width of the chip selection position (2) is not greater than the width of the FPC component area (1).

8. The component patch structure with optimized design of the component area according to claim 1, characterized in that, Multiple FPC component areas (1) are provided.

9. An FPC, characterized in that, It includes a component chip structure optimized according to the component area described in any one of claims 1 to 8.

10. A display module, characterized in that, It includes the FPC described in claim 9.

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