Multi-channel flexible binding test device for PCIE (Peripheral Component Interface Express) switching chip

Abstract

The utility model provides a multi-channel flexible binding test device for a PCIE (Peripheral Component Interface Express) switching chip, which relates to the technical field of communication and comprises the PCIE switching chip, a PCIE slot connector and a switching device, the PCIE switching chip is provided with a plurality of PCIE channels, and the plurality of PCIE channels are connected with the PCIE slot connector directly or through a switching device; the PCIE slot connector is a PCIE interface of a PCIE channel of the PCIE switching chip; the switching device is respectively connected with the PCIE channels of the PCIE switching chip and the PCIE slot connector, and is used for switching the connection relationship between the PCIE channels of the PCIE switching chip and the PCIE slot connector, so that the plurality of PCIE channels of the PCIE switching chip are bound into different widths. The utility model provides a multi-channel flexible binding test device for a PCIE (Peripheral Component Interface Express) switching chip. A plurality of PCIE channels of the PCIE switching chip are bound into PCIE channels with different widths through a switching device so as to quickly establish test environments of different uplink ports and downlink ports.

Description

Technical Field

[0001] The utility model relates to the technical field of communications, in particular to a multi-channel flexible binding test device for a PCIE switching chip. Background Technique

[0002] At present, with the continuous development of communication technologies such as 5G, artificial intelligence, and big data, the PCIE bus, as the core bus in a high-performance computing architecture, has increasing requirements for the number and rate of its PCIE channels. When the PCIE devices in a high-performance computing architecture exceed the number of PCIE channels of the CPU, the PCIE switching chip exchanges data between PCIE channels through its internal organization to transfer data between PCIE devices and achieve data routing and forwarding. In this process, the PCIE switching chip is similar to a router, directly connecting data transmission from the CPU to each PCIE device and making full use of the limited PCIE channels of the CPU. The usage scenarios of the PCIE switching chip are flexible and changeable. Therefore, after the PCIE switching chip is taped out, various scenario tests need to be carried out to meet the requirements of the PCIE specification.

[0003] Test on the upstream port of the PCIE switch chip connected to the CPU (root complex, RC). The test scenarios usually involve one or multiple CPUs. Test on the downstream port of the PCIE switch chip connected to the endpoint device (EP). The test scenarios usually involve multiple endpoint devices. The existing PCIE switch chip test boards usually fixedly allocate 48 PCIE channels into 6 PCIE X8 channels, and can only perform tests on several fixed scenarios of PCIE X8 channels or PCIE X4 channels, and cannot flexibly switch the test scenarios. If other test scenarios need to be added, a dedicated PCIE test board needs to be designed again, which is costly and has a long development cycle. There are also existing PCIE switch chip test boards that connect the PCIE channels to the Mezzanine connector, and then connect to the adapter card through the iSAS-to-iSAS cable. The Mezzanine connector is converted into a PCIE slot connector or a PCIE gold finger connector through the adapter card to perform tests on multiple scenarios of PCIE X16 channels, PCIE X8 channels, and PCIE X4 channels. Different adapter boards and cables are used to build the test scenario according to the required test scenario during the test. However, due to the constraints of the electrical parameter performance of the adapter board and the cable, it is difficult to meet the data test of 16.0 Gbps, and the test scenario cannot be flexibly switched, and the cost is relatively high. There are also existing PCIE switch chip test boards that use PCIE high-speed passive switches to expand the connection test between the PCIE channels and the CPU (RC) or the endpoint device (EP). However, 1 high-speed passive switch is required for binding 1 PCIE X4 channel. The test scenario setup is complex, and it cannot meet the test of a large number of PCIE channels. The electrical performance parameters such as the insertion loss and differential impedance of the high-speed passive switch cannot be optimized, and the radio frequency switch rate only supports up to 8 Gbps. Summary of the Invention

[0004] The purpose of the present invention is to provide a multi-channel flexible binding test device for PCIE switch chips to solve at least one of the above technical problems existing in the prior art.

[0005] To solve the above technical problems, a multi-channel flexible binding test device for PCIE switch chips provided by the present invention includes: a PCIE switch chip, a PCIE slot connector, and a switching device;

[0006] The PCIE switch chip is arranged on a PCIE switch chip test board. The PCIE switch chip is provided with a plurality of PCIE channels, and the plurality of PCIE channels are directly or connected to the PCIE slot connector through the switching device;

[0007] The PCIE slot connector is the PCIE interface of the PCIE channel of the PCIE switching chip and is set on the PCIE switching chip test board. The PCIE channel of the PCIE switching chip is tested as an upstream port or a downstream port through the PCIE slot connector.

[0008] The switching device is respectively connected to the PCIE channel of the PCIE switching chip and the PCIE slot connector, and is used to switch the connection relationship between the PCIE channel of the PCIE switching chip and the PCIE slot connector, so as to bind several PCIE channels of the PCIE switching chip into different widths.

[0009] Further, every 16 of several PCIE channels of the PCIE switching chip form a test module. Every four of the 16 PCIE channels in this test module form a test unit, which is divided into a first test unit, a second test unit, a third test unit, and a fourth test unit.

[0010] The PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the PCIE slot connector through the switching device.

[0011] The PCIE slot connector includes: a first PCIE slot connector, a second PCIE slot connector, a third PCIE slot connector, and a fourth PCIE slot connector; the PCIE channels of the first test unit are directly connected to the first PCIE slot connector.

[0012] Further, the switching device includes a channel switching buckle plate and a high-speed mezzanine connector.

[0013] The female seat of the high-speed mezzanine connector is set on the PCIE switching chip test board and is respectively connected to the PCIE channels of the second test unit, the third test unit, and the fourth test unit, as well as the PCIE slot connector.

[0014] The male seat of the high-speed mezzanine connector is set on the channel switching buckle plate. The channel switching buckle plate is inserted onto the female seat of the high-speed mezzanine connector on the PCIE switching chip test board through the male seat of the high-speed mezzanine connector, and then is respectively connected to the PCIE channels of the second test unit, the third test unit, and the fourth test unit, as well as the PCIE slot connector through the female seat of the high-speed mezzanine connector.

[0015] The channel switching buckle plate sets the connection relationship between the PCIE channels of the second test unit, the third test unit, and the fourth test unit and the PCIE slot connector by setting the connection relationship of several signal pins of the high-speed mezzanine connector male socket, thereby binding the 16 PCIE channels of the test module into different widths.

[0016] Further, several signal pins are arranged on the high-speed mezzanine connector female socket, which are horizontally divided into a second connection unit, a third connection unit, and a fourth connection unit;

[0017] Several signal pins of the second connection unit are used for the connection between the PCIE channels of the second test unit and the PCIE slot connector;

[0018] Several signal pins of the third connection unit are used for the connection between the PCIE channels of the third test unit and the PCIE slot connector;

[0019] Several signal pins of the fourth connection unit are used for the connection between the PCIE channels of the fourth test unit and the PCIE slot connector;

[0020] The high-speed mezzanine connector female socket is longitudinally divided into a transmission area, a reception area, and an isolation area;

[0021] Several signal pins of the transmission area are used for the connection of the transmission ends (TX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit;

[0022] Several signal pins of the reception area are used for the connection of the reception ends (RX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit;

[0023] The isolation area is arranged between the transmission area and the reception area, and several signal pins of the isolation area are used for signal isolation between the transmission ends (TX) and the reception ends (RX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit, improving the high-speed signal crosstalk index;

[0024] Several signal pins of the transmission area and the reception area of the high-speed mezzanine connector female socket include: Pin pins, GND pins, X16 pins, and X4 pins;

[0025] The Pin pins are used for signal transmission between the transmission ends (TX) and the reception ends (RX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit;

[0026] The GND pin is the signal ground, which serves to provide a short - distance return path for signals, control impedance, isolate signals, and reduce crosstalk between signals;

[0027] The X16 pin is used for signal transmission of the transmit (TX) and receive (RX) ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit when the PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the first PCIE slot connector;

[0028] The X4 pin is used for signal transmission of the transmit (TX) and receive (RX) ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit when the PCIE channels of the second test unit, the third test unit, and the fourth test unit are respectively connected to the second PCIE slot connector, the third PCIE slot connector, and the fourth PCIE slot connector;

[0029] Several signal pins in the transmit area and the receive area of the fourth connection unit further include the X8 pin, which is used for signal transmission of the transmit (TX) and receive (RX) ends of the PCIE channel of the fourth test unit when the PCIE channel of the fourth test unit is connected to the third PCIE slot connector.

[0030] Further, several signal pins are arranged on the male high - speed mezzanine connector, which are horizontally divided into a second binding unit, a third binding unit, and a fourth binding unit;

[0031] Several signal pins of the second binding unit are used to set the connection relationship between the PCIE channel of the second test unit and the PCIE slot connector;

[0032] Several signal pins of the third binding unit are used to set the connection relationship between the PCIE channel of the third test unit and the PCIE slot connector;

[0033] Several signal pins of the fourth binding unit are used to set the connection relationship between the PCIE channel of the fourth test unit and the PCIE slot connector;

[0034] The male high - speed mezzanine connector is longitudinally divided into a transmit area, a receive area, and an isolation area;

[0035] Several signal pins in the transmit area are used to connect to the transmit (TX) ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit;

[0036] Several signal pins in the receiving area are used to connect to the receiving ends (RX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit;

[0037] The isolation area is arranged between the transmitting area and the receiving area. Several signal pins in the isolation area are used for signal isolation between the transmitting ends (TX) and the receiving ends (RX) of the PCIE channels of the second test unit, the third test unit, and the fourth test unit, so as to improve the high-speed signal crosstalk index;

[0038] The several signal pins in the transmitting area and the receiving area of the high-speed mezzanine connector male socket include: Pin pins, GND pins, X16 pins, X4 pins, and X8 pins; the several signal pins of the high-speed mezzanine connector male socket and female socket correspond one by one.

[0039] Furthermore, the channel switching buckle plate includes a first channel switching buckle plate. The Pin pins of the second binding unit, the third binding unit, and the fourth binding unit of the high-speed mezzanine connector male socket on the first channel switching buckle plate are connected to the X16 pins. The PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the first PCIE slot connector through the first channel switching buckle plate, and are used to bind 16 PCIE channels of the test module into one PCIE X16 channel.

[0040] Furthermore, the channel switching buckle plate further includes a second channel switching buckle plate. The Pin pins of the second binding unit of the high-speed mezzanine connector male socket on the second channel switching buckle plate are connected to the X16 pins, the Pin pins of the third binding unit are connected to the X4 pins, and the Pin pins of the fourth binding unit are all connected to the X8 pins. The PCIE channel of the second test unit is connected to the first PCIE slot connector through the second channel switching buckle plate, and the PCIE channels of the third test unit and the fourth test unit are connected to the third PCIE slot connector, and are used to bind 16 PCIE channels of the test module into two PCIE X8 channels.

[0041] Further, the channel switching buckle plate further includes a third channel switching buckle plate. The Pin pins of the second binding unit of the male high-speed mezzanine connector on the third channel switching buckle plate are connected to the X16 pins, and the Pin pins of the third binding unit and the fourth binding unit are connected to the X4 pins. The PCIE channels of the second test unit are connected to the first PCIE slot connector through the third channel switching buckle plate, the PCIE channels of the third test unit are connected to the third PCIE slot connector, and the PCIE channels of the fourth test unit are connected to the fourth PCIE slot connector, so as to bind 16 PCIE channels of the test module into a PCIE X8 channel and two PCIE X4 channels.

[0042] Further, the channel switching buckle plate further includes a fourth channel switching buckle plate. The Pin pins of the second binding unit, the third binding unit and the fourth binding unit of the male high-speed mezzanine connector on the fourth channel switching buckle plate are connected to the X4 pins. The PCIE channels of the second test unit are connected to the second PCIE slot connector through the fourth channel switching buckle plate, the PCIE channels of the third test unit are connected to the third PCIE slot connector, and the PCIE channels of the fourth test unit are connected to the fourth PCIE slot connector, so as to bind 16 PCIE channels of the test module into 4 PCIE X4 channels.

[0043] Further, several pins of the isolation area of the male high-speed mezzanine connector on the channel switching buckle plate include: in-position detection pins and buckle model detection pins; when the channel switching buckle plate is inserted on the PCIE switch chip detection board through the high-speed mezzanine connector, the in-position detection signal level will be pulled low, and the in-position detection signal is connected to the FPGA; the levels of the buckle model detection pins of different channel switching buckle plates are different and are connected to the FPGA, so as to identify the model of the channel switching buckle plate inserted on the PCIE switch chip detection board, and further identify the binding situation of 16 PCIE channels of the detection module.

[0044] Adopting the above technical solution, the utility model has the following beneficial effects:

[0045] A multi-channel flexible binding test device for a PCIE switching chip provided by the present utility model can bind several PCIE channels of the PCIE switching chip into PCIE channels with different widths through a switching device to quickly build test environments with different upstream ports and downstream ports, which can meet the rapid switching of the connection relationship between a large number of channel numbers and PCIE slot connectors, reduce the signal link length, reduce the number of interconnection nodes, with a rate up to 28 Gbps, improve the reliability and standardization of the test environment, and the test environment can be built simply and time-saving; the channel switching buckle plate is convenient for quick plugging and unplugging and replacement according to the required test scenarios, with a short development cycle and low cost. Description of the Drawings

[0046] In order to more clearly illustrate the specific embodiments of the present utility model or the technical solutions in the prior art, the following will briefly introduce the drawings required for use in the description of the specific embodiments or the prior art. Obviously, the following drawings are some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0047] Figure 1 It is a connection relationship diagram of the multi-channel flexible binding test device for the PCIE switching chip provided by the embodiment of the present utility model;

[0048] Figure 2 For Figure 1 It is a connection relationship diagram of the switching device binding a PCIE X16 channel shown;

[0049] Figure 3 For Figure 1 It is a circuit diagram of the transmission area of the high-speed mezzanine connector female seat of the switching device shown;

[0050] Figure 4 For Figure 1 It is a circuit diagram of the receiving area of the high-speed mezzanine connector female seat of the switching device shown;

[0051] Figure 5 For Figure 1 It is a circuit diagram of the isolation area of the high-speed mezzanine connector female seat of the switching device shown;

[0052] Figure 6 It is an assembly schematic diagram of the channel switching buckle plate and the PCIE switching chip test board;

[0053] Figure 7 For Figure 2 It is a pin assignment diagram of the high-speed mezzanine connector female seat of the switching device shown;

[0054] Figure 8 It is a circuit diagram of the transmission area of the high-speed mezzanine connector male seat of the first channel switching buckle plate;

[0055] Figure 9 Circuit diagram of the receiving area of the male high-speed mezzanine connector of the first channel switching buckle plate;

[0056] Figure 10 Circuit diagram of the isolation area of the male high-speed mezzanine connector of the first channel switching buckle plate;

[0057] Figure 11 For Figure 1 Impedance detection diagram of the high-speed mezzanine connector of the switching device shown;

[0058] Figure 12 For Figure 1 Insertion loss detection diagram of the high-speed mezzanine connector of the switching device shown;

[0059] Figure 13 Connection diagram of the switching device of the PCIE switch chip multi-channel flexible binding test device provided by another embodiment of the present invention binding two PCIE X8 channels;

[0060] Figure 14 For Figure 13 Pin assignment diagram of the female high-speed mezzanine connector of the switching device shown;

[0061] Figure 15 Circuit diagram of the sending area of the male high-speed mezzanine connector of the second channel switching buckle plate;

[0062] Figure 16 Circuit diagram of the receiving area of the male high-speed mezzanine connector of the second channel switching buckle plate;

[0063] Figure 17 Circuit diagram of the isolation area of the male high-speed mezzanine connector of the second channel switching buckle plate;

[0064] Figure 18 Connection diagram of the switching device of the PCIE switch chip multi-channel flexible binding test device provided by another embodiment of the present invention binding one PCIE X8 channel and two PCIE X4 channels;

[0065] Figure 19 For Figure 18 Pin assignment diagram of the female high-speed mezzanine connector of the switching device shown;

[0066] Figure 20 Circuit diagram of the sending area of the male high-speed mezzanine connector of the third channel switching buckle plate;

[0067] Figure 21 Circuit diagram of the receiving area of the male high-speed mezzanine connector of the third channel switching buckle plate;

[0068] Figure 22 Circuit diagram of the isolation area of the male high-speed mezzanine connector for the third-channel switching buckle plate;

[0069] Figure 23 Connection diagram of the switching device of the PCIE switch chip multi-channel flexible binding test device provided by another embodiment of the present invention, binding four PCIE X4 channels;

[0070] Figure 24 For Figure 23 Pin assignment diagram of the female high-speed mezzanine connector of the switching device shown;

[0071] Figure 25 Circuit diagram of the transmission area of the male high-speed mezzanine connector for the fourth-channel switching buckle plate;

[0072] Figure 26 Circuit diagram of the receiving area of the male high-speed mezzanine connector for the fourth-channel switching buckle plate;

[0073] Figure 27 Circuit diagram of the isolation area of the male high-speed mezzanine connector for the fourth-channel switching buckle plate;

[0074] Figure 28 Connection diagram of the in-position detection and buckle plate model detection of the PCIE switch chip multi-channel flexible binding test device provided by another embodiment of the present invention. Detailed implementation manners

[0075] Next, the technical solutions of the present invention will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0076] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0077] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0078] The following further explains and illustrates the present utility model in conjunction with specific embodiments.

[0079] It should also be noted that the following specific embodiments or specific implementation manners are a series of optimized setting manners listed by the present utility model to further explain the specific content of the utility model, and these setting manners can be combined with each other or used in association with each other.

[0080] Embodiment 1

[0081] As Figure 1-12As shown in the figure, a multi-channel flexible binding test device for a PCIE switching chip provided in this embodiment includes: a PCIE switching chip, a PCIE slot connector, and a switching device; the PCIE switching chip is arranged on a PCIE switching chip test board, and the PCIE switching chip is provided with a plurality of PCIE channels, and the plurality of PCIE channels are connected to the PCIE slot connector or connected to the switching device and then connected to the PCIE slot connector through the switching device; the PCIE slot connector is a PCIE interface of the PCIE channels of the PCIE switching chip and is arranged on the PCIE switching chip test board; the PCIE channels of the PCIE switching chip can be selectively used as an upstream port or a downstream port for testing through the PCIE slot connector; when used as an upstream port, the PCIE slot connector is connected to a CPU (RC) through a PCIE 4.0 cable for testing; when used as a downstream port, a PCIE endpoint device (EP) is inserted into the PCIE slot connector for testing; the PCIE channels led out through the PCIE slot connector follow the consistency of the electrical parameters (TX and RX) of the main board in the PCIE mechanical and electrical specifications, which is convenient for carrying out PCIE electrical parameter testing and PCIE protocol switching network testing, and is convenient for docking endpoint devices and PCIE protocol test instruments; the switching device is arranged on the PCIE switching chip test board and is respectively connected to the PCIE channels of the PCIE switching chip and the PCIE slot connector, and is used for switching the connection relationship between the PCIE channels of the PCIE switching chip and the PCIE slot connector, so as to bind the plurality of PCIE channels of the PCIE switching chip into PCIE channels with different widths; the width of the PCIE channels bound on one PCIE slot connector is the number of PCIE channels connected to the PCIE slot connector.

[0082] Refer to Figure 1-2As shown, every 16 of several PCIE channels of the PCIE switching chip form a test module; every four of the 16 PCIE channels of the test module form a test unit, which are divided into a first test unit, a second test unit, a third test unit, and a fourth test unit; the PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the switching device and then connected to the PCIE slot connector through the switching device; the PCIE slot connector includes: a first PCIE slot connector 1, a second PCIE slot connector 2, a third PCIE slot connector 3, and a fourth PCIE slot connector 4; the first PCIE slot connector 1 is used for binding PCIE X16 channels or PCIE X8 channels or PCIE X4 channels, and the PCIE channels of the first test unit are connected to the first PCIE slot connector 1; the second PCIE slot connector 2 and the fourth PCIE slot connector 4 are used for binding PCIE X4 channels; the third PCIE slot connector 3 is used for binding PCIE X8 channels or PCIE X4 channels. In this embodiment, the PCIE switching chip has 48 PCIE channels, which are divided into three test modules; taking the test module composed of PCIE channels Lane0 to 15 as an example, PCIE channels Lane0 to 3 are the first test unit, PCIE channels Lane4 to 7 are the second test unit, PCIE channels Lane8 to 11 are the third test unit, and PCIE channels Lane12 to 15 are the fourth test unit.

[0083] Refer to Figure 6As shown, the switching device includes a channel switching buckle plate and a high-speed mezzanine connector; the female socket of the high-speed mezzanine connector is arranged on the PCIE switch chip test board and is respectively connected to the PCIE channels Lane4-7 of the second test unit, the PCIE channels Lane8-11 of the third test unit, the PCIE channels Lane12-15 of the fourth test unit and the PCIE slot connector; the male socket of the high-speed mezzanine connector is arranged on the channel switching buckle plate, and the channel switching buckle plate is inserted on the female socket of the high-speed mezzanine connector on the PCIE switch chip test board through the male socket of the high-speed mezzanine connector, and then is respectively connected to the PCIE channels Lane4-7 of the second test unit, the PCIE channels Lane8-11 of the third test unit, the PCIE channels Lane12-15 of the fourth test unit and the PCIE slot connector through the female socket of the high-speed mezzanine connector; the channel switching buckle plate sets the connection relationship between the PCIE channels Lane4-7 of the second test unit, the PCIE channels Lane8-11 of the third test unit, the PCIE channels Lane12-15 of the fourth test unit and the PCIE slot connector by setting the connection relationship of several signal pins of the male socket of the high-speed mezzanine connector, and then binds the PCIE channels Lane0-15 of the test module into PCIE channels with different widths; the high-speed mezzanine connector provides high density, high-speed performance, large arrays, makes the distribution of high-speed signals and return paths more flexible, and supports a high-speed signal rate of 28 Gbps.

[0084] Refer to Figure 3-5As shown, there are 400 signal pins arranged in a rectangular array on the high-speed mezzanine connector female socket, with 10 rows from A to J and 40 columns from 1 to 40, and they are ball pins; the 400 signal pins of the high-speed mezzanine connector female socket are horizontally divided into a second connection unit, a third connection unit, and a fourth connection unit; the signal pins of columns 1 - 12 of the high-speed mezzanine connector female socket are the second connection unit, which is used for the connection between the PCIE channel Lane4 - 7 of the second test unit and the PCIE slot connector; the signal pins of columns 13 - 24 of the high-speed mezzanine connector female socket are the third connection unit, which is used for the connection between the PCIE channel Lane8 - 11 of the third test unit and the PCIE slot connector; the signal pins of columns 25 - 40 of the high-speed mezzanine connector female socket are the fourth connection unit, which is used for the connection between the PCIE channel Lane12 - 15 of the fourth test unit and the PCIE slot connector; the 400 signal pins of the high-speed mezzanine connector female socket are vertically divided into a transmission area, a reception area, and an isolation area; the signal pins of rows A - D of the high-speed mezzanine connector female socket are the transmission area, which is used for the connection of the transmission ends (TX) of the PCIE channel Lane4 - 7 of the second test unit, the PCIE channel Lane8 - 11 of the third test unit, and the PCIE channel Lane12 - 15 of the fourth test unit; the signal pins of rows G - J of the high-speed mezzanine connector female socket are the reception area, which is used for the connection of the reception ends (RX) of the PCIE channel Lane4 - 7 of the second test unit, the PCIE channel Lane8 - 11 of the third test unit, and the PCIE channel Lane12 - 15 of the fourth test unit; the signal pins of rows E and F of the high-speed mezzanine connector female socket are the isolation area, which is used for signal isolation between the transmission ends (TX) and the reception ends (RX) of the PCIE channel Lane4 - 7 of the second test unit, the PCIE channel Lane8 - 11 of the third test unit, and the PCIE channel Lane12 - 15 of the fourth test unit, improving the high-speed signal crosstalk index; several signal pins in the transmission area and the reception area of the high-speed mezzanine connector female socket include: Pin pins, GND pins, X16 pins, and X4 pins; the Pin pins are used for signal transmission between the transmission ends (TX) and the reception ends (RX) of the PCIE channel Lane4 - 7 of the second test unit, the PCIE channel Lane8 - 11 of the third test unit, and the PCIE channel Lane12 - 15 of the fourth test unit; the GND pins are signal grounds, which play the roles of providing a short-distance return path for signals, controlling impedance, signal isolation, and reducing crosstalk between signals;The X16 pin is used for signal transmission of the transmit end (TX) and the receive end (RX) of the PCIE channels Lane4 - 7 of the second test unit, the PCIE channels Lane8 - 11 of the third test unit, and the PCIE channels Lane12 - 15 of the fourth test unit when they are connected to the first PCIE slot connector 1; the X4 pin is used for signal transmission of the transmit end (TX) and the receive end (RX) of the PCIE channels Lane4 - 7 of the second test unit, the PCIE channels Lane8 - 11 of the third test unit, and the PCIE channels Lane12 - 15 of the fourth test unit when they are respectively connected to the second PCIE slot connector 2, the third PCIE slot connector 3, and the fourth PCIE slot connector 4; several signal pins in the transmit area and the receive area of the fourth connection unit further include the X8 pin, and the X8 pin is used for signal transmission of the transmit end (TX) and the receive end (RX) of the PCIE channels Lane12 - 15 of the fourth test unit when the PCIE channels Lane12 - 15 of the fourth test unit are connected to the third PCIE slot connector 3.;

[0085] In this embodiment, on the male connector of the high-speed mezzanine connector, there are 400 signal pins arranged in a rectangular array with 10 rows from A to J and 40 columns from 1 to 40, and these are ball pins; the 400 signal pins of the male connector of the high-speed mezzanine connector are horizontally divided into a second bonding unit, a third bonding unit, and a fourth bonding unit; the signal pins in columns 1 - 12 of the male connector of the high-speed mezzanine connector are the second bonding unit, which is used to set the connection relationship between the PCIE channel Lanes 4 - 7 of the second test unit and the PCIE slot connector; the signal pins in columns 13 - 24 of the male connector of the high-speed mezzanine connector are the third bonding unit, which is used to set the connection relationship between the PCIE channel Lanes 8 - 11 of the third test unit and the PCIE slot connector; the signal pins in columns 25 - 40 of the male connector of the high-speed mezzanine connector are the fourth bonding unit, which is used to set the connection relationship between the PCIE channel Lanes 12 - 15 of the fourth test unit and the PCIE slot connector; the 400 signal pins of the male connector of the high-speed mezzanine connector are vertically divided into a transmission area, a reception area, and an isolation area; the signal pins in rows A - D of the male connector of the high-speed mezzanine connector are the transmission area, which is used to connect the transmission ends (TX) of the PCIE channel Lanes 4 - 7 of the second test unit, the PCIE channel Lanes 8 - 11 of the third test unit, and the PCIE channel Lanes 12 - 15 of the fourth test unit; the signal pins in rows G - J of the male connector of the high-speed mezzanine connector are the reception area, which is used to connect the reception ends (RX) of the PCIE channel Lanes 4 - 7 of the second test unit, the PCIE channel Lanes 8 - 11 of the third test unit, and the PCIE channel Lanes 12 - 15 of the fourth test unit; the signal pins in rows E and F of the male connector of the high-speed mezzanine connector are the isolation area, which is used for signal isolation between the transmission ends (TX) and the reception ends (RX) of the PCIE channel Lanes 4 - 7 of the second test unit, the PCIE channel Lanes 8 - 11 of the third test unit, and the PCIE channel Lanes 12 - 15 of the fourth test unit, so as to improve the high-speed signal crosstalk index; several signal pins in the transmission area and the reception area of the male connector of the high-speed mezzanine connector include: Pin pins, GND pins, X16 pins, X4 pins, and X8 pins; the 400 signal pins of the male connector of the high-speed mezzanine connector correspond one-to-one with the 400 signal pins of the female connector of the high-speed mezzanine connector.

[0086] Refer to Figure 7-10As shown, in this embodiment, the channel switching buckle plate is the first channel switching buckle plate. The Pin pins of the second binding unit, the third binding unit, and the fourth binding unit of the male high-speed mezzanine connector on the first channel switching buckle plate are connected to the X16 pins. The second binding unit, the third binding unit, and the fourth binding unit are respectively connected to the PCIE channels Lane4 - 7 of the second test unit, the PCIE channels Lane8 - 11 of the third test unit, the PCIE channels Lane12 - 15 of the fourth test unit, and the first PCIE slot connector 1 through the Pin pins and the X16 pins of the second connection unit, the third connection unit, and the fourth connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane4 - 7 of the second test unit, the PCIE channels Lane8 - 11 of the third test unit, and the PCIE channels Lane12 - 15 of the fourth test unit to the first PCIE slot connector 1. And the PCIE channels Lane0 - 3 of the first test unit are directly connected to the first PCIE slot connector 1, thus binding the 16 PCIE channels of the test module into a PCIE X16 channel, and this PCIE X16 channel can be selectively used as an upstream port or a downstream port for testing.

[0087] Refer to Figure 11 , Figure 12 As shown, the signal integrity of the high-speed mezzanine connector is optimized to meet the requirements of protocol consistency. The impedance is 90Ω ± 5%, and the insertion loss is less than -0.5dB. The ball pins of the high-speed mezzanine connector are arranged on the first layer of the PCB, the second layer of the PCB is hollowed out, and the ball pins refer to the third layer of the PCB; the line width and line pitch of the differential line are optimized to 4.2 / 5; the diameter of the anti-pad is optimized to 20mil; the aperture of the via hole is adjusted to 8 - 16mil.

[0088] Embodiment 2

[0089] This embodiment is basically the same as Embodiment 1, except that:

[0090] As Figure 13-17As shown, in this embodiment, the channel switching buckle plate is the second channel switching buckle plate. The Pin pins of the second binding unit of the male high-speed mezzanine connector on the second channel switching buckle plate are connected to the X16 pins, the Pin pins of the third binding unit are connected to the X4 pins, and the Pin pins of the fourth binding unit are connected to the X8 pins. The second binding unit is respectively connected to the PCIE channels Lane4 - 7 of the second test unit and the first PCIE slot connector 1 through the Pin pins and the X16 pins of the second connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane4 - 7 of the second test unit to the first PCIE slot connector 1. And the PCIE channels Lane0 - 3 of the first test unit are directly connected to the first PCIE slot connector 1, binding them into a PCIE X8 channel. The third binding unit is respectively connected to the PCIE channels Lane8 - 11 of the third test unit and the third PCIE slot connector 3 through the Pin pins and the X4 pins of the third connection unit of the female high-speed mezzanine connector. The fourth binding unit is respectively connected to the PCIE channels Lane12 - 15 of the fourth test unit and the third PCIE slot connector 3 through the Pin pins and the X8 pins of the fourth connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane8 - 11 of the third test unit and the PCIE channels Lane12 - 15 of the fourth test unit to the third PCIE slot connector 3, binding them into another PCIE X8 channel, thus binding the 16 PCIE channels of the test module into two PCIE X8 channels. Optionally, one PCIE X8 channel is used as the upstream port and the other PCIE X8 channel is used as the downstream port for testing; or both PCIE X8 channels are used as the downstream ports for testing.

[0091] Embodiment 3

[0092] This embodiment is basically the same as Embodiment 1, except that:

[0093] As Figure 18-22As shown, in this embodiment, the channel switching buckle plate is the third channel switching buckle plate. The Pin pins of the second binding unit of the male high-speed mezzanine connector on the third channel switching buckle plate are connected to the X16 pins, and the Pin pins of the third binding unit and the fourth binding unit are connected to the X4 pins. The second binding unit is respectively connected to the PCIE channels Lane4 - 7 of the second test unit and the first PCIE slot connector 1 through the Pin pins and the X16 pins of the second connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane4 - 7 of the second test unit to the first PCIE slot connector 1. And the PCIE channels Lane0 - 3 of the first test unit are directly connected to the first PCIE slot connector 1, binding them into a PCIE X8 channel. The third binding unit is respectively connected to the PCIE channels Lane8 - 11 of the third test unit and the third PCIE slot connector 3 through the Pin pins and the X4 pins of the third connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane8 - 11 of the third test unit to the third PCIE slot connector 3, binding them into a PCIE X4 channel. The fourth binding unit is respectively connected to the PCIE channels Lane12 - 15 of the fourth test unit and the fourth PCIE slot connector 4 through the Pin pins and the X4 pins of the fourth connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane12 - 15 of the fourth test unit to the fourth PCIE slot connector 4, binding them into another PCIE X4 channel, thereby binding the 16 PCIE channels of the test module into a PCIE X8 channel and two PCIE X4 channels. Optionally, one PCIE X8 channel is used as the upstream port and two PCIE X4 channels are used as the downstream ports for testing; or one PCIE X8 channel and two PCIE X4 channels are both used as the downstream ports for testing.

[0094] Embodiment 4

[0095] This embodiment is basically the same as Embodiment 1, the difference being that:

[0096] As Figure 23-27As shown, in this embodiment, the channel switching buckle plate is the fourth channel switching buckle plate. The Pin pins of the second binding unit, the third binding unit, and the fourth binding unit of the male high-speed mezzanine connector on the fourth channel switching buckle plate are connected to the X4 pins. The second binding unit is connected to the PCIE channels Lane4 to Lane7 of the second test unit and the second PCIE slot connector 2 respectively through the Pin pins and the X4 pins of the second connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane4 to Lane7 of the second test unit to the second PCIE slot connector 2 and binding them into a PCIE X4 channel. The third binding unit is connected to the PCIE channels Lane8 to Lane11 of the third test unit and the third PCIE slot connector 3 respectively through the Pin pins and the X4 pins of the third connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane8 to Lane11 of the third test unit to the third PCIE slot connector 3 and binding them into another PCIE X4 channel. The fourth binding unit is connected to the PCIE channels Lane12 to Lane15 of the fourth test unit and the fourth PCIE slot connector 4 respectively through the Pin pins and the X4 pins of the fourth connection unit of the female high-speed mezzanine connector, connecting the PCIE channels Lane12 to Lane15 of the fourth test unit to the fourth PCIE slot connector 4 and binding them into yet another PCIE X4 channel. And the PCIE channels Lane0 to Lane3 of the first test unit are directly connected to the first PCIE slot connector 1 and are also bound into a PCIE X4 channel. Thus, the 16 PCIE channels of the test module are bound into 4 PCIE X4 channels. Optionally, one PCIE X4 channel is used as the upstream port and three PCIE X4 channels are used as the downstream ports for testing; or all four PCIE X4 channels are used as the downstream ports for testing.

[0097] Embodiment 5

[0098] This embodiment is basically the same as Embodiment 1, except that:

[0099] As Figure 28As shown, in this embodiment, several pins in the isolation area of the high-speed mezzanine connector male socket on the channel switching pinch board include an in-place detection pin and a pinch board model detection pin; when the channel switching pinch board is inserted into the PCIE switch chip detection board through the high-speed mezzanine connector, the in-place detection signal level will be pulled low, and the in-place detection signal is connected to the FPGA; the pinch board model detection pins of different channel switching pinch boards have different levels, which are connected to the FPGA to identify the model of the channel switching pinch board inserted into the PCIE switch chip detection board.

[0100] In the above embodiments, the Pin pin of the high-speed mezzanine connector male socket on the channel switching gusset plate is connected to the X16 pin or the X4 pin or the X8 pin through a short and equidistant PCB trace. The binding method of the PCIE channels Lane16~31, Lane 32~47 of the PCIE switching chip is consistent with Lane0~15. If the PCIE switching chip has 64 or 96 or more PCIE channels, it can be expanded according to the technical solution of the present application; of course, the high-speed mezzanine connector with 200 signal pins can be selected or appropriately cut according to the number of PCIE channels of the PCIE switching chip. The switching device described in the present application meets the use of the PCIE 4.0 protocol at 16Gbps. If the rate is increased to 32Gbps, a high-speed mezzanine connector that supports up to 56Gbps can be selected.

[0101] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the utility model.

Claims

1. A multi-channel flexible binding test device for a PCIE switch chip, characterized in that, Including: A PCIE switch chip, a PCIE slot connector, and a switching device; The PCIE switch chip is arranged on a PCIE switch chip test board. The PCIE switch chip is provided with a plurality of PCIE channels, and the plurality of PCIE channels are directly or connected to the PCIE slot connector through the switching device; The PCIE slot connector is a PCIE interface of the PCIE channels of the PCIE switch chip and is arranged on the PCIE switch chip test board; The switching device is respectively connected to the PCIE channels of the PCIE switch chip and the PCIE slot connector, and is used for switching the connection relationship between the PCIE channels of the PCIE switch chip and the PCIE slot connector, and further binding the plurality of PCIE channels of the PCIE switch chip into different widths.

2. The multi-channel flexible binding test device for a PCIE switching chip according to claim 1, wherein Every 16 of the plurality of PCIE channels of the PCIE switch chip form a test module, and every four of the 16 PCIE channels of the test module form a test unit, which are divided into a first test unit, a second test unit, a third test unit, and a fourth test unit; The PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the PCIE slot connector through the switching device; The PCIE slot connector includes: a first PCIE slot connector, a second PCIE slot connector, a third PCIE slot connector, and a fourth PCIE slot connector; The PCIE channels of the first test unit are connected to the first PCIE slot connector.

3. The PCIE switch chip multi-channel flexible binding test device according to claim 2, characterized in that, The switching device includes a channel switching buckle plate and a high-speed mezzanine connector; The female seat of the high-speed mezzanine connector is arranged on the PCIE switch chip test board and is respectively connected to the PCIE channels of the second test unit, the third test unit, and the fourth test unit and the PCIE slot connector; The male seat of the high-speed mezzanine connector is arranged on the channel switching buckle plate. The channel switching buckle plate is inserted on the female seat of the high-speed mezzanine connector on the PCIE switch chip test board through the male seat of the high-speed mezzanine connector, and further connected to the PCIE channels of the second test unit, the third test unit, and the fourth test unit and the PCIE slot connector respectively through the female seat of the high-speed mezzanine connector; The channel switching buckle plate sets the connection relationship between the PCIE channels of the second test unit, the third test unit, and the fourth test unit and the PCIE slot connector by setting the connection relationship of a plurality of signal pins of the male seat of the high-speed mezzanine connector, and further binds the 16 PCIE channels of the test module into different widths.

4. The PCIE switch chip multi-channel flexible binding test device according to claim 3, characterized in that, A plurality of signal pins are arranged on the female seat of the high-speed mezzanine connector and are horizontally divided into a second connection unit, a third connection unit, and a fourth connection unit; The plurality of signal pins of the second connection unit are used for the connection between the PCIE channels of the second test unit and the PCIE slot connector; Several signal pins of the third connection unit are used for the connection between the PCIE channels of the third test unit and the PCIE slot connector; Several signal pins of the fourth connection unit are used for the connection between the PCIE channels of the fourth test unit and the PCIE slot connector; The high-speed mezzanine connector female socket is longitudinally divided into a transmission area, a reception area, and an isolation area; Several signal pins of the transmission area are used for the connection of the transmission ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; Several signal pins of the reception area are used for the connection of the reception ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; The isolation area is arranged between the transmission area and the reception area, and several signal pins of the isolation area are used for signal isolation between the transmission ends and reception ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; Several signal pins of the transmission area and the reception area of the high-speed mezzanine connector female socket include: Pin pins, GND pins, X16 pins, and X4 pins; The Pin pins are used for signal transmission between the transmission ends and reception ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; The GND pins are signal grounds; The X16 pins are used for signal transmission between the transmission ends and reception ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit when the PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the first PCIE slot connector; The X4 pins are used for signal transmission between the transmission ends and reception ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit when the PCIE channels of the second test unit, the third test unit, and the fourth test unit are respectively connected to the second PCIE slot connector, the third PCIE slot connector, and the fourth PCIE slot connector; Several signal pins of the transmission area and the reception area of the fourth connection unit further include X8 pins, and the X8 pins are used for signal transmission between the transmission ends and reception ends of the PCIE channel of the fourth test unit when the PCIE channel of the fourth test unit is connected to the third PCIE slot connector.

5. The PCIE switch chip multi-channel flexible binding test device according to claim 3, characterized in that Several signal pins are arranged on the high-speed mezzanine connector male socket, which is horizontally divided into a second binding unit, a third binding unit, and a fourth binding unit; Several signal pins of the second binding unit are used to set the connection relationship between the PCIE channel of the second test unit and the PCIE slot connector; Several signal pins of the third binding unit are used to set the connection relationship between the PCIE channel of the third test unit and the PCIE slot connector; Several signal pins of the fourth binding unit are used to set the connection relationship between the PCIE channel of the fourth test unit and the PCIE slot connector; The male high-speed mezzanine connector is longitudinally divided into a transmission area, a reception area, and an isolation area; A plurality of signal pins in the transmission area are used for connecting the transmitting ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; A plurality of signal pins in the reception area are used for connecting the receiving ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; The isolation area is arranged between the transmission area and the reception area, and a plurality of signal pins in the isolation area are used for signal isolation between the transmitting ends and the receiving ends of the PCIE channels of the second test unit, the third test unit, and the fourth test unit; A plurality of signal pins in the transmission area and the reception area of the male high-speed mezzanine connector include: Pin pins, GND pins, X16 pins, X4 pins, and X8 pins; the plurality of signal pins of the male high-speed mezzanine connector and the female connector correspond one by one.

6. The PCIE switch chip multi-channel flexible binding test device according to claim 5, characterized in that The channel switching buckle plate includes a first channel switching buckle plate. The Pin pins and the X16 pins of the second binding unit, the third binding unit, and the fourth binding unit of the male high-speed mezzanine connector on the first channel switching buckle plate are connected. The PCIE channels of the second test unit, the third test unit, and the fourth test unit are connected to the first PCIE slot connector through the first channel switching buckle plate, and are used for binding 16 PCIE channels of the test module into one PCIE X16 channel.

7. The PCIE switch chip multi-channel flexible binding test device according to claim 5, characterized in that The channel switching buckle plate further includes a second channel switching buckle plate. The Pin pin and the X16 pin of the second binding unit of the male high-speed mezzanine connector on the second channel switching buckle plate are connected. The Pin pin of the third binding unit is connected to the X4 pin, and the Pin pins of the fourth binding unit are all connected to the X8 pins. The PCIE channel of the second test unit is connected to the first PCIE slot connector through the second channel switching buckle plate, and the PCIE channels of the third test unit and the fourth test unit are connected to the third PCIE slot connector, and are used for binding 16 PCIE channels of the test module into two PCIE X8 channels.

8. The PCIE switch chip multi-channel flexible binding test device according to claim 5, characterized in that The channel switching buckle further includes a third channel switching buckle. The Pin pins of the second binding unit of the high-speed mezzanine connector male socket on the third channel switching buckle are connected to the X16 pins, and the Pin pins of the third binding unit and the fourth binding unit are connected to the X4 pins. Through the third channel switching buckle, the PCIE channels of the second test unit are connected to the first PCIE slot connector, the PCIE channels of the third test unit are connected to the third PCIE slot connector, and the PCIE channels of the fourth test unit are connected to the fourth PCIE slot connector, so as to bind 16 PCIE channels of the test module into one PCIE X8 channel and two PCIE X4 channels.

9. The PCIE switch chip multi-channel flexible binding test device according to claim 5, characterized in that, The channel switching buckle further includes a fourth channel switching buckle. The Pin pins of the second binding unit, the third binding unit, and the fourth binding unit of the high-speed mezzanine connector male socket on the fourth channel switching buckle are connected to the X4 pins. Through the fourth channel switching buckle, the PCIE channels of the second test unit are connected to the second PCIE slot connector, the PCIE channels of the third test unit are connected to the third PCIE slot connector, and the PCIE channels of the fourth test unit are connected to the fourth PCIE slot connector, so as to bind 16 PCIE channels of the test module into 4 PCIE X4 channels.

10. The multi-channel flexible binding test device for a PCIE switching chip according to claim 5, characterized in that Several pins in the isolation area of the high-speed mezzanine connector male socket on the channel switching buckle include: in-position detection pins and buckle model detection pins; when the channel switching buckle is inserted on the PCIE switch chip detection board through the high-speed mezzanine connector, the in-position detection signal level will be pulled low, and the in-position detection signal is connected to the FPGA; the levels of the buckle model detection pins of different channel switching buckles are different and are connected to the FPGA, which is used to identify the model of the channel switching buckle inserted on the PCIE switch chip detection board, and further identify the binding situation of 16 PCIE channels of the detection module.

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