Test circuit and test system of memory chip

Abstract

The utility model provides a test circuit and a test system for a memory chip. The test circuit comprises a test circuit and a plurality of sub test circuits, the test circuit is provided with a programmable logic array and a plurality of I / O expansion circuits. The programmable logic array expands pins of the programmable logic array through a plurality of I / O expansion circuits to obtain a plurality of test pins; different sub test circuits are provided with different ball grid arrays; a corresponding memory chip is placed in each ball grid array; the test pin is connected with the memory chip through the ball grid array; the upper computer receives the test instruction, controls the programmable logic array to send a test electric signal to the storage chip, receives an actual electric signal corresponding to the test electric signal output by the storage chip, and transmits the actual electric signal to the upper computer; the upper computer is also used for determining the performance of the storage chip according to the actual electric signal. According to the circuit, different types of to-be-tested memory chips are connected with the upper computer through different types of ball grid arrays, so that the test efficiency is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of chip testing, in particular to a test circuit and a test system for a storage chip. Background Art

[0002] During the manufacturing process of storage chips, aging tests need to be carried out on the chips to distinguish the grades of the chips through a series of tests. The current test circuit can only perform tests on a single type of chip, resulting in cumbersome processes and low efficiency during the testing of multiple types of storage chips. Summary of the Utility Model

[0003] The purpose of the utility model is to provide a test circuit and a test system for a storage chip, so as to alleviate the technical problem that the current test circuit can only perform tests on a single type of chip, resulting in cumbersome processes and low efficiency during the testing of multiple types of storage chips, simplify the processes of testing multiple types of storage chips during the testing process, and improve the test efficiency.

[0004] In a first aspect, an embodiment of the utility model provides a test circuit for a storage chip, including: a test circuit and a plurality of sub-test circuits; the test circuit and the plurality of sub-test circuits are placed under a preset temperature condition; the test circuit is provided with a programmable logic array and a plurality of I / O expansion circuits; the programmable logic array is powered by a power supply device of an external device; the programmable logic array extends the pins of the programmable logic array through the plurality of I / O expansion circuits to obtain a preset number of test pins; the programmable logic array is controlled by a host computer of an external device; different sub-test circuits are provided with different types of ball grid arrays; each of the ball grid arrays is used to place a corresponding storage chip to be tested; the test pins are connected to the storage chip to be tested through the ball grid array; the host computer is used to, if receiving a test instruction from a user, control the programmable logic array to send a preset test electrical signal to the storage chip to be tested, receive an actual electrical signal corresponding to the test electrical signal output by the storage chip to be tested, and transmit the actual electrical signal to the host computer; the host computer is further used to determine the performance of the storage chip to be tested according to the actual electrical signal.

[0005] In a preferred embodiment of the utility model, the programmable logic array and the sub-test circuits are connected through the power supply device of the external device; the programmable logic array is connected to the power supply device of the external device through a first voltage stabilizing circuit; the sub-test circuits are connected to the power supply device of the external device through a second voltage stabilizing circuit.

[0006] In a preferred embodiment of the present utility model, the first voltage stabilizing circuit includes: a first voltage stabilizing chip, a first filter capacitor, a first inductor, a pull-up resistor for the first voltage stabilizing chip, a first current limiting resistor, and a first feedback resistor; the main power voltage input terminal of the first voltage stabilizing chip is connected to the power supply device, and the switching transistor output terminal of the first voltage stabilizing chip is connected to the programmable logic array through the first inductor; the enable terminal, the main power voltage input terminal, and the synchronous switch input terminal of the first voltage stabilizing chip are all connected to the first filter capacitor; the first filter capacitor is grounded; the analog power input terminal of the first voltage stabilizing chip is connected to the power supply device through the pull-up resistor for the first voltage stabilizing chip; the enable terminal of the first voltage stabilizing chip is connected to the power supply device through the first current limiting resistor; the feedback input terminal of the first voltage stabilizing chip is connected to the switching transistor output terminal through the first feedback resistor.

[0007] In a preferred embodiment of the present utility model, the model of the first voltage stabilizing chip is SY8047.

[0008] In a preferred embodiment of the present utility model, the second voltage stabilizing circuit includes: a second voltage stabilizing chip, a pull-up resistor for the second voltage stabilizing chip, a second inductor, a freewheeling diode, a bootstrap capacitor, a second feedback resistor, and a second filter capacitor; the voltage input terminal of the second voltage stabilizing chip is connected to the power supply device; the enable terminal of the second voltage stabilizing chip is connected to the I / O expansion circuit through the pull-up resistor for the second voltage stabilizing chip; the bootstrap pin of the second voltage stabilizing chip is connected to one end of the second inductor through the bootstrap capacitor; one end of the second inductor is also connected to the negative electrode of the freewheeling diode; the positive electrode of the freewheeling diode is grounded; the feedback pin of the second voltage stabilizing chip is connected to the other end of the second inductor through the second feedback resistor; the output pin of the second voltage stabilizing chip is connected to the sub-test circuit; the output pin of the second voltage stabilizing chip is also grounded through the second filter capacitor.

[0009] In a preferred embodiment of the present utility model, the model of the second voltage stabilizing chip is RT8279.

[0010] In a preferred embodiment of the present utility model, an I2C channel expansion circuit is further connected between the programmable logic array and the storage chip to be tested; the I2C channel expansion circuit is used to expand the I2C interface of the programmable logic array; the host computer is further configured to, if receiving a test instruction from the user, control the programmable logic array to send a preset test electrical signal to the storage chip to be tested through the I2C interface, receive an actual electrical signal corresponding to the test electrical signal output by the storage chip to be tested through the I2C interface, and transmit the actual electrical signal to the host computer.

[0011] In a preferred embodiment of the present utility model, the above I2C channel expansion circuit includes: an I2C expansion chip, an I2C expansion chip pull-up resistor, a second impedance matching resistor, a fourth current limiting resistor, a second address selection resistor, and a fourth filter capacitor; the address input terminal of the above I2C expansion chip is connected to the above second address selection resistor; the above second address selection resistor is connected to the above second voltage stabilizing circuit; the clock line, static data authentication terminal, and multiple output terminals of the above I2C expansion chip are connected to the above second voltage stabilizing circuit through the above I2C expansion chip pull-up resistor; the clock line of the above I2C expansion chip is connected to the first communication terminal of the above programmable logic array through the first sub-impedance matching resistor in the above second impedance matching resistor; the static data authentication terminal of the above I2C expansion chip is connected to the second communication terminal of the above programmable logic array through the second sub-impedance matching resistor in the above second impedance matching resistor; the reset terminal of the above I2C expansion chip is connected to the above second voltage stabilizing circuit through the above fourth current limiting resistor; the power input terminal of the above I2C expansion chip is connected to the above second voltage stabilizing circuit; the power input terminal of the above I2C expansion chip is also grounded through the above fourth filter capacitor.

[0012] In a preferred embodiment of the present utility model, the model of the above I2C expansion chip is PCA9548.

[0013] In a preferred embodiment of the present utility model, the above I / O expansion circuit includes: an I / O expansion chip, an I / O expansion chip pull-up resistor, a first impedance matching resistor, a third current limiting resistor, a first address selection resistor, and a third filter capacitor; the address input terminal of the above I / O expansion chip is connected to the above first address selection resistor; the above first address selection resistor is connected to the above second voltage stabilizing circuit; the clock line, static data authentication terminal, and multiple output terminals of the above I / O expansion chip are connected to the above second voltage stabilizing circuit through the above I / O expansion chip pull-up resistor; the clock line of the above I / O expansion chip is connected to the first communication terminal of the above programmable logic array through the first sub-impedance matching resistor in the above first impedance matching resistor; the static data authentication terminal of the above I / O expansion chip is connected to the second communication terminal of the above programmable logic array through the second sub-impedance matching resistor in the above first impedance matching resistor; the reset terminal of the above I / O expansion chip is connected to the above second voltage stabilizing circuit through the above third current limiting resistor; the power input terminal of the above I / O expansion chip is connected to the above second voltage stabilizing circuit; the power input terminal of the above I / O expansion chip is also grounded through the above third filter capacitor.

[0014] In a preferred embodiment of the present utility model, the model of the above I / O expansion chip is the PCA9555APW chip.

[0015] In a preferred embodiment of the present utility model, the test circuit of the above storage chip further includes: a board-to-board connector respectively connected to the above-mentioned multiple I / O expansion circuits and the ball grid array.

[0016] In a preferred embodiment of the present utility model, the above test circuit is further provided with a temperature sensor connected to the above host computer; the above temperature sensor is used to monitor the real-time temperature of the above test circuit; the above host computer is further used to determine whether the real-time temperature exceeds a preset threshold, and if so, disconnect the above test circuit and the above multiple sub-test circuits from the above power supply device.

[0017] In a preferred embodiment of the present utility model, the model of the above temperature sensor is LM95231.

[0018] In a second aspect, an embodiment of the present utility model further provides a test system, including: the test circuit of the above storage chip.

[0019] An embodiment of the present utility model provides a test circuit and a test system for a storage chip, including: a test circuit and a plurality of sub-test circuits; the above test circuit and the above plurality of sub-test circuits are placed under a preset temperature condition; the above test circuit is provided with a programmable logic array and a plurality of I / O expansion chips; the above programmable logic array is powered by an external power supply device; the above programmable logic array expands the pins of the above programmable logic array through the above plurality of I / O expansion chips to obtain a preset number of test pins; the above programmable logic array is controlled by an external host computer; different sub-test circuits are provided with different types of ball grid arrays; each of the above ball grid arrays is used to place a corresponding storage chip to be tested; the above test pins are connected to the above storage chip to be tested through the above ball grid array; the above host computer is used to, if receiving a test instruction from a user, control the above programmable logic array to send a preset test electrical signal to the above storage chip to be tested, receive the actual electrical signal corresponding to the above test electrical signal output by the above storage chip to be tested, and transmit the above actual electrical signal to the above host computer; the above host computer is further used to determine the performance of the above storage chip to be tested according to the above actual electrical signal. The test circuit of the storage chip connects different types of storage chips to be tested to the host computer through different types of ball grid arrays, so that various storage chips to be tested can be tested based on this test circuit, simplifying the testing process of multiple types of storage chips and improving the testing efficiency. Description of the Drawings

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 The structural schematic diagram of a test circuit for a storage chip provided by an embodiment of the present invention;

[0022] Figure 2 The structural schematic diagram of another test circuit for a storage chip provided by an embodiment of the present invention;

[0023] Figure 3 The structural schematic diagram of a first voltage stabilizing circuit provided by an embodiment of the present invention;

[0024] Figure 4 The structural schematic diagram of a second voltage stabilizing circuit provided by an embodiment of the present invention;

[0025] Figure 5 The structural schematic diagram of an I / O expansion circuit provided by an embodiment of the present invention;

[0026] Figure 6 The structural schematic diagram of an I2C channel expansion circuit provided by an embodiment of the present invention;

[0027] Figure 7 The structural schematic diagram of a test system provided by an embodiment of the present invention.

[0028] Icon: 11 - Test circuit; 12 - Sub - test circuit; 21 - Programmable logic array; 22 - I / O expansion circuit; 23 - Host computer; 24 - Ball grid array; 25 - Power supply device; 26 - First voltage stabilizing circuit; 27 - Second voltage stabilizing circuit; 28 - Board - to - board connector; 31 - Test system; 32 - Test circuit for storage chip. Specific Embodiments

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Generally, the components of the embodiments of the present invention described and illustrated in the drawings here can be arranged and designed in various different configurations.

[0030] The current test circuit can only test a single type of chip, resulting in a cumbersome process and low efficiency in testing multi-type memory chips.

[0031] Based on this, the embodiments of the present utility model provide a test circuit and a test system for memory chips. This circuit can simplify the process of testing multi-type memory chips and improve the test efficiency. For ease of understanding, the test circuit of the memory chip will be described in detail first.

[0032] Embodiment 1

[0033] In this embodiment, Figure 1 is a schematic structural diagram of a test circuit for a memory chip provided by an embodiment of the present utility model.

[0034] As Figure 1 seen, the test circuit of the memory chip includes: a test circuit 11 and a plurality of sub-test circuits 12; the above-mentioned test circuit 11 and the above-mentioned plurality of sub-test circuits 12 are placed under a preset temperature condition.

[0035] Among them, the above-mentioned test circuit 11 is provided with a programmable logic array 21 and a plurality of I / O expansion circuits 22; the above-mentioned programmable logic array 21 is powered by an external power supply device; the above-mentioned programmable logic array 21 expands the pins of the programmable logic array through the above-mentioned plurality of I / O expansion circuits 22 to obtain a preset number of test pins; the above-mentioned programmable logic array 21 is controlled by an external host computer 23; different sub-test circuits 12 are provided with different types of ball grid arrays 24; each of the above-mentioned ball grid arrays 24 is used to place the corresponding memory chip to be tested; the above-mentioned test pins are connected to the above-mentioned memory chip to be tested through the above-mentioned ball grid array 24; the above-mentioned host computer 23 is used to, if receiving a test instruction from a user, control the above-mentioned programmable logic array 21 to send a preset test electrical signal to the above-mentioned memory chip to be tested, receive the actual electrical signal corresponding to the above-mentioned test electrical signal output by the above-mentioned memory chip to be tested, and transmit the above-mentioned actual electrical signal to the above-mentioned host computer 23; the above-mentioned host computer 23 is further used to determine the performance of the above-mentioned memory chip to be tested according to the above-mentioned actual electrical signal.

[0036] Among them, the above-mentioned ball grid array 24 can provide 132 test slots. According to different inserted socket small boards, aging operations can be performed on different memory chips. And only one programmable logic array 21, that is, FPGA, plus I / O expansion circuit 22 can age 132 memory chips to be tested.

[0037] Among them, the types of the above-mentioned memory chips to be tested are: NAND, EMMC, and UFS.

[0038] For ease of understanding, Figure 2Schematic diagram of the structure of another test circuit for a storage chip provided by an embodiment of the present utility model.

[0039] As Figure 2 seen, the above-mentioned programmable logic array 21 and the above-mentioned sub-test circuit 12 are connected by an external power supply device 25; the above-mentioned programmable logic array 21 is connected to the above-mentioned external power supply device 25 through a first voltage stabilizing circuit 26; the above-mentioned sub-test circuit 12 is connected to the above-mentioned external power supply device 25 through a second voltage stabilizing circuit 27.

[0040] For ease of understanding, Figure 3 Schematic diagram of the structure of a first voltage stabilizing circuit provided by an embodiment of the present utility model.

[0041] As Figure 3 seen, the above-mentioned first voltage stabilizing circuit 26 includes: a first voltage stabilizing chip, a first filter capacitor, a first inductor, a pull-up resistor for the first voltage stabilizing chip, a first current limiting resistor, and a first feedback resistor; the main power voltage input terminal of the above-mentioned first voltage stabilizing chip is connected to the above-mentioned power supply device, and the switching transistor output terminal of the above-mentioned first voltage stabilizing chip is connected to the above-mentioned programmable logic array 21 through the above-mentioned first inductor; the enable terminal, the main power voltage input terminal, and the synchronous switch input terminal of the above-mentioned first voltage stabilizing chip are all connected to the above-mentioned first filter capacitor; the above-mentioned first filter capacitor is grounded; the analog power input terminal of the above-mentioned first voltage stabilizing chip is connected to the above-mentioned power supply device through the above-mentioned pull-up resistor for the first voltage stabilizing chip; the enable terminal of the above-mentioned first voltage stabilizing chip is connected to the above-mentioned power supply device through the above-mentioned first current limiting resistor; the feedback input terminal of the above-mentioned first voltage stabilizing chip is connected to the switching transistor output terminal through the above-mentioned first feedback resistor.

[0042] Among them, the model of the above-mentioned first voltage stabilizing chip is SY8047, and the pull-up resistor for the first voltage stabilizing chip is represented by R6; the above-mentioned first current limiting resistor includes a first sub-current limiting resistor and a second sub-current limiting resistor, where the above-mentioned first sub-current limiting resistor is represented by R7, and the above-mentioned second sub-current limiting resistor is represented by R8; the above-mentioned first feedback resistor includes: a first sub-feedback resistor and a second sub-feedback resistor, where the first sub-feedback resistor is represented by R9, and the above-mentioned second sub-feedback resistor is represented by R10; the above-mentioned first inductor is represented by L2; the above-mentioned first filter capacitor includes a first sub-filter capacitor, a second sub-filter capacitor, a third sub-filter capacitor, a fourth sub-filter capacitor, a fifth sub-filter capacitor, a sixth sub-filter capacitor, and a seventh sub-filter capacitor; the above-mentioned first sub-filter capacitor is represented by C10, the above-mentioned second sub-filter capacitor is represented by C16, the above-mentioned third sub-filter capacitor is represented by C17, the above-mentioned fourth sub-filter capacitor is represented by C12, the above-mentioned fifth sub-filter capacitor is represented by C13, the above-mentioned sixth sub-filter capacitor is represented by C14; the above-mentioned seventh sub-filter capacitor is represented by C11.

[0043] Further, the first filtering capacitor further includes: an eighth sub-filtering capacitor; wherein, the eighth sub-filtering capacitor is represented by C15; one end of the eighth sub-filtering capacitor is connected to the feedback input terminal of the first voltage stabilizing chip, and the other end is connected to the programmable logic array 21.

[0044] Further, Figure 4 is a schematic structural diagram of a second voltage stabilizing circuit provided by an embodiment of the present invention.

[0045] As Figure 4 can be seen, the second voltage stabilizing circuit 27 includes: a second voltage stabilizing chip, a pull-up resistor of the second voltage stabilizing chip, a second inductor, a freewheeling diode, a bootstrap capacitor, a second feedback resistor, and a second filtering capacitor; the voltage input terminal of the second voltage stabilizing chip is connected to the power supply device; the enable terminal of the second voltage stabilizing chip is connected to the I / O expansion circuit through the pull-up resistor of the second voltage stabilizing chip; the bootstrap pin of the second voltage stabilizing chip is connected to one end of the second inductor through the bootstrap capacitor; one end of the second inductor is further connected to the negative electrode of the freewheeling diode; the positive electrode of the freewheeling diode is grounded; the feedback pin of the second voltage stabilizing chip is connected to the other end of the second inductor through the second feedback resistor; the output pin of the second voltage stabilizing chip is connected to the sub-test circuit; the output pin of the second voltage stabilizing chip is further grounded through the second filtering capacitor.

[0046] Wherein, the model of the second voltage stabilizing chip is RT8279; the pull-up resistor of the second voltage stabilizing chip is represented by R1; the second inductor is represented by L1; the freewheeling diode is represented by D1, and the bootstrap capacitor is represented by C1; the second feedback resistor includes a third sub-feedback resistor and a fourth sub-feedback resistor, wherein, the third sub-feedback resistor is represented by R4, and the fourth sub-feedback resistor is represented by R5; the second filtering capacitor is represented by C5, C6, C7, and C8.

[0047] Further, the above I / O expansion circuit 22 includes: an I / O expansion chip, an I / O expansion chip pull-up resistor, a first impedance matching resistor, a third current limiting resistor, a first address selection resistor, and a third filter capacitor; the address input terminal of the I / O expansion chip is connected to the first address selection resistor; the first address selection resistor is connected to the second voltage stabilizing circuit 27; the clock line, the static data authentication terminal, and multiple output terminals of the I / O expansion chip are connected to the second voltage stabilizing circuit through the I / O expansion chip pull-up resistor; the clock line of the I / O expansion chip is connected to the first communication terminal of the programmable logic array 21 through the first sub-impedance matching resistor in the first impedance matching resistor; the static data authentication terminal of the I / O expansion chip is connected to the second communication terminal of the programmable logic array 21 through the second sub-impedance matching resistor in the first impedance matching resistor; the interrupt output of the I / O expansion chip is connected to the second voltage stabilizing circuit 27 through the third current limiting resistor; the power input terminal of the I / O expansion chip is connected to the second voltage stabilizing circuit 27; the power input terminal of the I / O expansion chip is also grounded through the third filter capacitor.

[0048] For ease of understanding, Figure 5 FIG. 5 is a schematic structural diagram of an I / O expansion circuit provided by an embodiment of the present invention.

[0049] Among them, the model of the I / O expansion chip is a PCA9555APW chip; the I / O expansion chip pull-up resistor is represented by R19 and R20; the first sub-impedance matching resistor in the first impedance matching resistor is represented by R37; the second sub-impedance matching resistor in the first impedance matching resistor is represented by R39; the I / O expansion chip pull-up resistor is represented by R23, R24, R25, R26, R27, R28, R31, R31, R49, R50, R51, R52, R53, R54, R55, R56; the first address selection resistor is represented by R33, R34, R40, R43, R44, R45; the third current limiting resistor is represented by R22; the third filter capacitor is represented by C19 and C20; C19 and C20 are connected in parallel.

[0050] Among them, an I2C channel expansion circuit is further connected between the programmable logic array 21 and the storage chip to be tested; the I2C channel expansion circuit is used to expand the I2C interface of the programmable logic array 21; the host computer 23 is further configured to, if receiving a test instruction from a user, control the programmable logic array 21 to send a preset test electrical signal to the storage chip to be tested through the I2C interface, receive an actual electrical signal corresponding to the test electrical signal output by the storage chip to be tested through the I2C interface, and transmit the actual electrical signal to the host computer 23.

[0051] For the convenience of understanding, Figure 6 FIG. 1 is a schematic structural diagram of an I2C channel expansion circuit provided by an embodiment of the present invention.

[0052] As Figure 6 can be seen, the above I2C channel expansion circuit includes: an I2C expansion chip, an I2C expansion chip pull-up resistor, a second impedance matching resistor, a fourth current-limiting resistor, a second address selection resistor, and a fourth filter capacitor; the address input terminal of the above I2C expansion chip is connected to the above second address selection resistor; the above second address selection resistor is connected to the above second voltage stabilizing circuit 27; the clock line, static data authentication terminal, and multiple output terminals of the above I2C expansion chip are connected to the above second voltage stabilizing circuit 27 through the above I2C expansion chip pull-up resistor; the clock line of the above I2C expansion chip is connected to the first communication terminal of the above programmable logic array 21 through the first sub-impedance matching resistor in the above second impedance matching resistor; the static data authentication terminal of the above I2C expansion chip is connected to the second communication terminal of the above programmable logic array 21 through the second sub-impedance matching resistor in the above second impedance matching resistor; the reset terminal of the above I2C expansion chip is connected to the above second voltage stabilizing circuit 27 through the above fourth current-limiting resistor; the power input terminal of the above I2C expansion chip is connected to the above second voltage stabilizing circuit 27; the power input terminal of the above I2C expansion chip is also grounded through the above fourth filter capacitor.

[0053] In this embodiment, the model of the above I2C channel expansion chip is PCA9548; the I2C expansion chip pull-up resistor is represented by R29 and R30; the first sub-impedance matching resistor in the above second impedance matching resistor is represented by R42; the second sub-impedance matching resistor in the above second impedance matching resistor is represented by R38; the I2C expansion chip pull-up resistor is represented by R18, R17, R16, R15, R14, R13, R12, R11, R57, R58, R59, R60, R61, R62, R63, R64, and the above second address selection resistor is represented by R35, R36, R41, R46, R47, R48; the above fourth current-limiting resistor is represented by R21; the above fourth filter capacitor is represented by C21.

[0054] Further, the above fourth current-limiting resistor is also grounded through a filter capacitor C18.

[0055] In specific implementation, the host computer 23 sends a specific command (determined by the firmware of the chip) to the FPGA through the serial port, forwards it to the chip through the FPGA, and after a period of time, detects the level state of a certain pin of the chip to judge the aging degree of the chip, thereby completing the aging process of the entire storage chip to be tested.

[0056] Further, the test circuit of the above storage chip further includes a board-to-board connector 28 respectively connected to the above-mentioned multiple I / O expansion circuits 22 and the ball grid array 24.

[0057] Further, an I2C channel expansion chip is also connected between the above-mentioned programmable logic array 21 and the storage chip to be tested; the I2C channel expansion chip is used to expand the I2C interface of the programmable logic array; the host computer 23 is also used to control the programmable logic array 21 to send a preset test electrical signal to the storage chip to be tested through the I2C interface if a test instruction from the user is received, receive the actual electrical signal corresponding to the test electrical signal output by the storage chip to be tested through the I2C interface, and transmit the actual electrical signal to the host computer 23.

[0058] In actual operation, the above test circuit 11 is also provided with a temperature sensor connected to the above host computer 23; the temperature sensor is used to monitor the real-time temperature of the test circuit; the host computer 23 is also used to determine whether the real-time temperature exceeds a preset threshold, and if so, disconnect the test circuit 11 and the above-mentioned multiple sub-test circuits 12 from the power supply device 25.

[0059] Here, the test circuit 11 and the sub-test circuit 12 are placed in an incubator at a preset temperature. The model of the above temperature sensor is LM95231. The LM95231 is used to monitor the temperatures of the test circuit 11 and the sub-test circuit 12. When an abnormality occurs, the test board will automatically disconnect the connections between the test circuit 11 and the sub-test circuit 12 and the power supply device 25.

[0060] Further, the types of the above actual electrical signals are: actual voltage signals and actual current signals; the host computer 23 is also used to determine the power consumption of the storage chip to be tested according to the above actual voltage signals and the above actual current signals.

[0061] An embodiment of the present utility model provides a test circuit for a storage chip, including: a test circuit and a plurality of sub-test circuits; the above test circuit and the above plurality of sub-test circuits are placed under a preset temperature condition; the above test circuit is provided with a programmable logic array and a plurality of I / O expansion circuits; the above programmable logic array is powered by a power supply device of an external device; the above programmable logic array expands the pins of the above programmable logic array through the above plurality of I / O expansion circuits to obtain a preset number of test pins; the above programmable logic array is controlled by a host computer of an external device; different sub-test circuits are provided with different types of ball grid arrays; each of the above ball grid arrays is used to place a corresponding storage chip to be tested; the above test pins are connected to the above storage chip to be tested through the above ball grid array; the above host computer is used to control the above programmable logic array to send a preset test electrical signal to the above storage chip to be tested if it receives a test instruction from a user, and receive an actual electrical signal corresponding to the above test electrical signal output by the above storage chip to be tested, and transmit the above actual electrical signal to the above host computer; the above host computer is further used to determine the performance of the above storage chip to be tested according to the above actual electrical signal. The test circuit of the storage chip connects different types of storage chips to be tested to the host computer through different types of ball grid arrays, so that various storage chips to be tested can be tested based on this test circuit, simplifying the testing process of multiple types of storage chips and improving the testing efficiency.

[0062] Embodiment 2

[0063] Based on the above embodiment, Figure 7 It is a schematic structural diagram of a test system provided by an embodiment of the present utility model.

[0064] As Figure 7 can be seen, the test system 31 includes: the test circuit 32 of the storage chip in the above embodiment.

[0065] The test system provided by the embodiment of the present utility model has the same technical features as the test circuit of the storage chip provided by the above embodiment, so it can also solve the same technical problems and achieve the same technical effects. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working process of the above-described test system can refer to the corresponding process in the embodiment of the test circuit of the storage chip described above, and will not be repeated here.

[0066] Therefore, the following detailed description of the embodiments of the present utility model provided in the drawings is not intended to limit the scope of the claimed present utility model, but merely represents selected embodiments of the present utility model. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present utility model.

[0067] Finally, it should be noted that the above embodiments are only specific implementation manners of the present utility model, used to illustrate the technical solutions of the present utility model, rather than limiting it. The protection scope of the present utility model is not limited thereto. Although the present utility model has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the technical field of the present utility model can still modify the technical solutions recorded in the foregoing embodiments, or can easily think of changes, or perform equivalent replacements on some of the technical features; and these modifications, changes or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present utility model, and should all be covered within the protection scope of the present utility model.

Claims

1. A test circuit for a memory chip, characterized in that, Including: A test circuit and a plurality of sub-test circuits; The test circuit and the plurality of sub-test circuits are placed under a preset temperature condition; The test circuit is provided with a programmable logic array and a plurality of I / O expansion circuits; the programmable logic array is powered by a power supply device of an external device; the programmable logic array expands the pins of the programmable logic array through the plurality of I / O expansion circuits to obtain a preset number of test pins; the programmable logic array is controlled by a host computer of an external device; Different sub-test circuits are provided with different types of ball grid arrays; each of the ball grid arrays is used to place a corresponding memory chip under test; the test pins are connected to the memory chip under test through the ball grid array; The host computer is used to, if receiving a test instruction from a user, control the programmable logic array to send a preset test electrical signal to the memory chip under test, receive an actual electrical signal corresponding to the test electrical signal output by the memory chip under test, and transmit the actual electrical signal to the host computer; The host computer is further used to determine the performance of the memory chip under test according to the actual electrical signal.

2. The test circuit of the storage chip according to claim 1, wherein The programmable logic array and the sub-test circuits are connected through the power supply device of the external device; the programmable logic array is connected to the power supply device of the external device through a first voltage stabilizing circuit; the sub-test circuits are connected to the power supply device of the external device through a second voltage stabilizing circuit.

3. The test circuit of the storage chip according to claim 2, wherein The first voltage stabilizing circuit includes: a first voltage stabilizing chip, a first filter capacitor, a first inductor, a pull-up resistor of the first voltage stabilizing chip, a first current limiting resistor and a first feedback resistor; the main power voltage input end of the first voltage stabilizing chip is connected to the power supply device, and the switching transistor output end of the first voltage stabilizing chip is connected to the programmable logic array through the first inductor; the enable end, the main power voltage input end and the synchronous switch input end of the first voltage stabilizing chip are all connected to the first filter capacitor; the first filter capacitor is grounded; the analog power input end of the first voltage stabilizing chip is connected to the power supply device through the pull-up resistor of the first voltage stabilizing chip; the enable end of the first voltage stabilizing chip is connected to the power supply device through the first current limiting resistor; the feedback input end of the first voltage stabilizing chip is connected to the switching transistor output end through the first feedback resistor.

4. The test circuit of the storage chip according to claim 3, wherein The model of the first voltage stabilizing chip is SY8047.

5. The test circuit of a storage chip according to claim 2, wherein The second voltage stabilizing circuit includes: a second voltage stabilizing chip, a pull-up resistor for the second voltage stabilizing chip, a second inductor, a freewheeling diode, a bootstrap capacitor, a second feedback resistor, and a second filter capacitor; the voltage input terminal of the second voltage stabilizing chip is connected to the power supply device; the enable terminal of the second voltage stabilizing chip is connected to the I / O expansion circuit through the pull-up resistor for the second voltage stabilizing chip; the bootstrap pin of the second voltage stabilizing chip is connected to one end of the second inductor through the bootstrap capacitor; one end of the second inductor is also connected to the negative electrode of the freewheeling diode; the positive electrode of the freewheeling diode is grounded; the feedback pin of the second voltage stabilizing chip is connected to the other end of the second inductor through the second feedback resistor; the output pin of the second voltage stabilizing chip is connected to the sub-test circuit; the output pin of the second voltage stabilizing chip is also grounded through the second filter capacitor.

6. The test circuit of the storage chip according to claim 5, characterized in that, The model of the second voltage stabilizing chip is RT8279.

7. The test circuit of the storage chip according to claim 2, characterized in that, An I2C channel expansion circuit is also connected between the programmable logic array and the storage chip to be tested; The I2C channel expansion circuit is used to expand the I2C interface of the programmable logic array; The host computer is further configured to, if receiving a test instruction from a user, control the programmable logic array to send a preset test electrical signal to the storage chip to be tested through the I2C interface, receive an actual electrical signal corresponding to the test electrical signal output by the storage chip to be tested through the I2C interface, and transmit the actual electrical signal to the host computer.

8. The test circuit of the storage chip according to claim 7, characterized in that, The I2C channel expansion circuit includes: an I2C expansion chip, a pull-up resistor for the I2C expansion chip, a second impedance matching resistor, a fourth current limiting resistor, a second address selection resistor, and a fourth filter capacitor; The address input terminal of the I2C expansion chip is connected to the second address selection resistor; the second address selection resistor is connected to the second voltage stabilizing circuit; the clock line, the static data authentication terminal, and multiple output terminals of the I2C expansion chip are connected to the second voltage stabilizing circuit through the pull-up resistor for the I2C expansion chip; the clock line of the I2C expansion chip is connected to the first communication terminal of the programmable logic array through the first sub-impedance matching resistor in the second impedance matching resistor; the static data authentication terminal of the I2C expansion chip is connected to the second communication terminal of the programmable logic array through the second sub-impedance matching resistor in the second impedance matching resistor; the reset terminal of the I2C expansion chip is connected to the second voltage stabilizing circuit through the fourth current limiting resistor; the power input terminal of the I2C expansion chip is connected to the second voltage stabilizing circuit; the power input terminal of the I2C expansion chip is also grounded through the fourth filter capacitor.

9. The test circuit of the storage chip according to claim 8, wherein, The model of the I2C expansion chip is PCA9548.

10. The test circuit of the storage chip according to claim 2, characterized in that, The I / O expansion circuit includes: an I / O expansion chip, a pull-up resistor for the I / O expansion chip, a first impedance matching resistor, a third current-limiting resistor, a first address selection resistor, and a third filter capacitor; the address input terminal of the I / O expansion chip is connected to the first address selection resistor; the first address selection resistor is connected to the second voltage stabilization circuit; the clock line, the static data authentication terminal, and multiple output terminals of the I / O expansion chip are connected to the second voltage stabilization circuit through the pull-up resistor for the I / O expansion chip; the clock line of the I / O expansion chip is connected to the first communication terminal of the programmable logic array through the first sub-impedance matching resistor in the first impedance matching resistor; the static data authentication terminal of the I / O expansion chip is connected to the second communication terminal of the programmable logic array through the second sub-impedance matching resistor in the first impedance matching resistor; the reset terminal of the I / O expansion chip is connected to the second voltage stabilization circuit through the third current-limiting resistor; the power input terminal of the I / O expansion chip is connected to the second voltage stabilization circuit; the power input terminal of the I / O expansion chip is also grounded through the third filter capacitor.

11. The test circuit of the storage chip according to claim 10, characterized in that, The model of the I / O expansion chip is PCA9555APW chip.

12. The test circuit of a storage chip according to any one of claims 1-11, characterized in that, The test circuit of the memory chip further includes: a board-to-board connector respectively connected to the multiple I / O expansion circuits and the ball grid array.

13. The test circuit of a storage chip according to any one of claims 1-11, characterized in that, The test circuit is also provided with a temperature sensor connected to the host computer; The temperature sensor is used to monitor the real-time temperature of the test circuit; The host computer is also used to determine whether the real-time temperature exceeds a preset threshold, and if so, disconnect both the test circuit and the multiple sub-test circuits from the power supply device.

14. The test circuit of a storage chip according to claim 13, characterized in that, The model of the temperature sensor is LM95231.

15. A test system, characterized in that, Including: The test circuit of the memory chip according to any one of claims 1 to 14.

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