Semiconductor packaging structure
By using glass wafers and high-density metal interconnection layers in semiconductor packaging structures, combined with flip chips or interposer layers, the problems of low I/O density and slow signal transmission in existing packaging structures are solved, and a multi-chip stacked package with high integration and fast signal transmission is achieved.
Patent Information
- Application Number
- CN202422437951.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-10-09
AI Technical Summary
The I/O density of existing system-level packaging structures is difficult to improve, the signal transmission rate is slow, and the integration is low, making it difficult to meet the needs of high-performance computing and AI servers.
A glass wafer is used as a supporting substrate, and a functional unit is installed internally, and a high-density metal interconnection layer is formed on its surface. The chip unit is connected to the metal interconnection layer through flip-fitting mount or interposer layer to realize multi-chip stacking packaging.
It improves the I/O density and integration of the packaging structure, enhances the signal transmission rate, simplifies the packaging process, and realizes multi-chip 3D+3D multi-dimensional stacking.
Smart Images
Figure CN223156037U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and particularly relates to a semiconductor packaging structure. Background Art
[0002] The requirements for packaging such as functional integration, large storage space, miniaturization, and high reliability in high-performance computing and AI servers are getting higher and higher. How to integrate and package multiple different types of high-density chips together to form a powerful system or subsystem with relatively small volume and power consumption has become a major challenge in the field of advanced semiconductor chip packaging.
[0003] As an emerging heterogeneous integration technology, System In Package (SIP) technology can integrate multiple active devices with different functions, passive devices, microelectromechanical systems (MEMS), and / or other components such as optical elements into one package body, thereby forming a system or subsystem that can provide multiple functions, and has become the packaging form of more and more chips.
[0004] However, the I / O (Input / Output) density of the current system-level packaging structure is still difficult to improve, the signal transmission rate is slow, and the integration level is also relatively low. How to further improve the I / O density, signal transmission rate, and integration level has become a technical problem that needs to be solved urgently. Summary of the Utility Model
[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present utility model is to provide a semiconductor packaging structure to further improve the I / O density and the integration level of the packaging structure.
[0006] To achieve the above purpose and other related purposes, the present utility model provides a semiconductor packaging structure, including:
[0007] A glass wafer, including a first surface and a second surface arranged opposite to each other, and functional units are arranged inside the glass wafer and exposed on the first surface;
[0008] A metal interconnection layer, arranged on the first surface of the glass wafer and connected to the functional units;
[0009] A chip unit, arranged on the surface of the metal interconnection layer and forming a connection with the metal interconnection layer.
[0010] Optionally, the chip unit includes a chip, and the chip is connected to the metal interconnection layer in a flip-chip mounting manner.
[0011] Optionally, the chip unit includes:
[0012] An interposer, arranged on the metal interconnection layer and connected to the metal interconnection layer;
[0013] A chip is disposed on the interposer, and the chip is connected to the interposer through metal bumps.
[0014] Optionally, the interposer is an active silicon interposer, and active devices are included in the active silicon interposer, and the active devices are interconnected with the chip.
[0015] Optionally, the chip unit includes a first chip and a second chip, the first chip and the second chip are spaced apart, and each chip is interconnected with the active devices in the active silicon interposer.
[0016] Optionally, the first chip is selected from one of HBM chips, IO chips, SOC chips, CPU chips or GPU chips, and the second chip is selected from one of HBM chips, IO chips, SOC chips, CPU chips or GPU chips.
[0017] Optionally, a dielectric layer is further disposed on the interposer, and the dielectric layer fills the gap on the side wall of the chip on the interposer and covers the upper surface of the chip.
[0018] Optionally, the metal interconnect layer is a damascene interconnect layer or a redistribution layer.
[0019] Optionally, the glass wafer further includes TGV metal pillars, and the TGV metal pillars penetrate from the first surface of the glass wafer to the second surface.
[0020] Optionally, solder bumps are further disposed on the second surface of the glass wafer, and the solder bumps are connected to the exposed TGV metal pillars on the second surface.
[0021] Compared with the prior art, the semiconductor packaging structure of the present invention has at least the following beneficial effects:
[0022] The semiconductor packaging structure of the present invention includes a glass wafer, a metal interconnect layer and a chip unit. The glass wafer includes a first surface and a second surface which are oppositely arranged. A functional unit is disposed in the glass wafer, and the functional unit is exposed on the first surface. The metal interconnect layer is disposed on the first surface of the glass wafer and is connected to the functional unit. The chip unit is disposed on the surface of the metal interconnect layer and forms a connection with the metal interconnect layer. Thus, in the semiconductor packaging structure of the present invention, a glass wafer is used as a support substrate to form a semiconductor packaging structure, and a functional unit, that is, a functional chip, is formed in the glass wafer. Bonding chips above the glass wafer can realize multi-chip stacking and packaging, improving the integration degree of the packaging structure. Moreover, a high-density metal interconnect layer can be formed on the surface of the glass wafer, thereby being able to improve the signal transmission rate. Compared with the existing glass substrate-level packaging, the interconnect density on the surface of the glass wafer is higher, and due to the manufacturability of the glass wafer, the process of forming the packaging structure is also simpler.
[0023] Furthermore, the chip unit in the semiconductor packaging structure of the present utility model includes an interposer and a chip located on the interposer. On the one hand, the interposer is an active silicon interposer, and active devices are provided in the active silicon interposer. Coupled with the chip located on the interposer, 3D stacking can be achieved. Stacking the chip unit on the metal interconnect layer of the glass wafer can achieve multi-dimensional stacking of 3D+3D. On the other hand, the interposer and the chip adopt a copper-copper micro-bump interconnection method, which can reduce the node pitch, increase the signal channels, and provide the transmission rate. Moreover, multiple chips with different functions can be co-packaged in the chip unit, which can be the co-packaging of logic storage to achieve the multi-functionality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] Figure 1 is a schematic structural diagram of the semiconductor packaging structure in the embodiment of the present utility model;
[0025] Figure 2 is a schematic structural diagram of a glass wafer provided;
[0026] Figure 3 is a schematic structural diagram after forming a first glass substrate on the glass wafer;
[0027] Figure 4 is a schematic structural diagram after grinding the second surface of the glass wafer and forming solder bumps at the positions of the exposed TGV metal pillars;
[0028] Figure 5 is a schematic structural diagram after forming a second glass substrate on the second surface of the glass wafer and removing the first glass substrate;
[0029] Figure 6 is a schematic structural diagram after forming a metal interconnect layer on the first surface of the glass wafer;
[0030] Figure 7 is a schematic structural diagram of a chip unit provided;
[0031] Figure 8 is a schematic structural diagram after connecting the chip unit to the metal interconnect layer.
[0032] LIST OF REFERENCE NUMERALS:
[0033] 100 Glass wafer
[0034] 101 First surface
[0035] 102 Second surface
[0036] 103 TGV metal pillar
[0037] 104 Solder bump
[0038] 105 Functional unit
[0039] 200 Metal Interconnection Layer
[0040] 300 Chip Unit
[0041] 301 Interposer
[0042] 3011 Active Device
[0043] 302 Chip
[0044] 3021 First Chip
[0045] 3022 Second Chip
[0046] 303 Dielectric Layer
[0047] 400 First Glass Substrate
[0048] 500 Second Glass Substrate Detailed Implementation Modes
[0049] The following specific embodiments illustrate the implementation modes of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation modes. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.
[0050] It should be noted that the diagrams provided in the embodiments of the present invention only illustrate the basic concept of the present invention in a schematic manner. Although only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation, the forms, quantities, and proportions of the components in actual implementation can be changed arbitrarily, and the layout form of the components may also be more complex. The structures, proportions, sizes, etc. shown in the accompanying diagrams of the specification are only used to cooperate with the content disclosed in the specification for those skilled in the art to understand and read, and are not used to limit the implementation conditions that the present application can implement. Therefore, they do not have technical essence. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope that the technical content disclosed in the present application can cover.
[0051] Embodiment 1
[0052] This embodiment provides a semiconductor package structure. Referring to Figure 1 , this semiconductor package structure includes a glass wafer 100, a metal interconnection layer 200, and a chip unit 300. Referring to Figure 2, the glass wafer 100 includes a first surface 101 and a second surface 102 which are oppositely arranged. A functional unit 105 is disposed within the glass wafer 100, and the functional unit 105 is exposed on the first surface 101. A metal interconnect layer 200 is disposed on the first surface 101 of the glass wafer 100 and is interconnected with the functional unit 105. A chip unit 300 is disposed on the surface of the metal interconnect layer 200 and forms a connection with the metal interconnect layer 200. Thus, in this embodiment, the semiconductor package structure uses the glass wafer 100 as a support substrate to form the semiconductor package structure. A functional unit 105, that is, a functional chip, is formed within the glass wafer 100. At the same time, bonding chips above the glass wafer 100 can achieve the stacked co-packaging of multiple chips, improving the integration degree of the package structure. Moreover, a high-density metal interconnect layer 200 can be formed on the surface of the glass wafer 100, thereby improving the signal transmission rate.
[0053] Specifically, referring to Figure 2 , a functional unit 105 is disposed within the glass wafer 100, and the functional unit 105 may include active devices or passive devices. The active device 3011 may be one or more of a logic device (logic IC), a memory device (HighBandwidth Memory; HBM), a converter (Switch), and a power management unit (Power Management Unit; PM). The passive device may be a resistor, an inductor, a capacitor, etc. The glass wafer 100 includes a first surface 101 and a second surface 102 which are oppositely arranged, and the functional unit 105 is exposed on the first surface 101. Moreover, TGV metal pillars 103 are also disposed within the glass wafer 100, and the TGV metal pillars 103 extend in the direction from the first surface 101 to the second surface 102 and penetrate through the glass wafer 100. Optionally, referring to Figure 6 , solder bumps 104 are further disposed on the second surface 102 of the glass wafer 100, and the solder bumps 104 form a connection with the TGV metal pillars 103 exposed on the second surface 102 of the glass wafer 100. The solder bumps 104 are used for subsequent bonding of the entire package structure to other substrates.
[0054] Referring to Figure 1 , the metal interconnect layer 200 is disposed on the first surface 101 of the glass wafer 100 and forms a connection with the functional unit 105 on the glass wafer 100. The metal interconnect layer 200 may be a damascene interconnect layer, a redistribution layer, or a combination of a damascene interconnect layer and a redistribution layer. Among them, the metal interconnect layer 200 includes a dielectric layer and metal wiring. The material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide, etc., and the material of the metal wiring may include copper, aluminum, etc. The material, number of layers, manufacturing method, etc. of the metal interconnect layer 200 may also be selected according to actual requirements, and this embodiment does not limit this.
[0055] The chip unit 300 may only include a chip 302, and the chip 302 is directly connected to the metal interconnection layer 200. At this time, the chip 302 can be connected to the metal interconnection layer 200 in a flip-chip mounting manner. Refer to Figure 7 , the chip unit 300 may also include an interposer 301 and a chip 302. The chip 302 is disposed on the interposer 301 and is connected to the interposer 301 through metal bumps on the chip 302. The interposer 301 of the chip unit 300 is disposed on the metal interconnection layer 200 and is connected to the metal interconnection layer 200. In this embodiment, the chip unit 300 includes an interposer 301 and a chip 302. By connecting the metal bumps on the chip 302 to the metal bumps on the interposer 301, compared with the method of directly flipping the chip 302 onto the metal interconnection layer 200, this embodiment uses the interposer 301 to connect the metal interconnection layer 200 and the chip 302. Through the connection form of the copper metal bumps on the interposer 301 and the copper metal bumps on the chip 302, the connection channels can be increased, the pin pitch can be reduced, and the transmission signal channels can be increased. In this embodiment, the interposer 301 is an active silicon interposer 301, and the active silicon interposer 301 includes active devices 3011, and the active devices 3011 are interconnected with the chip 302. Furthermore, the chip unit 300 in this embodiment includes a stack of multiple chips 302, realizing 3D stack packaging and having a higher integration level.
[0056] Optionally, refer to Figure 7 , the chip unit 300 includes a first chip 3021 and a second chip 3022, and the first chip 3021 and the second chip 3022 are spaced apart. Each chip 302 is connected to the active devices 3011 in the active silicon interposer 301. Optionally, both the first chip 3021 and the second chip 3022 are active devices 3011. The first chip 3021 is selected from one of an HBM chip, an IO chip, an SOC chip, a CPU chip, or a GPU chip, and the second chip is selected from one of an HBM chip, an IO chip, an SOC chip, a CPU chip, or a GPU chip. In this embodiment, the first chip 3021 is an SOC chip and the second chip 3022 is an HBM chip. Thus, the chip unit 300 can achieve co-packaging of logic and storage, making it more diverse.
[0057] Optionally, refer to Figure 7, on the interposer 301 within each chip unit 300, there is also a dielectric layer 303. The dielectric layer 303 fills the gap at the sidewall of the chip 302 and covers the surface of the chip 302. The dielectric layer 303 is used for protecting and encapsulating the chip unit 300. The material of the dielectric layer 303 can be silicon nitride, silicon oxide. It can also be a combination of one or more of, but not limited to, polyimide, silica gel, and epoxy resin. One or more of methods such as liquid encapsulation molding, vacuum lamination, and spin coating can be used to form the dielectric layer 303.
[0058] This embodiment provides a method for manufacturing a semiconductor package structure, and the manufacturing method includes:
[0059] S1: Provide a glass wafer, in which functional units are provided;
[0060] Specifically, referring to Figure 2 , provide a glass wafer 100, in which functional units 105 are provided. The functional units 105 can include active devices 3011 or passive devices. The active devices 3011 can be one or more of a logic device (logic IC), a memory device (High Bandwidth Memory; HBM), a converter (Switch), and a power management unit (Power Management Unit; PM). The passive devices are resistors, inductors, capacitors, etc. The glass wafer 100 includes a first surface 101 and a second surface 102 which are oppositely arranged, and the functional units 105 are exposed on the first surface 101. And, TGV metal pillars 103 are also provided in the glass wafer 100, and the TGV metal pillars 103 extend in the direction from the first surface 101 to the second surface 102 and penetrate through the glass wafer 100.
[0061] S2: Provide a first glass substrate on the first surface of the glass wafer;
[0062] Specifically, referring to Figure 3 , provide a first glass substrate, and adhere the glass substrate to the first surface 101 of the glass wafer 100. Optionally, a separation layer can be used to adhere the glass wafer 100 and the glass substrate. The first glass substrate 400 can be used as a support substrate for subsequent grinding or other operations on the second surface 102 of the glass wafer 100, and needs to be peeled off later. Optionally, the separation layer includes but is not limited to a tape and a polymer layer. For example, the separation layer can be selected as a photo-thermal conversion layer, and later, the separation layer can be heated by, for example, a laser until it fails and loses its adhesiveness, and then the first glass substrate 400 is removed.
[0063] S3: Grind and thin the second surface of the glass wafer to expose the TGV metal pillars inside the glass wafer, and form solder bumps on the TGV metal pillars on the second surface;
[0064] Specifically, refer to Figure 4 , and use chemical mechanical polishing (CMP) to grind the second surface 102 of the glass wafer 100 until the TGV metal pillars 103 inside the glass wafer 100 are exposed. After exposing the TGV metal pillars 103, solder bumps 104 are formed at the positions corresponding to the TGV metal pillars 103 on the second surface 102.
[0065] S4: Form a second glass substrate on the second surface of the glass wafer, and strip and remove the first glass substrate;
[0066] Specifically, refer to Figure 5 , bond the second glass substrate 500 on the second surface 102 of the glass wafer 100, and strip and remove the first glass substrate 400. Subsequently, using the second glass substrate 500 as the support substrate, perform subsequent step operations on the first surface 101 of the glass wafer 100.
[0067] S5: Form a metal interconnect layer on the first surface of the glass wafer;
[0068] Specifically, refer to Figure 6 , form a metal interconnect layer 200 on the first surface 101 of the glass wafer 100. The metal interconnect layer 200 includes a dielectric layer and metal wiring. The material of the dielectric layer may include silicon oxide, silicon nitride, or polyimide, etc. The material of the metal wiring can be copper.
[0069] S6: Provide a chip unit, place the chip unit on the metal interconnect layer, and make the chip unit form an electrical connection with the metal interconnect layer;
[0070] Specifically, refer to Figure 7 , provide a chip unit 300. The chip unit 300 may only include a chip 302, and the chip 302 is directly connected to the metal interconnect layer 200. At this time, the chip 302 can be connected to the metal interconnect layer 200 in a flip-chip mounting manner. The chip unit 300 may also include an interposer 301 and a chip 302, where the interposer 301 is disposed on the metal interconnect layer 200 and connected to the metal interconnect layer 200. The chip 302 is disposed on the interposer 301 and forms a connection through the metal bumps on the chip 302 and the metal bumps on the interposer 301. Metal bumps are also provided on the side of the interposer 301 facing away from the chip 302, and these metal bumps are used to form a connection with the metal interconnect layer 200.
[0071] S7: Remove the second glass substrate to form a semiconductor package structure.
[0072] Specifically, referring to Figure 8 , after forming the connection between the chip unit 300 and the metal interconnection layer 200, the second glass substrate 500 on the second surface 102 of the glass wafer 100 is removed to obtain a semiconductor package structure as shown in Figure 1 . Subsequently, the semiconductor package structure can be packaged on a PCB substrate.
[0073] In summary, the semiconductor package structure in the present utility model uses a glass wafer as a support substrate to form a semiconductor package structure. A functional unit, that is, a functional chip, is formed in the glass wafer. Bonding a chip above the glass wafer with the functional chip can achieve the stacked co-packaging of multiple chips, improving the integration degree of the package structure. Moreover, a high-density metal interconnection layer can be formed on the surface of the glass wafer, thereby improving the signal transmission rate. Compared with the existing glass substrate-level packaging, the interconnection density on the surface of the glass wafer is higher and the transmission rate is faster. The present utility model utilizes the manufacturability of the glass wafer, replaces the glass substrate-level packaging with the glass wafer, and realizes the 3D + 3D multi-chip system-level packaging of multi-chip vertical stacking. Due to the manufacturability of the glass wafer, the process of forming the package structure is also simpler.
[0074] The above embodiments are only illustrative of the principles and effects of the present utility model, and are not used to limit the present utility model. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present utility model. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present utility model should still be covered by the claims of the present utility model.
Claims
1. A semiconductor package structure, characterized in that, Comprising: A glass wafer, including a first surface and a second surface which are oppositely arranged, a functional unit is arranged in the glass wafer, and the functional unit is exposed on the first surface; A metal interconnection layer, arranged on the first surface of the glass wafer and connected to the functional unit; A chip unit, arranged on the surface of the metal interconnection layer and forming a connection with the metal interconnection layer.
2. The semiconductor package structure according to claim 1, wherein The chip unit includes a chip, and the chip is connected to the metal interconnection layer in a flip-chip mounting manner.
3. The semiconductor package structure according to claim 1, wherein, The chip unit includes: An interposer, arranged on the metal interconnection layer and connected to the metal interconnection layer; A chip, arranged on the interposer, and the chip forms a connection with the interposer through metal bumps.
4. The semiconductor package structure according to claim 3, wherein, The interposer is an active silicon interposer, and active devices are included in the active silicon interposer, and the active devices are interconnected with the chip.
5. The semiconductor package structure according to claim 4, wherein The chip unit includes a first chip and a second chip, the first chip and the second chip are arranged at intervals, and each chip is interconnected with the active devices in the active silicon interposer.
6. The semiconductor package structure according to claim 5, wherein The first chip is selected from one of HBM chips, IO chips, SOC chips, CPU chips or GPU chips, and the second chip is selected from one of HBM chips, IO chips, SOC chips, CPU chips or GPU chips.
7. The semiconductor package structure according to claim 3, wherein, A dielectric layer is further arranged on the interposer, and the dielectric layer fills the gap at the side wall of the chip above the interposer and covers the upper surface of the chip.
8. The semiconductor package structure according to claim 1, wherein, The metal interconnection layer is a damascene interconnection layer or a redistribution layer.
9. The semiconductor package structure according to claim 1, wherein TGV metal pillars are further included in the glass wafer, and the TGV metal pillars penetrate from the first surface of the glass wafer to the second surface.
10. The semiconductor package structure according to claim 1, wherein, Solder bumps are further arranged on the second surface of the glass wafer, and the solder bumps are connected to the TGV metal pillars exposed on the second surface.