Packaging device and electronic equipment

Abstract

The embodiment of the utility model provides a packaging device and electronic equipment, and relates to the technical field of semiconductor packaging. The packaging device comprises a substrate, a chip, an isolating layer, a plastic packaging layer and a plurality of bonding wires, the chip is arranged on the mounting surface of the substrate, the bonding wires electrically connect the chip with the substrate, the isolating layer wraps the bonding wires, the plastic packaging layer wraps the substrate, the chip, the bonding wires, the isolating layer and the plastic packaging layer are electrically connected with electrodes among ground networks of the substrate, and the bonding wires are electrically connected with the isolating layer and the plastic packaging layer. And the plastic packaging layer is made of a conductive plastic packaging material. Therefore, the bonding wires are isolated through the isolating layers, the bonding wires are also isolated from the substrate and the chip through the isolating layers, the plastic packaging layer is electrically connected with the electrodes between the ground networks of the substrate, namely, the plastic packaging layer is grounded, a return path is provided for signal wires in the packaging device, common-mode impedance between signals is reduced, and the reliability of the packaging device is improved. The common-mode crosstalk generated between the bonding wires is also reduced, the signal reflection condition is weakened, and the purpose of EMI shielding is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor packaging, and in particular, to a packaging device and an electronic device. Background Art

[0002] In electronic devices, electromagnetic interference (EMI) can cause signal quality degradation and, in severe cases, device failure.

[0003] For packaging products, traditional EMI shielding methods only solve the electromagnetic interference problems of the outside of the packaging product and the substrate circuit. For the current increasingly high integration of packaging products, the packaging process still mostly uses the bonding method of wire bonding, and the electromagnetic interference problem between high-density bonding wires is becoming more and more serious. At present, there is no effective solution to the electromagnetic interference problem between bonding wires. Summary of the Utility Model

[0004] In view of this, the purpose of the embodiments of the present utility model is to provide a packaging device and an electronic device to at least partially improve the above problems.

[0005] To achieve the above purpose, the technical solutions adopted in the embodiments of the present utility model are as follows:

[0006] In a first aspect, an embodiment of the present utility model provides a packaging device, which includes a substrate, a chip, an isolation layer, a plastic encapsulation layer, and a plurality of bonding wires;

[0007] The chip is disposed on the mounting surface of the substrate;

[0008] Each of the bonding wires electrically connects the chip to the substrate;

[0009] The isolation layer wraps each of the bonding wires;

[0010] The plastic encapsulation layer covers the substrate, the chip, each of the bonding wires, and the isolation layer;

[0011] The plastic encapsulation layer is electrically connected to the electrode between the ground network of the substrate; the material of the plastic encapsulation layer is a conductive plastic encapsulation material.

[0012] Optionally, each of the bonding wires connects the chip to the substrate by welding;

[0013] A first solder joint is formed at the welding position between the chip and each of the bonding wires; each of the first solder joints is located on the mesa of the chip;

[0014] A second solder joint is formed at the welding position between the substrate and each of the bonding wires; each of the second solder joints is located on the mounting surface of the substrate;

[0015] The cross-sectional area of the first solder joint and the cross-sectional area of the second solder joint are both larger than the cross-sectional area of the bonding wire;

[0016] The isolation layer also covers each of the first solder joints and each of the second solder joints.

[0017] Since the cross-sectional area of the solder joint is larger than the cross-sectional area of the bonding wire, the isolation layer can also cover each of the first solder joints and each of the second solder joints, further reducing the electromagnetic interference of each bonding wire.

[0018] Optionally, the isolation layer also covers the mounting surface of the substrate and the mesa of the chip.

[0019] Covering an isolation layer on the mounting surface of the substrate and the mesa of the chip can further isolate each bonding wire from the substrate and the chip, reducing the electromagnetic interference between each bonding wire and the substrate and the chip.

[0020] Optionally, the first solder joints are arranged side by side, and the perpendicular distances from the first solder joints to one side of the chip are equal;

[0021] The second solder joints are arranged staggeredly, and the perpendicular distances from the second solder joints to one side of the chip are different.

[0022] By arranging the second solder joints staggeredly, that is, the bonding wires are not neatly arranged, the bonding wires arranged in this way can reduce the occurrence of resonance at specific frequencies, thereby reducing the common-mode noise at these frequencies and reducing the common-mode crosstalk.

[0023] Optionally, there are more than five second solder joints. The perpendicular distances from the second solder joints to one side of the chip include two lengths. Taking the second solder joint with the farther perpendicular distance as the third solder joint and the second solder joint with the closer perpendicular distance as the fourth solder joint, the arrangement of each second solder joint is as follows:

[0024] Two fourth solder joints are respectively arranged on both sides of one third solder joint;

[0025] One third solder joint is respectively arranged on both sides of two fourth solder joints.

[0026] Further, on the basis of the staggered arrangement, by regularly arranging each second solder joint, the bonding wires can be made neater on the basis of reducing the industrial mode crosstalk.

[0027] Optionally, the material of the isolation layer is epoxy resin.

[0028] Optionally, the encapsulation layer also covers each of the first solder joints and each of the second solder joints;

[0029] The isolation layer isolates the encapsulation layer from the substrate, the chip, the bonding wires, the first solder joints, and the second solder joints.

[0030] Optionally, the conductive encapsulation material includes copper and / or carbon fiber.

[0031] Optionally, the packaged device further includes a heat conduction layer disposed on the bottom surface of the substrate.

[0032] In a second aspect, an embodiment of the present invention provides an electronic device including the packaged device according to any one of the first aspects above.

[0033] For the packaged device and the electronic device provided by the embodiment of the present invention, by wrapping an isolation layer around each bonding wire to isolate each bonding wire, the electromagnetic interference between the bonding wires is reduced. The electrode between the encapsulation layer and the ground network of the substrate is electrically connected, that is, the encapsulation layer is grounded, providing a return path for the internal signal lines of the packaged device, reducing the common-mode impedance between signals, and also reducing the common-mode crosstalk generated between the bonding wires, weakening the signal reflection situation, and achieving the purpose of EMI shielding.

[0034] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, is described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of a packaged device provided by an embodiment of the present invention;

[0037] Figure 2 It is another schematic structural diagram of a packaged device provided by an embodiment of the present invention;

[0038] Figure 3 It is another schematic structural diagram of a packaged device provided by an embodiment of the present invention;

[0039] Figure 4 It is a top view structural diagram of a packaged device provided by an embodiment of the present invention;

[0040] Figure 5 It is another top view structural diagram of a packaged device provided by an embodiment of the present invention;

[0041] Figure 6 This is another schematic structural view of a packaging device provided by an embodiment of the present invention.

[0042] Icon: 10 - packaging device; 11 - substrate; 12 - chip; 13 - isolation layer; 14 - bonding wire; 15 - first solder joint; 16 - second solder joint; 161 - third solder joint; 162 - fourth solder joint; 17 - plastic encapsulation layer; 18 - electrode; 19 - heat conduction layer. Detailed implementation manners

[0043] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0044] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0045] It should be noted that: similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0046] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, or the orientation or positional relationships when the product of the present invention is in its normal use, or the orientation or positional relationships commonly understood by those skilled in the art. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present invention.

[0047] In addition, the terms "first", "second", "third", etc. are only used for descriptive distinction and cannot be understood as indicating or implying relative importance.

[0048] In the description of the present utility model, it should also be noted that unless otherwise clearly specified and defined, the terms "arranged", "installed", "connected", and "linked" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0049] In electronic devices, electromagnetic interference will cause the signal quality to decline, and in severe cases, it will cause the device to fail. For packaged products, the traditional EMI shielding method only solves the electromagnetic interference problems outside the packaged product and on the circuit of the substrate 11. For the current increasingly high integration of packaged products, the packaging process still mostly uses the bonding method of wire bonding. The electromagnetic interference problem between the highly dense bonding wires 14 is becoming more and more serious.

[0050] Based on the above situation, the embodiments of the present utility model provide a packaged device 10 and an electronic device. By wrapping an isolation layer 13 on each bonding wire 14 to isolate each bonding wire 14, and electrically connecting the electrode 18 between the plastic package layer 17 and the ground network of the substrate 11, that is, the plastic package layer 17 is grounded, a return path is provided for the internal signal lines of the packaged device 10, the common-mode impedance between signals is reduced, the common-mode crosstalk generated between the bonding wires 14 is also reduced accordingly, the signal reflection situation is weakened, the electromagnetic interference between each bonding wire 14 is reduced, and the electromagnetic interference problem between the highly dense bonding wires 14 is solved.

[0051] The following will describe in detail some embodiments of the present utility model with reference to the drawings. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0052] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of a packaged device 10 provided by an embodiment of the present utility model. In the embodiment of the present utility model, the packaged device 10 includes a substrate 11, a chip 12, an isolation layer 13, a plastic package layer 17, and multiple bonding wires 14. The chip 12 is arranged on the mounting surface of the substrate 11. Each bonding wire 14 electrically connects the chip 12 and the substrate 11. The isolation layer 13 wraps each bonding wire 14. The plastic package layer 17 covers the substrate 11, the chip 12, each bonding wire 14, and the isolation layer 13. The electrode 18 between the plastic package layer 17 and the ground network of the substrate 11 is electrically connected. The material of the plastic package layer 17 is a conductive plastic package material.

[0053] For the dense bonding wires 14, an isolation layer 13 can be attached to the periphery of the bonding wires 14 by physical vapor deposition. That is, an insulating material is vaporized into molecules or atoms, and then the vaporized molecules or atoms are deposited on the bonding wires 14 through some means. The isolation layer 13 can be an insulating isolation film to isolate the bonding wires 14 from each other, thereby reducing the electromagnetic interference between the bonding wires 14.

[0054] The internal structure of the package is isolated from the plastic package layer 17 through the isolation layer 13, and the electrode 18 between the plastic package layer 17 and the ground network of the substrate 11 is electrically connected. That is, the plastic package layer 17 is grounded, providing a return path for the internal signal lines of the packaged device 10, reducing the common-mode impedance between the signals, and also reducing the common-mode crosstalk generated between the bonding wires 14, weakening the signal reflection, and achieving the purpose of EMI shielding.

[0055] There are various ways to electrically connect the chip 12 and the substrate 11 by the bonding wires 14. It can be that each bonding wire 14 connects the chip 12 and the substrate 11 by welding. Refer to Figure 2 , Figure 2 FIG. is another schematic structural diagram of a packaged device 10 provided by an embodiment of the present invention. First solder joints 15 are formed at the welding positions of the chip 12 and the bonding wires 14, and each first solder joint 15 is located on the mesa of the chip 12. Second solder joints 16 are formed at the welding positions of the substrate 11 and the bonding wires 14, and each second solder joint 16 is located on the mounting surface of the substrate 11. The cross-sectional areas of the first solder joints 15 and the second solder joints 16 are both larger than the cross-sectional area of the bonding wires 14. The isolation layer 13 also covers each first solder joint 15 and each second solder joint 16.

[0056] Welding will form solder joints on the chip 12 and the substrate 11. The cross-sectional area of the solder joints will be larger than the cross-sectional area of the bonding wires 14, and the solder joints will also have the function of electrical connection. They connect the chip 12 to the circuit board or its substrate 11 to ensure the smooth flow of current. Therefore, there will also be electromagnetic interference. The isolation layer 13 can also cover each first solder joint 15 and each second solder joint 16 to further reduce electromagnetic interference.

[0057] Furthermore, in order to reduce the electromagnetic interference between the bonding wires 14, the chip 12, and the substrate 11, refer to Figure 3 , Figure 3 FIG. is another schematic structural diagram of a packaged device 10 provided by an embodiment of the present invention. The isolation layer 13 can also cover the mounting surface of the substrate 11 and the mesa of the chip 12.

[0058] Conventional bonding wires 14 are arranged neatly, and each solder joint is basically on a straight line, and the bonding wires 14 are basically arranged in parallel, which will cause the problem of common-mode crosstalk. Therefore, in a possible implementation, the bonding wires 14 can be arranged staggeredly. Specifically, refer toFigure 4 , Figure 4 This is a top - view structural schematic diagram of a packaging device 10 provided by an embodiment of the present utility model. Each first solder joint 15 is arranged side by side, and the vertical distance from each first solder joint 15 to one side of the chip 12 is equal. Each second solder joint 16 is arranged staggeredly, and the vertical distance from each second solder joint 16 to one side of the chip 12 is different.

[0059] By arranging the first solder joints 15 neatly and the second solder joints 16 staggeredly, the staggered arrangement of each bonding wire 14 is naturally formed, which can reduce the occurrence of resonance at specific frequencies, thereby reducing the common - mode noise at these frequencies and reducing the common - mode crosstalk.

[0060] Furthermore, if the bonding wires 14 are arranged randomly, problems such as messy bonding wires 14 will occur. In order to keep the bonding wires 14 tidy while reducing the common - mode crosstalk, the second solder joints 16 can be arranged according to certain rules. In a possible implementation manner, referring to Figure 5 , Figure 5 This is another top - view structural schematic diagram of a packaging device 10 provided by an embodiment of the present utility model. The number of second solder joints 16 is more than five. The vertical distance from the second solder joints 16 to one side of the chip 12 includes two lengths. The second solder joint 16 with a longer vertical distance is defined as the third solder joint 161, and the second solder joint 16 with a shorter vertical distance is defined as the fourth solder joint 162. The arrangement mode of each second solder joint 16 is: two fourth solder joints 162 are respectively arranged on both sides of a third solder joint 161, and one third solder joint 161 is respectively arranged on both sides of the two fourth solder joints 162.

[0061] In this arrangement mode, that is, one third solder joint 161 and two fourth solder joints 162 are arranged in sequence. Through this arrangement mode, both the common - mode crosstalk can be reduced and a certain degree of tidiness can be maintained.

[0062] The specific arrangement mode is not limited. For example, it can also be one third solder joint 161 and one fourth solder joint 162 arranged in sequence.

[0063] The several lengths included in the vertical distance from the second solder joints 16 to one side of the chip 12 are not limited either. For example, it can be three lengths, and the specific arrangement mode can be correspondingly changed according to the specific situation.

[0064] The material of the isolation layer 13 can be made of epoxy resin. Epoxy resin has good mechanical strength and chemical stability, and can well implement the structure of this embodiment.

[0065] In this embodiment, an insulating isolation film is attached to exposed areas such as the periphery of the bonding wire 14, the mesa of the chip 12, and the mounting surface of the substrate 11 by physical vapor deposition, isolating the internal structure of the package from the plastic encapsulation layer 17, and then plastic encapsulation is performed using a conductive plastic encapsulant. The electrode 18 between the plastic encapsulation layer 17 and the ground network of the substrate 11 is electrically connected, that is, the plastic encapsulation layer 17 is grounded, providing a return path for the internal signal lines of the packaged device, reducing the common-mode impedance between signals, reducing the common-mode crosstalk generated between the bonding wires 14, weakening the signal reflection situation, and effectively suppressing the electromagnetic interference between the bonding wires 14.

[0066] The material used for plastic encapsulation can change its electrical conductivity and thermal conductivity through conditions such as molecular structure and additives. By introducing materials with excellent electrical and thermal conductivity, such as copper and carbon fiber, into the plastic encapsulation layer 17 to form a polymer composite material, while improving the electrical conductivity of the plastic encapsulation layer 17, the heat dissipation performance of the plastic encapsulation layer 17 can be well improved, and to a certain extent, the heat dissipation performance of the packaging structure can be improved.

[0067] To further improve the heat dissipation performance, the packaged device 10 may further include a heat conduction layer 19, see Figure 6 , Figure 6 which is another structural schematic diagram of a packaged device 10 provided by an embodiment of the present invention. The heat conduction layer 19 is disposed on the bottom surface of the substrate 11, and the heat conduction layer 19 can transfer the heat generated by electronic components such as the chip 12 and the substrate 11 out of the entire packaged device 10, thereby improving the heat dissipation performance of the packaged device 10.

[0068] In another embodiment, the electronic device includes the packaged device 10. When the electromagnetic interference of the packaged device 10 is reduced, the electronic device can also reduce electromagnetic interference and improve the signal quality of the electronic device.

[0069] In summary, a packaging device 10 and an electronic device provided by an embodiment of the present utility model. The packaging device 10 includes a substrate 11, a chip 12, an isolation layer 13, multiple bonding wires 14, a first solder joint 15, a second solder joint 16, a plastic encapsulation layer 17, and a heat conduction layer 19. The isolation layer 13 covers and wraps the substrate 11, the chip 12, the isolation layer 13, the multiple bonding wires 14, the first solder joint 15, and the second solder joint 16, isolating the plastic encapsulation layer 17 from these electronic components. The plastic encapsulation layer 17 is grounded, which can reduce the electromagnetic interference of each atomic component, provide a return path for the signal lines inside the packaging device, reduce the common-mode impedance between signals, and accordingly reduce the common-mode crosstalk generated between the bonding wires 14. The weakening of signal reflection can effectively suppress the electromagnetic interference between the bonding wires 14. Through the plastic encapsulation layer 17 and the heat conduction layer 19 made of a polymer composite material, while improving the conductivity of the plastic encapsulation layer 17, the heat dissipation performance of the plastic encapsulation layer 17 can be well improved, and to a certain extent, the heat dissipation performance of the packaging structure is improved. And by arranging the second solder joints 16 staggeredly, the common-mode crosstalk of the bonding wires 14 can be further reduced.

[0070] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

[0071] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present utility model, the present utility model can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in the present utility model. Any reference signs in the claims should not be regarded as limiting the claimed rights.

Claims

1. An encapsulation device, characterized in that, The encapsulated device includes a substrate, a chip, an isolation layer, a plastic encapsulation layer, and a plurality of bonding wires; The chip is disposed on the mounting surface of the substrate; Each of the bonding wires electrically connects the chip to the substrate; The isolation layer wraps around each of the bonding wires; The plastic encapsulation layer covers the substrate, the chip, each of the bonding wires, and the isolation layer; The electrode between the plastic encapsulation layer and the ground network of the substrate is electrically connected; the material of the plastic encapsulation layer is a conductive plastic encapsulation material.

2. The encapsulation device according to claim 1, characterized in that Each of the bonding wires connects the chip to the substrate by welding; A first solder joint is formed at the welding position between the chip and each of the bonding wires; each of the first solder joints is located on the chip's mesa; A second solder joint is formed at the welding position between the substrate and each of the bonding wires; each of the second solder joints is located on the mounting surface of the substrate; The cross-sectional area of the first solder joint and the cross-sectional area of the second solder joint are both larger than the cross-sectional area of the bonding wire; The isolation layer also covers each of the first solder joints and each of the second solder joints.

3. The encapsulation device according to claim 2, characterized in that, The isolation layer also covers the mounting surface of the substrate and the chip's mesa.

4. The encapsulated device according to claim 2, characterized in that, Each of the first solder joints is arranged side by side, and the perpendicular distance from each of the first solder joints to one side of the chip is equal; Each of the second solder joints is arranged staggeredly, and the perpendicular distance from each of the second solder joints to one side of the chip is different.

5. The encapsulation device according to claim 4, characterized in that, There are more than five second solder joints, and the perpendicular distance from the second solder joints to one side of the chip includes two lengths. The second solder joint with a farther perpendicular distance is defined as the third solder joint, and the second solder joint with a closer perpendicular distance is defined as the fourth solder joint. The arrangement of each of the second solder joints is as follows: Two fourth solder joints are arranged on both sides of one third solder joint; One third solder joint is arranged on both sides of two fourth solder joints.

6. The encapsulated device according to claim 1, wherein The material of the isolation layer is epoxy resin.

7. The encapsulated device according to claim 1, wherein The conductive plastic encapsulation material includes copper and / or carbon fiber.

8. The encapsulated device according to claim 1, characterized in that, The encapsulated device further includes a heat-conducting layer, and the heat-conducting layer is disposed on the bottom surface of the substrate.

9. An electronic device, characterized in that, Including the encapsulated device according to any one of claims 1 to 8.

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