Low-cost power supply circuit capable of preventing output end voltage from flowing backwards

Abstract

Aiming at the problems of high cost and backward flowing of the voltage at the output end of the conventional power supply circuit, the utility model provides the low-cost power supply circuit capable of preventing backward flowing of the voltage at the output end, which is a new circuit designed by using discrete devices such as two PMOS (P-channel Metal Oxide Semiconductor) tubes and two NMOS (N-channel Metal Oxide Semiconductor) tubes, and compared with the prior art, the cost is greatly reduced, and the backward flowing of the voltage at the output end can be prevented.

Description

Technical Field

[0001] The utility model belongs to the technical field of power supply circuits, and particularly relates to a low-cost power supply circuit for preventing output voltage backflow. Background Technique

[0002] Power supply circuits are widely used in automotive electronic products, such as power supply output for USB devices, power supply output for camera modules, power supply output for cooling fans, and so on. Currently, there are two most commonly used existing power supply circuit solutions. One is to directly use integrated chips from semiconductor companies, and the other is to mainly use discrete devices such as a PMOS transistor to form a power supply output circuit.

[0003] The disadvantages of the first solution of directly using integrated chips: Integrated chips generally have relatively high costs, and the dedicated integrated chips produced by each chip manufacturer are not universal. The input voltage, output voltage, and maximum output current are all restricted to varying degrees by the dedicated integrated chips.

[0004] The disadvantages of the second solution of using discrete devices such as a single PMOS transistor to form a power supply circuit: When the power supply circuit is turned off, if an external voltage is accidentally connected to the output terminal, the voltage will backflow to the input terminal of the power supply circuit. In the lightest case, it will cause the product's functions to malfunction and reduce the product's service life. In the worst case, it will cause the product to burn out. Content of the Utility Model

[0005] Based on this, in view of the above technical problems, a low-cost power supply circuit for preventing output voltage backflow is provided.

[0006] To solve the above technical problems, the utility model adopts the following technical solutions:

[0007] As a first aspect of the present utility model, a power supply circuit for preventing reverse voltage injection at the output end with low cost is provided, which is characterized by comprising a PMOS transistor Q1, a PMOS transistor Q2, a first resistor R1, a second resistor R2, an NMOS transistor Q3, an NMOS transistor Q4, a power signal input terminal POWER-IN, a power signal output terminal POWER-OUT, and a control signal terminal ON-OFF. The gate of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q3. The drain of the PMOS transistor Q1 is connected to the power signal input terminal POWER-IN. The source of the PMOS transistor Q1 is connected to the source of the PMOS transistor Q2. The gate of the PMOS transistor Q2 is connected to the drain of the NMOS transistor Q4. The drain of the PMOS transistor Q2 is connected to the power signal output terminal POWER-OUT. Two ends of the first resistor R1 are respectively connected to the gate and the source of the PMOS transistor Q1. Two ends of the second resistor R2 are respectively connected to the gate and the source of the PMOS transistor Q2. The gate of the NMOS transistor Q3 is connected to the control signal terminal ON-OFF. The source of the NMOS transistor Q3 is grounded. The gate of the NMOS transistor Q4 is connected to the control signal terminal ON-OFF. The source of the NMOS transistor Q4 is grounded.

[0008] As a second aspect of the present utility model, a power supply circuit for preventing reverse voltage injection at the output end with low cost is provided, which is characterized by comprising a PMOS transistor Q1, a PMOS transistor Q2, a first resistor R1, a second resistor R2, an NMOS transistor Q3, an NMOS transistor Q4, a power signal input terminal POWER-IN, a power signal output terminal POWER-OUT, and a control signal terminal ON-OFF. The gate of the PMOS transistor Q1 is connected to the drain of the NMOS transistor Q3. The source of the PMOS transistor Q1 is connected to the power signal input terminal POWER-IN. The drain of the PMOS transistor Q1 is connected to the drain of the PMOS transistor Q2. The gate of the PMOS transistor Q2 is connected to the drain of the NMOS transistor Q4. The source of the PMOS transistor Q2 is connected to the power signal output terminal POWER-OUT. Two ends of the first resistor R1 are respectively connected to the gate and the source of the PMOS transistor Q1. Two ends of the second resistor R2 are respectively connected to the gate and the source of the PMOS transistor Q2. The gate of the NMOS transistor Q3 is connected to the control signal terminal ON-OFF. The source of the NMOS transistor Q3 is grounded. The gate of the NMOS transistor Q4 is connected to the control signal terminal ON-OFF. The source of the NMOS transistor Q4 is grounded.

[0009] The power supply circuit for preventing reverse output voltage injection provided by the present utility model is a new circuit designed with discrete devices such as two PMOS transistors and two NMOS transistors. Compared with the prior art, the cost is greatly reduced, and at the same time, reverse voltage injection at the output end can be prevented. Description of the Drawings

[0010] Figure 1 This is a schematic structural diagram of the present utility model. Specific embodiments

[0011] The following will describe the embodiments of the present utility model in conjunction with the accompanying drawings of the specification. It should be noted that the embodiments involved in this specification are not exhaustive and do not represent the only embodiments of the present utility model. The following corresponding embodiments are only for clearly explaining the inventive content of the utility model patent of the present utility model, and do not limit its embodiments. For those of ordinary skill in the art, based on the description of this embodiment, different forms of changes and modifications can be made. Any changes or modifications that belong to the technical concept and inventive content of the present utility model and are obvious are also within the protection scope of the present utility model.

[0012] Embodiment 1

[0013] As Figure 1 shown, an embodiment of the present application provides a low-cost power supply circuit for preventing output terminal voltage backflow, including PMOS transistor Q1, PMOS transistor Q2, first resistor R1, second resistor R2, NMOS transistor Q3, NMOS transistor Q4, power signal input terminal POWER-IN, power signal output terminal POWER-OUT, control signal terminal ON-OFF, third resistor R3, fourth resistor R4, fifth resistor R5, sixth resistor R6, seventh resistor R7, eighth resistor R8, first capacitor C1, second capacitor C2, and resistor RL.

[0014] The gate of PMOS transistor Q1 is connected to the drain of NMOS transistor Q3 through the series-connected third resistor R3. The drain of PMOS transistor Q1 is connected to the power signal input terminal POWER-IN, and the source of PMOS transistor Q1 is connected to the source of PMOS transistor Q2.

[0015] The gate of PMOS transistor Q2 is connected to the drain of NMOS transistor Q4 through the series-connected fourth resistor R4. The drain of PMOS transistor Q2 is connected to the power signal output terminal POWER-OUT.

[0016] Both ends of the first resistor R1 are respectively connected to the gate and source of PMOS transistor Q1. Both ends of the second resistor R2 are respectively connected to the gate and source of PMOS transistor Q2.

[0017] The gate of NMOS transistor Q3 is connected to the control signal terminal ON-OFF through the series-connected fifth resistor R5. The source of NMOS transistor Q3 is grounded. One end of the sixth resistor R6 is connected to the gate of NMOS transistor Q3, and the other end is grounded.

[0018] The gate of NMOS transistor Q4 is connected to the control signal terminal ON - OFF through the serially connected seventh resistor R7. The source of NMOS transistor Q4 is grounded. One end of the eighth resistor R8 is connected to the gate of NMOS transistor Q4, and the other end is grounded.

[0019] One end of the first capacitor C1, the second capacitor C2, and the resistor RL are all connected to the drain of PMOS transistor Q2, and the other ends are all grounded.

[0020] When the control signal terminal ON - OFF is at a low level, NMOS transistors Q3 and Q4 are in the off state, and PMOS transistors Q1 and Q2 are both non - conductive. Since PMOS transistors Q1 and Q2 are used in pairs and the directions of the body diodes integrated inside them are opposite, when PMOS transistors Q1 and Q2 are not turned on, even if a power signal is applied from the power signal output terminal POWER - OUT, there will be no phenomenon of power voltage backflow, effectively preventing the voltage from flowing back to the input terminal.

[0021] When the control signal terminal ON - OFF is at a high level, NMOS transistors Q3 and Q4 are in the conductive state. The first resistor R1 and the second resistor R2 will divide enough voltage to turn on PMOS transistors Q1 and Q2, so as to supply the power from the power signal input terminal POWER - IN to the power signal output terminal POWER - OUT.

[0022] The third resistor R3 and the first resistor R1 form a voltage - dividing circuit to limit the gate current of PMOS transistor Q1 and prevent the gate current from being too large. Similarly, the fourth resistor R4 and the second resistor R2 form a voltage - dividing circuit to limit the gate current of PMOS transistor Q2 and prevent the gate current from being too large.

[0023] The fifth resistor R5 and the sixth resistor R6 form a voltage - dividing circuit to limit the gate current of NMOS transistor Q3 and prevent the gate current from being too large. The sixth resistor R6 also ensures that the voltage division between the gate and source of NMOS transistor Q3 obtains enough voltage to turn on.

[0024] The first capacitor C1 (4.7uF) and the second capacitor C2 (100nF) play a filtering role. The combination of a large - value capacitor and a small - value capacitor can filter out the clutter in different frequency bands and at the same time can reduce the equivalent series resistance ESR of the filtering capacitor.

[0025] The resistor RL is a load resistor.

[0026] Among them, NMOS transistor Q3 and PMOS transistor Q1 are turned on. Cooperating with R1, R2, R5, and R6, the voltage drop of the circuit in the embodiment of the present application can be extremely low. In general load applications, the voltage drop is only a few millivolts to dozens of millivolts, and the power supply efficiency is high. When the load is 249 mA, the circuit voltage drop is only 10 mV. For the existing single-PMOS transistor power supply circuit, in order to solve the problem of voltage backflow, a diode is often connected in series to prevent voltage backflow. However, the voltage drop of the diode is relatively large, generally between 0.3 V and 0.7 V. For low-voltage application circuits such as 1.8 V, 3.3 V, and 5 V, such a large voltage drop cannot meet the requirements.

[0027] Embodiment 2

[0028] The difference between Embodiment 2 and Embodiment 1 is that:

[0029] The source of PMOS transistor Q1 is connected to the power signal input terminal POWER-IN, and the drain of PMOS transistor Q1 is connected to the drain of PMOS transistor Q2.

[0030] The source of PMOS transistor Q2 is connected to the power signal output terminal POWER-OUT.

[0031] One end of the first capacitor C1, the second capacitor C2, and the resistor RL are all connected to the source of PMOS transistor Q2, and the other end is grounded.

[0032] This embodiment can also achieve the technical effects of Embodiment 1. The principle is the same as that of Embodiment 1 and will not be elaborated here.

[0033] As can be seen from the above, the low-cost power supply circuit for preventing output terminal voltage backflow provided by the present application is a new circuit designed using discrete devices such as two PMOS transistors and two NMOS transistors. Compared with the prior art, the cost is greatly reduced, and at the same time, output terminal voltage backflow can be prevented.

[0034] In addition, compared with the existing PMOS transistor power supply circuit, the present application has an ultra-low voltage drop and high power supply efficiency.

[0035] The input voltage, output voltage, and load current parameters of the existing integrated chip circuit are restricted by specific application selections. However, the present application has a wide range of input voltages, output voltages, and can flexibly adapt to various load output currents, improving the performance parameters of the circuit.

[0036] For the existing integrated chip circuit, since the chips produced by each manufacturer are not the same, the replaceability is poor. However, for the present application, since conventional resistors, capacitors, PMOS transistors, and NMOS transistors are used as basic discrete devices, the replaceable devices are very flexible and have excellent versatility.

[0037] Obviously, those of ordinary skill in the art should recognize that the above embodiments are only used to illustrate the present utility model and are not intended to limit the present utility model. As long as within the scope of the substantial spirit of the present utility model, changes and modifications to the above-described embodiments will fall within the scope of the claims of the present utility model.

Claims

1. A low-cost power supply circuit for preventing reverse voltage injection at the output terminal, characterized in that, It includes PMOS transistor Q1, PMOS transistor Q2, first resistor R1, second resistor R2, NMOS transistor Q3, NMOS transistor Q4, power signal input terminal POWER-IN, power signal output terminal POWER-OUT and control signal terminal ON-OFF. The gate of PMOS transistor Q1 is connected to the drain of NMOS transistor Q3. The drain of PMOS transistor Q1 is connected to power signal input terminal POWER-IN. The source of PMOS transistor Q1 is connected to the source of PMOS transistor Q2. The gate of PMOS transistor Q2 is connected to the drain of NMOS transistor Q4. The drain of PMOS transistor Q2 is connected to power signal output terminal POWER-OUT. Two ends of first resistor R1 are respectively connected to the gate and source of PMOS transistor Q1. Two ends of second resistor R2 are respectively connected to the gate and source of PMOS transistor Q2. The gate of NMOS transistor Q3 is connected to control signal terminal ON-OFF. The source of NMOS transistor Q3 is grounded. The gate of NMOS transistor Q4 is connected to control signal terminal ON-OFF. The source of NMOS transistor Q4 is grounded.

2. The power supply circuit for preventing reverse voltage injection at the output end with low cost according to claim 1, characterized in that, It further includes third resistor R3 and fourth resistor R4. Third resistor R3 is connected in series between the gate of PMOS transistor Q1 and the drain of NMOS transistor Q3. Fourth resistor R4 is connected in series between the gate of PMOS transistor Q2 and the drain of NMOS transistor Q4.

3. The power supply circuit for preventing reverse voltage injection at the output end with low cost according to claim 1, characterized in that, It further includes fifth resistor R5, sixth resistor R6, seventh resistor R7 and eighth resistor R8. Fifth resistor R5 is connected in series between control signal terminal ON-OFF and the gate of NMOS transistor Q3. One end of sixth resistor R6 is connected to the gate of NMOS transistor Q3 and the other end is grounded. Seventh resistor R7 is connected in series between control signal terminal ON-OFF and the gate of NMOS transistor Q4. One end of eighth resistor R8 is connected to the gate of NMOS transistor Q4 and the other end is grounded.

4. The power supply circuit for preventing reverse voltage injection at the output end with low cost according to claim 1, wherein, It further includes first capacitor C1, second capacitor C2 and resistor RL. One ends of first capacitor C1, second capacitor C2 and resistor RL are all connected to the drain of PMOS transistor Q2 and the other ends are all grounded.

5. A low-cost power supply circuit for preventing reverse voltage injection at the output end, characterized in that, It includes PMOS transistor Q1, PMOS transistor Q2, first resistor R1, second resistor R2, NMOS transistor Q3, NMOS transistor Q4, power signal input terminal POWER-IN, power signal output terminal POWER-OUT, and control signal terminal ON-OFF. The gate of PMOS transistor Q1 is connected to the drain of NMOS transistor Q3. The source of PMOS transistor Q1 is connected to power signal input terminal POWER-IN. The drain of PMOS transistor Q1 is connected to the drain of PMOS transistor Q2. The gate of PMOS transistor Q2 is connected to the drain of NMOS transistor Q4. The source of PMOS transistor Q2 is connected to power signal output terminal POWER-OUT. Both ends of the first resistor R1 are respectively connected to the gate and source of PMOS transistor Q1. Both ends of the second resistor R2 are respectively connected to the gate and source of PMOS transistor Q2. The gate of NMOS transistor Q3 is connected to control signal terminal ON-OFF. The source of NMOS transistor Q3 is grounded. The gate of NMOS transistor Q4 is connected to control signal terminal ON-OFF. The source of NMOS transistor Q4 is grounded.

6. The power supply circuit for preventing reverse voltage injection at the output end with low cost according to claim 5, wherein It further includes third resistor R3 and fourth resistor R4. The third resistor R3 is connected in series between the gate of PMOS transistor Q1 and the drain of NMOS transistor Q3. The fourth resistor R4 is connected in series between the gate of PMOS transistor Q2 and the drain of NMOS transistor Q4.

7. The power supply circuit for preventing reverse voltage injection at the output end with low cost according to claim 5, characterized in that, It further includes fifth resistor R5, sixth resistor R6, seventh resistor R7, and eighth resistor R8. The fifth resistor R5 is connected in series between control signal terminal ON-OFF and the gate of NMOS transistor Q3. One end of the sixth resistor R6 is connected to the gate of NMOS transistor Q3, and the other end is grounded. The seventh resistor R7 is connected in series between control signal terminal ON-OFF and the gate of NMOS transistor Q4. One end of the eighth resistor R8 is connected to the gate of NMOS transistor Q4, and the other end is grounded.

8. The power supply circuit for preventing output terminal voltage backflow with low cost according to claim 5, characterized in that, It further includes first capacitor C1, second capacitor C2, and resistor RL. One ends of the first capacitor C1, second capacitor C2, and resistor RL are all connected to the source of PMOS transistor Q2, and the other ends are all grounded.

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