Power supply identification grading circuit and radio frequency switch system
By designing a power identification and grading circuit, and using the VDD gear identification module and the step-down module to control the PMOS tube, the problem of large area occupancy of the voltage regulator module is solved, and the chip area and voltage compatibility of the RF switching system are reduced.
Patent Information
- Application Number
- CN202422860982.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-11-22
AI Technical Summary
In the prior art, the voltage regulator module occupies a large area and is difficult to compatible with the input voltages of multiple fixed gear positions, resulting in the chip area of the RF switching system being unable to effectively reduce.
A power identification and grading circuit is designed to control the conduction or shutdown of the PMOS tube through the VDD gear identification module, and combine it with the step-down module to achieve gear compatibility of the input voltage, replacing the function of the voltage regulator module, saving chip area.
It realizes that when compatible with multiple fixed gear input voltages, it effectively saves chip area and meets the system's low power consumption requirements.
Smart Images
Figure CN223157064U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of radio frequency front - end chips, in particular to a power supply identification grading circuit and a radio frequency switch system. Background Art
[0002] With the continuous development of technology, people's demand for radio frequency front - end devices (such as power amplifiers, active antenna tuners, low - noise amplifiers, and antenna switches, etc.) is increasing continuously. The integration degree of radio frequency chip modules on the whole - machine system board is continuously strengthened. For equipment manufacturers, the wiring resources of chip interfaces, including the working voltage, are becoming increasingly tense. At the same time, the requirement of system low power consumption promotes the optimization of the working voltage in the direction of low voltage. The digital control voltage on the system board is generally 1.2V. Taking the radio frequency switch as an example, the working voltage is generally 2.8V, and it is required that the working voltage needs to be compatible with 1.8V or even 1.2V to work properly, so as to intensively use the wiring resources of the working voltage.
[0003] The design of radio frequency switches has called for the reuse of underlying module calls like building blocks to shorten the product development cycle. In response to the change of the external input voltage VDD, in the prior art, the following solutions are generally adopted: call the reused voltage regulator module to convert the external input voltage VDD, especially high voltage, to the internal voltage Vint suitable for the internal level. The voltage regulator module is suitable for wide - range voltage conversion, but this circuit module occupies a large area and does not meet the trend requirement of continuous chip shrinkage.
[0004] Therefore, how to design an input power supply identification grading circuit with a smaller occupied area, which can be compatible with the input voltage VDD of several fixed grades (2.8V / 1.8V / 1.2V) and be used in the radio frequency switch system, is an urgent problem to be solved. Summary of the Utility Model
[0005] In view of this, the purpose of the utility model is to solve the problem that the voltage regulator module, including the band - gap module and the LDO module, occupies a large chip area. For the case where the input voltage VDD is mainly a fixed voltage (2.8V / 1.8V / 1.2V), the on - off of the PMOS transistor is controlled by the grading identification circuit. When the input voltage VDD is at a higher grade, the buck module with a fixed buck amplitude is enabled to reduce the voltage to the range corresponding to the lower grade, so as to achieve the function of replacing the voltage regulator module, realize the compatibility of the input voltage VDD grades and save the chip area at the same time.
[0006] To achieve the above purpose, the utility model provides a power supply identification grading circuit, including a VDD grading identification module, a buck circuit switch, and a buck module;
[0007] The step-down circuit switch is a PMOS transistor; the step-down module includes a step-down diode or a plurality of step-down diodes connected in series; the step-down circuit switch is connected in parallel with the step-down module and is connected across the input end and the output end of the power supply identification grading circuit;
[0008] The input end of the VDD gear identification module is electrically connected to the input end of the power supply identification grading circuit, and the output end of the VDD gear identification module 110 is electrically connected to the control end of the step-down circuit switch;
[0009] The VDD gear identification module includes a peak current source, a constant current source and a current comparator, and the peak current source and the constant current source are respectively electrically connected to the current comparator; the VDD gear identification module is used to output a low voltage signal and turn off the step-down circuit switch when the input voltage VDD is the voltage corresponding to a preset first VDD gear, and output a high voltage signal and turn on the step-down circuit switch when the input voltage VDD is the voltage corresponding to a preset second VDD gear, and the voltage corresponding to the first VDD gear is less than the voltage corresponding to the second VDD gear.
[0010] Preferably, the peak current source includes a first resistor and a Nagata current mirror, and two ends of the first resistor are respectively electrically connected to the input end of the VDD gear identification module and the input end of the Nagata current mirror.
[0011] Preferably, the Nagata current mirror includes a first NMOS transistor, a second NMOS transistor and a second resistor; the source electrodes of the first NMOS transistor and the second NMOS transistor are grounded; two ends of the second resistor are respectively electrically connected to the drain electrode of the first NMOS transistor and the gate electrode of the first NMOS transistor; the gate electrode of the second NMOS transistor is electrically connected to the drain electrode of the first NMOS transistor; the threshold voltages of the first NMOS transistor and the second NMOS transistor are the same.
[0012] Preferably, the constant current source includes a Widlar current mirror; the constant current source further includes a third PMOS transistor and a fourth PMOS transistor arranged in cascode, and the third PMOS transistor and the fourth PMOS transistor are used to maintain the reference current and the output current of the Widlar current mirror to be equal.
[0013] Preferably, the Widlar current mirror includes a fifth NMOS transistor, a sixth NMOS transistor, and a third resistor R3; the sources of the third PMOS transistor and the fourth PMOS transistor are electrically connected to the input terminal of the VDD gear recognition module; the gates of the third PMOS transistor and the fourth PMOS transistor are electrically connected to the drain of the fourth PMOS transistor; the drain of the fifth NMOS transistor is electrically connected to the drain of the third PMOS transistor; the drain of the sixth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is grounded; both ends of the third resistor R3 are electrically connected to the source of the sixth NMOS transistor and the ground terminal respectively; the third PMOS transistor MP3 and the fourth PMOS transistor have the same device parameters; the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor are the same; the channel width-to-length ratio of the sixth NMOS transistor is K times that of the fifth NMOS transistor, where K>1.
[0014] Preferably, the VDD grading identification circuit includes a first parallel branch, a second parallel branch, a third parallel branch, a fourth parallel branch, a fifth parallel branch, and a sixth parallel branch; the first to sixth parallel branches are respectively connected in parallel between the input end and the ground end of the VDD grading identification circuit; the first parallel branch includes a first resistor R1, a second resistor R2, and a first NMOS transistor connected in series in sequence; the second parallel branch includes a first PMOS transistor and a second NMOS transistor connected in series and sharing the same drain; the third parallel branch includes a second PMOS transistor and a third NMOS transistor connected in series and sharing the same drain; the fourth parallel branch includes a third PMOS transistor and a fifth NMOS transistor connected in series and sharing the same drain; the fifth parallel branch includes a fourth PMOS transistor, a sixth NMOS transistor, and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS transistor and a fourth NMOS transistor connected in series and sharing the same drain; the sources of the first to fifth PMOS transistors are electrically connected to the input end of the VDD grading identification circuit; the sources of the first to fifth NMOS transistors are grounded; the drains of the sixth NMOS transistor and the fourth PMOS transistor are electrically connected, and the source of the sixth NMOS transistor is electrically connected to the third resistor R3; the drain of the fifth PMOS transistor is electrically connected to the output end of the VDD grading identification module; the gate of the first NMOS transistor is electrically connected to the circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS transistor is electrically connected to the drain of the first NMOS transistor; the gates of the third NMOS transistor and the fourth NMOS transistor are electrically connected to the drain of the third NMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected to the drain of the fifth NMOS transistor; the gates of the first PMOS transistor and the second PMOS transistor are electrically connected to the drain of the first PMOS transistor; the gates of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are electrically connected to the drain of the fourth PMOS transistor.
[0015] Preferably, the buck module specifically includes a buck diode, the first VDD grading is the 1.2V grading, and the second VDD grading is the 1.8V grading.
[0016] Preferably, the buck module specifically includes two buck diodes connected in series, the first VDD grading is the 1.8V grading, and the second VDD grading is the 2.8V grading.
[0017] On the other hand, the present utility model provides a radio frequency switch system, which includes a decoder module, a driver module, a charge pump module, a radio frequency switch and the aforementioned power supply identification and grading circuit; the power supply identification and grading circuit is electrically connected to the input end, the decoder module and the driver module of the radio frequency switch system respectively, and the power supply identification and grading circuit is used to convert the input voltage of the radio frequency switch system into an internal voltage; the decoder module is used to decode the control coding signal and provide a control signal to the driver module; the decoder module and the driver module are electrically connected to the charge pump module respectively, and the charge pump module is electrically connected to the radio frequency switch.
[0018] The beneficial effects of the present utility model are as follows:
[0019] For the case where the input voltage VDD is mainly a fixed voltage (2.8V / 1.8V / 1.2V), through the identification circuit inside the chip, the on or off of the PMOS transistor is controlled, so as to achieve the function of replacing the voltage regulator module, realize the compatibility of the input voltage VDD grades and save the chip area at the same time. Description of the Drawings
[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0021] Figure 1 It is a circuit structure block diagram of the radio frequency switch system;
[0022] Figure 2 It is a circuit structure block diagram of the power supply identification and grading circuit in Embodiment 1;
[0023] Figure 3 It is a circuit structure block diagram of the VDD grade identification module in the embodiment of the present utility model;
[0024] Figure 4 It is a circuit diagram of a Nagata current mirror based on NMOS transistors;
[0025] Figure 5 It is the I out —I in Schematic diagram of the relationship curve;
[0026] Figure 6 It is a circuit diagram of the peak-shaped current source in the embodiment of the present utility model;
[0027] Figure 7 It is a circuit diagram of the constant current source in the embodiment of the present utility model;
[0028] Figure 8 It is the circuit diagram of the VDD gear recognition module in the embodiment of the present utility model;
[0029] Figure 9 It is the circuit simulation result diagram of the first embodiment;
[0030] Figure 10 It is the circuit structure block diagram of the power supply recognition and grading circuit of the second embodiment. Specific implementation manners
[0031] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.
[0032] Figure 1The circuit structure block diagram of a radio frequency switch system in the prior art is shown. The function of the radio frequency switch system is to connect any one or several of multiple radio frequency signals through control logic to achieve the switching of different signal paths, including the switching between reception and transmission, the switching between different frequency bands, etc. The radio frequency switch system includes a voltage regulator module 100a, a decoder module 200, a driver module 300, a charge pump module 400, and several radio frequency switches 500. The voltage regulator module 100a is electrically connected to the VDD terminal and is used to convert the input voltage VDD into the internal working voltage Vint of the system and supply power to modules such as the decoder module 200 and the driver module 300; the decoder module 200 receives control coding signals from the control coding terminals CTL0 to CTL2, and after decoding, controls the driver module 300 to generate corresponding driving signals to drive the conduction or cutoff of the radio frequency switch 500; the decoder module 200 and the driver module 300 are respectively electrically connected to the charge pump module 400; the charge pump module 400 is electrically connected to the radio frequency switch 500 and is used to provide a bias voltage to the radio frequency switch 500. The voltage regulator module 100a usually includes a bandgap module and a low-dropout linear regulator module (LDO), and the chip occupation area is relatively large, which does not meet the requirements of the continuous chip shrinking trend. Considering that the voltage regulator module 100a is suitable for wide-range voltage conversion in terms of function, while the input voltage VDD of the radio frequency switch system usually has only several fixed gears (2.8V / 1.8V / 1.2V), the function of the voltage regulator module 100a is redundant. Therefore, customizing a circuit module dedicated to compatible conversion between the fixed gears of the above input voltage VDD to replace the voltage regulator module 100a in the prior art can further save the chip area and improve the chip performance while achieving the same function.
[0033] Embodiment 1
[0034] Figure 2The structural block diagram of the power supply identification grading circuit 100b of this embodiment is shown, including a VDD grading identification module 110 (VDD detect), a buck circuit switch 120, and a buck module. The buck circuit switch 120 is a PMOS transistor, and the buck module includes a diode 131. The input end of the power supply identification grading circuit 100b is used to connect to the input voltage VDD, and the output end of the power supply identification grading circuit 100b is used to output the internal voltage Vint used by the RF switch system. The buck circuit switch 120 and the buck module are connected in parallel and are connected across the input end and the output end of the power supply identification grading circuit 100b. The input end of the VDD grading identification module 110 is electrically connected to the input end of the power supply identification grading circuit 100b (i.e., connected to the input voltage VDD), and the output end of the VDD grading identification module 110 is electrically connected to the control end of the buck circuit switch 120 (i.e., the gate of the PMOS transistor). The power supply identification grading circuit 100b is used for the application where the input voltage VDD is compatible with 1.8V and 1.2V. Since the conduction voltage drop of a single diode is 0.6V, it can be directly used as the buck module to save chip area. During operation, when the VDD grading identification module 110 detects that the input voltage VDD is 1.8V, the output voltage is high, that is, VOUT = VDD, the PMOS transistor is turned off, and at this time, the output voltage of the power supply identification grading circuit 100b, that is, the internal voltage Vint = 1.8 - 0.6V = 1.2V; when the VDD grading identification module 110 detects that the input voltage VDD is 1.2V, the output voltage is low, that is, VOUT = 0, the PMOS transistor is turned on, and at this time, the output voltage of the power supply identification grading circuit 100b, that is, the internal voltage Vint = VDD = 1.2V.
[0035] Figure 3 The structural block diagram of the circuit of the VDD grading identification module 110 is shown. The VDD grading identification module includes a peak current source 111, a constant current source 112, and a current comparator 113. The peak current source 111 includes a Nagata current mirror, and the constant current source 112 includes a Widlar current mirror. The input ends of both are electrically connected to the input end of the VDD grading identification module 110 (i.e., connected to the input voltage VDD), and the output ends of both are respectively electrically connected to the current comparator 113. The current comparator 113 is used to compare the output current magnitudes of the peak current source 111 and the constant current source 112 and output the corresponding output voltage VOUT of the VDD grading identification module 110 according to the comparison result.
[0036] Figure 4Shows the circuit structure of a Nagata current mirror, including a first NMOS transistor MN1, a second NMOS transistor MN2, and a second resistor R2. The source electrodes of the first NMOS transistor MN1 and the second NMOS transistor MN2 are grounded; the second resistor R2 is connected across the drain and gate of the first NMOS transistor MN1; the gate of the second NMOS transistor MN2 is electrically connected to the drain of the first NMOS transistor MN1; the gate of the first NMOS transistor is used as the input terminal of the Nagata current mirror, and its input current is I in ; the drain of the second NMOS transistor MN2 is used as the output terminal of the Nagata current mirror, and its output current is I out (Nagata). The first NMOS transistor MN1 and the second NMOS transistor MN2 are fabricated on the chip by the same batch of manufacturing process, and their threshold voltages V t1 and V t2 are the same. During operation, both the first NMOS transistor MN1 and the second NMOS transistor MN2 operate in the saturation region. The principle of the Nagata current mirror is as follows:
[0037] According to Kirchhoff's voltage law of the circuit, the formula (1) can be obtained:
[0038] V gs1 -I in R2 = V gs2 (1);
[0039] Since V t1 = V t2 , the formula (2) can be further obtained:
[0040] V gs1 -V t1 -I in R2 = V gs2 -V t2 (2);
[0041] And further substituting the output characteristics of the MOS transistor in the saturation region, that is, the formula (3):
[0042]
[0043] Then the relationship between I in and I out (Nagata) can be obtained as the formula (4):
[0044]
[0045] In the formula: R2 is the resistance value of the second resistor; V gs1 and V gs2 are the gate-source voltage differences of the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively (V gsVoltage); I is the drain current of the NMOS transistor, and the drain current of the first NMOS transistor MN1 is the input current I in , and the drain current of the second NMOS transistor MN2 is the output current I out (Nagata); V t is the threshold voltage of the NMOS transistor; k n is the transconductance parameter of the NMOS transistor, k n = μ n ·c ox , that is, the product of the carrier mobility μ n and the gate oxide capacitance per unit area c ox ; (W / L) is the channel width-to-length ratio of the MOS device, and its subscripts 1 and 2 correspond to the first NMOS transistor MN1 and the second NMOS transistor MN2 respectively.
[0046] As Figure 5 shown, the I out —I in curve of the Nagata current mirror is a curve with a peak shape. I out (Nagata) reaches the peak at I in which is the first input current I in1 , and is smaller when deviated. As Figure 6 shown, a first resistor R1 is connected between the input end of the Nagata current mirror and the input voltage VDD to form the peak-shaped current source 111 of this embodiment, and a current related to the input voltage VDD can be output, and its relationship curve is also a curve with a peak shape.
[0047] Figure 7The constant current source 112 of this embodiment is shown, which includes a pair of cascode PMOS transistors (the third PMOS transistor MP3 and the fourth PMOS transistor MP4) and a Widlar current mirror. The Widlar current mirror includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, and a third resistor R3. The source electrodes of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are electrically connected to the input end of the constant current source 112 (i.e., connected to the input voltage VDD). The gate electrodes of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are electrically connected to the drain electrode of the fourth PMOS transistor MP4. The drain electrode of the fifth NMOS transistor MN5 is electrically connected to the drain electrode of the third PMOS transistor MP3. The drain electrode of the sixth NMOS transistor MN6 is electrically connected to the drain electrode of the fourth PMOS transistor MP4. The gate electrodes of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are electrically connected to the drain electrode of the fifth NMOS transistor. The source electrode of the fifth NMOS transistor MN5 is grounded. The third resistor R3 is connected across the source electrode of the sixth NMOS transistor MN6 and the ground terminal. The third PMOS transistor MP3 and the fourth PMOS transistor have the same device parameters, including the threshold voltage, transconductance parameter, and channel width-to-length ratio. The fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 have the same threshold voltage and transconductance parameter. The channel width-to-length ratio of the sixth NMOS transistor MN6 is K times that of the fifth NMOS transistor, where K > 1. Each MOS transistor operates in the saturation region.
[0048] Due to the same device parameters and the cascode third PMOS transistor MP3 and fourth PMOS transistor MP4 mirroring the output current I out (Widlar) of the Widlar current mirror back to the reference current I ref , making their magnitudes the same. Therefore, similarly, according to Kirchhoff's voltage law and the output characteristics in the saturation region of the MOS transistor, the relationship between I out (Widlar) and the device parameters of each component is given by Equation (5):
[0049]
[0050] In the formula: R3 is the resistance value of the third resistor; k n is the transconductance parameter of the NMOS transistor, (W / L) is the channel width-to-length ratio of the MOS device. Its subscript 5 corresponds to the fifth NMOS transistor MN5, and correspondingly, the channel width-to-length ratio (W / L)6 of the sixth NMOS transistor MN6 = K·(W / L)5;
[0051] It can be seen from this that when operating in the saturation region, the output current I out (Widlar) of the Widlar current mirror is independent of the input voltage VDD and can be determined by the device parameters of the circuit components. By setting appropriate device parameters, the output current I of the Nagata current mirrorout (Nagata) is greater than the output current I of the Widlar current mirror within a preset range where the input voltage VDD is around 1.2V out (Widlar), then the current comparator 113 can output a low voltage signal VOUT = 0 within this preset range (for example, VDD < 1.4V); when the input voltage VDD is around 1.8V, the output current I of the Nagata current mirror out (Nagata) then attenuates to be significantly less than the output current I of the Widlar current mirror out (Widlar), then the current comparator 113 can output a high voltage signal VOUT = VDD.
[0052] Figure 8The specific device circuit diagram of the VDD gear recognition module 110 of this embodiment is further shown, including first to sixth parallel branches, and the first to sixth parallel branches are connected across the input terminal and the ground terminal; the first parallel branch includes a first resistor R1, a second resistor R2, and a first NMOS transistor MN1 connected in series in sequence; the second parallel branch includes a first PMOS transistor MP1 and a second NMOS transistor MN2 connected in series and sharing the drain; the third parallel branch includes a second PMOS transistor MP2 and a third NMOS transistor MN3 connected in series and sharing the drain; the fourth parallel branch includes a third PMOS transistor MP3 and a fifth NMOS transistor MN5 connected in series and sharing the drain; the fifth parallel branch includes a fourth PMOS transistor MP4, a sixth NMOS transistor MN6, and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS transistor MP5 and a fourth NMOS transistor MN4 connected in series and sharing the drain; the sources of the first to fifth PMOS transistors MP1 / 2 / 3 / 4 / 5 are electrically connected to the input terminal; the sources of the first to fifth NMOS transistors MP1 / 2 / 3 / 4 / 5 are grounded; the sixth NMOS transistor MN6 and the fourth PMOS transistor MP4 are electrically connected with a common drain, and the source of the sixth NMOS transistor MN6 is electrically connected to the third resistor R3; the drain of the fifth PMOS transistor MP5 is electrically connected to the output terminal of the VDD gear recognition module 110; the gate of the first NMOS transistor MN1 is electrically connected to the circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS transistor MN2 is electrically connected to the drain of the first NMOS transistor MN1; the gates of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are electrically connected to the drain of the third NMOS transistor MN3; the gates of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 are electrically connected to the drain of the fifth NMOS transistor MN5; the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are electrically connected to the drain of the first PMOS transistor MP1; the gates of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fifth PMOS transistor MP5 are electrically connected to the drain of the fourth PMOS transistor MP4. Among them, the circuit parts of the peak current source 111 and the constant current source 112 are shown in a dashed box, and the remaining PMOS transistors and NMOS transistors are used to mirror the current and implement the function of the current comparator 113.
[0053] Figure 9 The simulation result diagram of this circuit is shown. The abscissa in the figure is the input voltage VDD, and the upper peak curve (blue) corresponds to I out (Nagata), the constant current curve (red) corresponds to I out (Widlar), and the lower voltage curve (green) corresponds to the output voltage VOUT of the VDD gear recognition module 110. It can be seen from the figure that the output voltage VOUT is 0 between 0.7V and 1.4V, and is the input voltage VDD above 1.5V.
[0054] Based on Figure 1 , the structure of the RF antenna system of this embodiment can be obtained by replacing the voltage regulator module 100a in the prior art with the power supply identification grading circuit 100b of this embodiment. That is, the RF switch system of this embodiment includes a power supply identification grading circuit 100b, a decoder module 200, a driver module 300, a charge pump module 400, and a plurality of RF switches 500. The power supply identification grading circuit 100b is electrically connected to the VDD terminal, and is used to convert the input voltage VDD into the internal working voltage Vint of the system, and supply power to modules such as the decoder module 200 and the driver module 300; the decoder module 200 receives control coding signals from the control coding terminals CTL0 to CTL2, and after decoding, provides control signals to the driver module 300, and the driver module 300 further drives the conduction or cut-off of the RF switch 500; the decoder module 200 and the driver module 300 are respectively electrically connected to the charge pump module 400; the charge pump module 400 is electrically connected to the RF switch 500, and is used to provide a bias voltage to the RF switch 500.
[0055] Embodiment 2
[0056] The difference between this embodiment and Embodiment 1 is that the power supply identification grading circuit 100c as Figure 10 shown is used to replace the power supply identification grading circuit 100b in Embodiment 1.
[0057] Figure 10The structural block diagram of the power supply identification grading circuit 100c of this embodiment is shown, including a VDD grading identification module 110 (VDD detect), a buck circuit switch 120, and a buck module. The buck circuit switch 120 is a PMOS transistor, and the buck module includes two diodes 131 / 132 connected in series. The input end of the power supply identification grading circuit 100c is used to connect the input voltage VDD, and the output end of the power supply identification grading circuit 100c is used to output the internal voltage Vint used by the RF switch system. The buck circuit switch 120 and the buck module are connected in parallel and are connected across the input end and the output end of the power supply identification grading circuit 100c. The input end of the VDD grading identification module 110 is electrically connected to the input end of the power supply identification grading circuit 100c (i.e., connected to the input voltage VDD), and the output end of the VDD grading identification module 110 is electrically connected to the control end of the buck circuit switch 120 (i.e., the gate of the PMOS transistor). The power supply identification grading circuit 100c is used for the input voltage VDD to be compatible with applications of 2.8V and 1.8V. During operation, when the VDD grading identification module 110 detects that the input voltage VDD is 2.8V, the output voltage is high, that is, VOUT = VDD, and the PMOS transistor is turned off. At this time, the output voltage of the power supply identification grading circuit 100c, that is, the internal voltage Vint = 2.8 - 2×0.6V = 1.6V; when the VDD grading identification module 110 detects that the input voltage VDD is 1.8V, the output voltage is low, that is, VOUT = 0, and the PMOS transistor is turned on. At this time, the output voltage of the power supply identification grading circuit 100c, that is, the internal voltage Vint = VDD = 1.8V. Since the internal voltage Vint of the RF switch system can still operate normally when it deviates from the rated value by 0.2V, the method of realizing grading compatibility through the power supply identification grading circuit 100c can greatly save the chip area occupied by the circuit while meeting the application requirements.
[0058] Compared with the first embodiment, the circuit topology of the VDD grading identification module 110 in this embodiment remains unchanged, but the device parameters are different. Those skilled in the art can adjust the relevant device parameters (such as adjusting the channel width-length ratio W / L and the resistance values of each resistor) according to the foregoing formulas (1) to (5) and simulation and other methods to make the module meet the identification function requirements during the operation of this embodiment.
[0059] In a preferred embodiment, the power supply identification grading circuit 100c and the power supply identification grading circuit 100b can be connected in series and multiplexed to be compatible with three fixed voltage grades.
[0060] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present utility model. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present utility model. Therefore, the present utility model will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A power supply identification and grading circuit, characterized in that It includes a VDD gear recognition module, a buck circuit switch, and a buck module; The buck circuit switch is a PMOS transistor; the buck module includes a buck diode or multiple buck diodes connected in series; the buck circuit switch and the buck module are connected in parallel and are connected across the input and output terminals of the power supply recognition grading circuit; The input terminal of the VDD gear recognition module is electrically connected to the input terminal of the power supply recognition grading circuit, and the output terminal of the VDD gear recognition module is electrically connected to the control terminal of the buck circuit switch; The VDD gear recognition module includes a peak current source, a constant current source, and a current comparator. The peak current source and the constant current source are respectively electrically connected to the current comparator. The VDD gear recognition module is used to output a low voltage signal and turn off the buck circuit switch when the input voltage VDD is the voltage corresponding to a preset first VDD gear, and output a high voltage signal and turn on the buck circuit switch when the input voltage VDD is the voltage corresponding to a preset second VDD gear. The voltage corresponding to the first VDD gear is less than the voltage corresponding to the second VDD gear.
2. The power supply identification and grading circuit according to claim 1, wherein The peak current source includes a first resistor and a Nagata current mirror. The two ends of the first resistor are respectively electrically connected to the input terminal of the VDD gear recognition module and the input terminal of the Nagata current mirror.
3. The power supply identification and grading circuit according to claim 2, wherein The Nagata current mirror includes a first NMOS transistor, a second NMOS transistor, and a second resistor; the source electrodes of the first NMOS transistor and the second NMOS transistor are grounded; the two ends of the second resistor are respectively electrically connected to the drain electrode and the gate electrode of the first NMOS transistor; the gate electrode of the second NMOS transistor is electrically connected to the drain electrode of the first NMOS transistor; the threshold voltages of the first NMOS transistor and the second NMOS transistor are the same.
4. The power supply identification and grading circuit according to claim 1, wherein The constant current source includes a Widlar current mirror; the constant current source further includes a third PMOS transistor and a fourth PMOS transistor arranged in cascode, and the third PMOS transistor and the fourth PMOS transistor are used to maintain the reference current and the output current of the Widlar current mirror to be equal.
5. The power supply identification and grading circuit according to claim 4, characterized in that The Widlar current mirror includes a fifth NMOS transistor, a sixth NMOS transistor, and a third resistor R3; the sources of the third PMOS transistor and the fourth PMOS transistor are electrically connected to the input terminal of the VDD grading identification module; the gates of the third PMOS transistor and the fourth PMOS transistor are electrically connected to the drain of the fourth PMOS transistor; the drain of the fifth NMOS transistor is electrically connected to the drain of the third PMOS transistor; the drain of the sixth NMOS transistor is electrically connected to the drain of the fourth PMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected to the drain of the fifth NMOS transistor; the source of the fifth NMOS transistor is grounded; both ends of the third resistor R3 are respectively electrically connected to the source of the sixth NMOS transistor and the ground terminal; the third PMOS transistor MP3 and the fourth PMOS transistor have the same device parameters; the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor are the same; the channel width-to-length ratio of the sixth NMOS transistor is K times that of the fifth NMOS transistor, where K > 1.
6. The power supply identification and grading circuit according to claim 1, characterized in that The VDD grading identification circuit includes a first parallel branch, a second parallel branch, a third parallel branch, a fourth parallel branch, a fifth parallel branch, and a sixth parallel branch; the first to sixth parallel branches are respectively connected in parallel between the input terminal and the ground terminal of the VDD grading identification circuit; the first parallel branch includes a first resistor R1, a second resistor R2, and a first NMOS transistor connected in series in sequence; the second parallel branch includes a first PMOS transistor and a second NMOS transistor connected in series and sharing the same drain; the third parallel branch includes a second PMOS transistor and a third NMOS transistor connected in series and sharing the same drain; the fourth parallel branch includes a third PMOS transistor and a fifth NMOS transistor connected in series and sharing the same drain; the fifth parallel branch includes a fourth PMOS transistor, a sixth NMOS transistor, and a third resistor R3 connected in series in sequence; the sixth parallel branch includes a fifth PMOS transistor and a fourth NMOS transistor connected in series and sharing the same drain; the sources of the first to fifth PMOS transistors are electrically connected to the input terminal of the VDD grading identification circuit; the sources of the first to fifth NMOS transistors are grounded; the sixth NMOS transistor and the fourth PMOS transistor are electrically connected with a common drain, and the source of the sixth NMOS transistor is electrically connected to the third resistor R3; the drain of the fifth PMOS transistor is electrically connected to the output terminal of the VDD grading identification module; the gate of the first NMOS transistor is electrically connected to the circuit node between the first resistor R1 and the second resistor R2; the gate of the second NMOS transistor is electrically connected to the drain of the first NMOS transistor; the gates of the third NMOS transistor and the fourth NMOS transistor are electrically connected to the drain of the third NMOS transistor; the gates of the fifth NMOS transistor and the sixth NMOS transistor are electrically connected to the drain of the fifth NMOS transistor; the gates of the first PMOS transistor and the second PMOS transistor are electrically connected to the drain of the first PMOS transistor; the gates of the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are electrically connected to the drain of the fourth PMOS transistor.
7. The power supply identification grading circuit according to claim 1, wherein The step-down module specifically includes a step-down diode. The first VDD level is the 1.2V level, and the second VDD level is the 1.8V level.
8. The power supply identification grading circuit according to claim 1, wherein, The step-down module specifically includes two step-down diodes connected in series. The first VDD level is the 1.8V level, and the second VDD level is the 2.8V level.
9. A radio frequency switch system, characterized in that, It includes a decoder module, a driver module, a charge pump module, a radio frequency switch, and the power supply identification grading circuit according to any one of claims 1 to 8; the power supply identification grading circuit is electrically connected to the input end of the radio frequency switch system, the decoder module, and the driver module respectively. The power supply identification grading circuit is used to convert the input voltage of the radio frequency switch system into an internal voltage; the decoder module is used to decode the control coding signal and provide a control signal to the driver module; the decoder module and the driver module are electrically connected to the charge pump module respectively, and the charge pump module is electrically connected to the radio frequency switch.