Chip packaging verification substrate and chip verification device

Abstract

The utility model provides a chip packaging verification substrate and a chip verification device. The verification substrate specifically comprises a PCB substrate; a plurality of chip to-be-verified areas which have different sizes and are nested on the surface of the PCB substrate; the plurality of jacks are arranged around the edge of the PCB substrate; wherein each of the plurality of chip to-be-verified areas comprises a chip bonding area and a golden finger area which is arranged around the chip bonding area in a surrounding manner; the chip bonding area is used for fixing a to-be-verified chip, and the shape and the size of the chip bonding area are matched with those of the to-be-verified chip; the golden finger area comprises a plurality of golden fingers, and the golden fingers are used for being electrically connected with a PAD of a chip to be verified; and the plurality of golden fingers in the to-be-verified area of any chip are respectively and electrically connected with the plurality of jacks with the same number. According to the verification substrate and the corresponding device, packaging measurement can be carried out on to-be-measured chips of various sizes on the same equipment.

Description

Technical Field

[0001] The present application relates to the technical field of chip packaging, and specifically, the present application relates to a chip packaging verification substrate and a chip verification device that can be applied to chip packaging of multiple sizes. Background Art

[0002] Currently, there are various sizes of chips in the market, so the demand for chip packaging testing is also increasing day by day. When testing a chip, first, a PCB substrate needs to be selected according to the size of the chip to be tested. After selecting a suitable-sized PCB substrate, the chip to be tested is fixed on the PCB substrate, so as to implement the function of testing the chip.

[0003] However, the functions of chips to be tested of different sizes and the requirements for the length of bonding leads are also different. Therefore, different-sized PCB substrates are required to adapt to chips to be tested of various sizes, which brings a lot of trouble to the chip packaging testing work, and even may require remaking the PCB substrate according to the size of the chip to be tested.

[0004] In summary, how to enable a PCB substrate to test chips to be tested of multiple sizes to make the chip packaging testing work faster and more convenient is a problem that needs to be solved currently. Content of the Utility Model

[0005] To solve or improve the above problems existing in the prior art, a first aspect of the present application provides a chip packaging verification substrate, which specifically includes:

[0006] A PCB substrate;

[0007] A plurality of chip areas to be verified, the sizes of the plurality of chip areas to be verified are different from each other, and they are nested on the surface of the PCB substrate;

[0008] A plurality of jacks, which are arranged around the edge of the PCB substrate;

[0009] Wherein, each of the plurality of chip areas to be verified includes a die bonding area, and a finger area surrounding the die bonding area; the die bonding area is used to fix the chip to be verified, and its shape and size are adapted to the chip to be verified; the finger area includes a plurality of fingers, and the fingers are used for electrical connection with the PADs of the chip to be verified; for any one of the plurality of chip areas to be verified, the plurality of fingers are respectively electrically connected to the same number of jacks.

[0010] The verification substrate provided by the foregoing technical solution is provided with chip verification regions of different sizes, specifically including a die bonding region for bonding chips of different sizes, and a gold finger region adapted to be connected to PADs (bonding pads) on chips of different sizes through bonding wires. A plurality of gold fingers are arranged on the gold finger region. This verification substrate is compatible with common chip models on the market, and its application can achieve the purpose of quickly packaging the chips to be tested, ensuring the timeliness of subsequent tests.

[0011] Moreover, through the setting of the gold fingers, the PADs on the chip can optionally select appropriate gold fingers and be electrically connected through bonding wires, and connecting to any gold finger can ensure that there is a unique jack electrically connected to it.

[0012] Optionally, in multiple nested chip verification regions, the gold fingers in the inner chip verification region are sequentially electrically connected to the jacks via the gold fingers in one or more outer chip verification regions.

[0013] During use, only the gold fingers in the gold finger region closest to the chip to be verified need to be selected and connected to it. Therefore, connecting the multiple gold fingers on the inner and outer sides in series helps to reduce the number of internal electrical connection lines in the PCB board. More importantly, it can avoid or reduce the interference between the internal electrical connection lines.

[0014] Optionally, the shapes of the multiple chip verification regions are adapted to the shapes of the chips to be verified, and their outer perimeters are rectangular;

[0015] Among them, the distances between the multiple gold fingers on each side in each chip verification region are equal, and they are aligned neatly in both the horizontal and vertical directions;

[0016] Among them, the internal electrical connection lines between the gold fingers in the same direction or opposite directions are parallel to each other.

[0017] The above optional solutions can make the internal electrical connection lines between the gold fingers on the PCB board "horizontal and vertical", with a clear and reasonable layout, which is more conducive to connecting the PADs to the gold fingers through bonding wires during the chip verification step, and connecting the jacks (or the pin headers / wiring posts soldered thereon) to the external test device. In other words, it can enable users to easily judge the electrical connection correspondence between the gold fingers and jacks on the substrate.

[0018] Optionally, the multiple chip verification regions include:

[0019] The inner-layer chip verification region includes a rectangular die bonding region and a gold finger region surrounding the rectangular die bonding region;

[0020] The outer-layer chip verification region nested outside the inner-layer chip verification region includes a rectangular frame-shaped die bonding region and a gold finger region surrounding the rectangular frame-shaped die bonding region;

[0021] Among them, the gold fingers in the area to be verified of the inner-layer chip are electrically connected in one-to-one correspondence through internal electrical connection lines to the gold fingers in the area to be verified of the outer-layer chip on the same side, and the gold fingers in the area to be verified of the outer-layer chip are electrically connected in one-to-one correspondence with the jacks on the same side.

[0022] Furthermore, the multiple areas to be verified of the chips further include:

[0023] One or more middle-layer chip areas to be verified, including a rectangular bonding area and a gold finger area surrounding the rectangular bonding area;

[0024] The middle-layer chip area to be verified is nested between the inner-layer chip area to be verified and the outer-layer chip area to be verified;

[0025] The gold fingers on the same side in the inner-layer chip area to be verified, one or more middle-layer chip areas to be verified, and the outer-layer chip area to be verified are electrically connected in sequence through internal electrical connection lines in a one-to-one correspondence.

[0026] In the foregoing solution, multiple areas to be verified of the chips are formed, nested layer by layer from the inside to the outside, which is suitable for chips to be verified of various sizes.

[0027] From another perspective, each area to be verified of the chip includes a bonding area and a gold finger area. The verification substrate as a whole presents a structural form of bonding area, gold finger area, bonding area, gold finger area... nested layer by layer. The bonding areas are spaced between two adjacent gold finger areas, having a good insulation effect, avoiding the influence of the electromagnetic induction phenomenon between different gold finger areas on chip testing. And, beneficial effects of minimizing the wire bonding time and the wire bonding length can be achieved.

[0028] Optionally, the internal electrical connection lines between the multiple gold fingers and the multiple jacks in the outer-layer chip area to be verified are arranged radially and do not intersect each other. It can avoid the mutual interference of the internal electrical connection lines between the outer gold fingers and the jacks, the wiring structure is clear, and the length of the internal electrical connection lines can be minimized as much as possible.

[0029] Optionally, in any two adjacent chip areas to be verified:

[0030] All the gold fingers in the inner chip area to be verified are electrically connected in one-to-one correspondence to the gold fingers in the outer chip area to be verified on the same side;

[0031] Some of the gold fingers in the outer chip area to be verified are electrically connected in one-to-one correspondence to the gold fingers in the inner chip area to be verified on the same side.

[0032] In the foregoing alternative solutions, since the number of PADs to be connected for chips of different sizes is different, generally, larger chips require a larger number of PADs to be connected and more gold fingers. On the other hand, a larger number of gold fingers can also adapt to the changes in the positions of PADs on larger chips, providing connection points as close as possible to the PADs thereon, which helps to shorten the length of bonding wires, is easy to operate and can reduce failures. In view of this, in the foregoing alternative solutions, more gold fingers are arranged on the edges of the chip area to be verified closer to the outside. To ensure that all gold fingers can be reasonably connected to the jacks, each inner gold finger in the foregoing alternative solution is connected layer by layer to the relatively outer gold fingers until it is connected to the outermost gold finger, so that when each chip area to be verified becomes effective (when the chip to be verified is installed), the connection between the gold fingers in the chip area to be verified and the jacks is unique, and there will be no situation where one gold finger is correspondingly connected to multiple jacks.

[0033] In the foregoing alternative technical solutions, the die bonding area is used to fix the chip to be verified through insulating glue; the gold fingers are used to electrically connect the PADs of the chip to be verified through bonding wires.

[0034] In the foregoing alternative technical solutions, the jacks are used to weld the pin headers, and the gold fingers in the gold finger area have the same shape and size.

[0035] In another aspect of the present application, a chip verification device is further provided. This verification device specifically includes:

[0036] A chip package verification substrate described in the foregoing technical solution or any of its alternative solutions, and a measuring device for measuring the chip to be verified.

[0037] In summary, the above technical solutions can at least achieve the following beneficial effects:

[0038] The verification substrate provided by the present application, and the verification device including this verification substrate, based on the multiple die bonding areas of different sizes provided on the PCB board, can fix and connect multiple chips to be measured of different sizes, have better reusability, not only save material costs and time costs, but also make the chip package testing work more convenient and faster.

[0039] More importantly, the verification substrate provided by the present application, while installing the chip to be verified, can make the length of the bonding wires led out from the chip PADs as short as possible, reduce the wire bonding time, and effectively reduce the influence of the electromagnetic induction phenomenon between the wire bonds / wires on the chip testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The drawings are used to provide a further understanding of the present application and constitute a part of this specification. The drawings illustrate the embodiments of the present application and are used to explain the principles of the present application together with the following description.

[0041] Figure 1 Shows a schematic diagram of the three - view planar structure of a chip verification substrate provided by an embodiment of the present application;

[0042] Figure 2 Shows a schematic diagram of the three - dimensional structure of a chip verification substrate provided by an embodiment of the present application;

[0043] Figure 3 Shows a connection schematic diagram between multiple chip regions to be verified and jacks on a chip verification substrate provided by an embodiment of the present application;

[0044] Figure 4 Shows a connection schematic diagram between multiple chip regions to be verified on a chip verification substrate provided by an embodiment of the present application;

[0045] Figure 5 Shows a connection schematic diagram between an inner - layer chip region to be verified with a size of 2mm×2mm and a chip to be verified provided by an embodiment of the present application;

[0046] Figure 6 Shows a connection schematic diagram between a middle - layer chip region to be verified with a size of 5mm×5mm and a chip to be verified provided by an embodiment of the present application;

[0047] Figure 7 Shows a connection schematic diagram between an outer - layer chip region to be verified with a size of 10mm×10mm and a chip to be verified provided by an embodiment of the present application.

[0048] In the figure, the reference numerals respectively represent:

[0049] 1: PCB substrate;

[0050] 2: Chip region to be verified, 21: Inner - layer chip region to be verified, 22: Outer - layer chip region to be verified, 23: Middle - layer chip region to be verified, 201: Die - bonding region, 202: Gold - finger region;

[0051] 3: Gold - finger;

[0052] 4: Jack;

[0053] 5: Internal electrical connection line;

[0054] 6: Bonding wire. Detailed implementation manners

[0055] In this specification, it will also be understood that when an element is described as relative to other elements, such as "connected to" other elements, the one element can be directly connected to or directly coupled to the one element, or there may also be an intervening third element. And "connection" in this specification particularly refers to electrical connection.

[0056] Unless otherwise specified, the "internal electrical connection lines" in this specification refer to the copper circuits or copper film conductors arranged on the PCB (printed circuit board). The "PAD" in this specification refers to the metal contact area on the chip for electrical connection, and its material can be a good conductor (electric) such as aluminum, copper, or gold. This specification does not make any limitations on this.

[0057] In addition, unless otherwise specified, the "same-direction gold fingers" in this specification refer to, for example, Figure 4 in, the multiple gold fingers arranged on the same-direction edges of multiple gold finger areas, for example, Figure 4 the first and second columns of gold fingers on the leftmost side. Similarly, the "opposite-direction gold fingers" refer to the multiple gold fingers on the opposite two edges of the same or different gold finger areas, for example, Figure 4 any two columns of gold fingers on the left and right sides are the "opposite-direction gold fingers".

[0058] The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the present application can be implemented in many different ways and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. The same reference numerals throughout the drawings denote the same components.

[0059] Hereinafter, exemplary embodiments according to the present application will be described with reference to the accompanying drawings.

[0060] In view of the defects in the prior art, a chip package verification substrate applicable to chip packages of various sizes is provided in the present application, aiming to at least improve the versatility of the tools during chip package testing. At the same time, a verification tool / device including such a verification substrate is also provided.

[0061] For the aforementioned verification substrate, as shown in the three views: Figure 1 and the perspective view: Figure 2 As shown, the substrate includes a plurality of chip areas to be verified 2, specifically, for example, the "hui"-shaped multi-layer nested chip areas to be verified 2 presented in the figure.

[0062] The verification substrate includes a PCB substrate 1 for carrying the area and structure.

[0063] The chip area to be verified 2 shown in the figure is disposed on one surface of the PCB substrate 1, which is a typical implementation, but the present application is not limited thereto. In one embodiment, the aforementioned areas and structures can be disposed on both the front and back sides of the PCB substrate, and can be selectively utilized, so that there can be more chip areas to be verified 2 with different sizes on the PCB substrate 1 to adapt to more chips to be verified with different sizes.

[0064] In a preferred embodiment of the present application, as Figure 1 or Figure 2 shown, the sizes of different chip areas to be verified are set according to the types of chip sizes on the market. It is expected to achieve the purpose of encapsulating / verifying chips with multiple sizes through one substrate and improving the versatility of the verification substrate.

[0065] The number of chip areas to be verified can be as many as possible, not limited to the three shown in the drawings, so as to adapt to more chips to be verified with different sizes, thereby improving the utilization rate of the verification substrate.

[0066] In a typical embodiment, as Figure 1 and Figure 2 shown, each chip area to be verified of this verification substrate includes an inner die bonding area and a finger area surrounding the die bonding area. Obviously, in each chip area to be verified, the die bonding area and the finger area are also arranged in a "hui" shape.

[0067] In some embodiments, the die bonding area may not be provided in some chip areas to be verified, and the die bonding area in the innermost chip area to be verified can be used to fix the chip.

[0068] In an embodiment, each die bonding area is used to fix a chip to be verified that is adapted to the size of this area (or the chip area to be verified including this area). The finger area is used to realize the electrical connection between the chip to be verified and the verification substrate, and then to an external test instrument. Therefore, a plurality of fingers are provided in the finger area, and the bonding wires led out from the chip PAD can be welded to the fingers, and are connected to the jacks through the internal electrical connection lines, and then connected to external devices.

[0069] In an embodiment, the fingers can be attached to the PCB board, such as a good conductor (electric) sheet structure of a pad structure, and are electrically connected to the corresponding copper film wires in the PCB board or the flying wires provided on the PCB board according to the wiring method described in the embodiments of the present application.

[0070] In an embodiment, the bonding wires can be, for example, silicon-aluminum wires or gold wires with a diameter of about 30 μm.

[0071] In a typical embodiment, multiple gold fingers on the gold finger region are arranged in a row along each side of the gold finger region respectively. During use, for example Figure 7 as shown, adjacent PADs on the chip can be respectively connected to the gold fingers in the same direction (arranged on the same side of the gold finger region) as far as possible through bonding wires. For example Figure 7 on the left side in, the gold fingers at the upper and lower ends are respectively connected, so as to minimize the interference or other mutual influences between the bonding wires.

[0072] In the embodiment of the present application, the verification substrate further includes a plurality of jacks, which are arranged on the PCB substrate, and the plurality of jacks are arranged around the periphery of the PCB substrate. The jacks are electrically connected to the gold fingers through internal electrical connection lines or flying wires.

[0073] In an alternative embodiment, the length and width of the gold finger are 0.8 mm and 0.2 mm respectively.

[0074] Among them, since the verification substrate of the embodiment of the present application has a plurality of gold finger regions, for any one gold finger region, the plurality of gold fingers therein are electrically connected to the same number of jacks among the plurality of jacks in a one-to-one correspondence.

[0075] In summary, a verification substrate provided by the embodiment of the present application can set chip regions to be verified with various sizes on the substrate to fix the chips to be verified adapted to each size, so as to achieve the purpose of testing chips to be verified with various sizes using one substrate. When encountering chips to be verified with different sizes and functions, it is not necessary to frequently replace the PCB substrate adapted to the size of the chip to be verified, saving time and cost, achieving the purpose of rapid packaging, and thus ensuring the timeliness of testing.

[0076] In an embodiment, as Figure 3 、 4 shown, in the nested chip regions 21, 22, 23 to be verified, each gold finger in the relatively inner chip region to be verified is electrically connected to one of the jacks 4 through the gold fingers in one or more relatively outer chip regions to be verified in sequence.

[0077] In an embodiment, as Figure 4 shown, the multiple chip regions 21, 22, 23 to be verified are rectangles or rectangular frames, and their outer perimeters are all rectangular shapes; among them, the internal electrical connection lines 5 between the gold fingers in different chip regions 2 to be verified are parallel or perpendicular to the sides of the rectangle or rectangular frame; the distances between the multiple gold fingers on each side in each chip region 2 to be verified are equal, and they are aligned neatly in both the vertical and horizontal directions; among them, the internal electrical connection lines 5 between the gold fingers in the same direction or opposite directions are parallel to each other.

[0078] More specifically, it includes:

[0079] The inner chip area to be verified 21, as Figure 5 shown, includes a rectangular die bonding area and a finger area 202 surrounding the rectangular die bonding area;

[0080] The outer chip area to be verified 22 nested outside the inner chip area to be verified 21, as Figure 7 shown, includes a rectangular frame die bonding area and a finger area 202 surrounding the rectangular frame die bonding area;

[0081] Among them, the fingers in the inner chip area to be verified 21 are electrically connected in position to the fingers in the outer chip area to be verified 22 in the same direction through the internal electrical connection lines 5, and the fingers in the outer chip area to be verified 22 are electrically connected to the jacks in the same direction. The connection method between the fingers and the jacks and the layout of the internal electrical connection lines are as Figure 3 shown.

[0082] More specifically, it further includes:

[0083] One or more middle chip areas to be verified 23, as Figure 6 shown, includes a rectangular frame die bonding area and a finger area 202 surrounding the rectangular frame die bonding area; the middle chip area to be verified 23 is nested between the inner chip area to be verified 21 and the outer chip area to be verified 22; the fingers in the inner chip area to be verified 21, one or more middle chip areas to be verified 23 and the outer chip area to be verified 22 in the same direction are electrically connected in position in sequence through the internal electrical connection lines 5.

[0084] In a typical embodiment, as Figure 4 shown, it includes a finger area provided with fingers 3 arranged and a die bonding area between two finger areas ( Figure 4 represented by the blank area in). In Figure 4 , from the innermost to the outermost, they are in sequence: the die bonding area of the inner chip area to be verified 21 (the central rectangle in the figure), the finger area of the inner chip area to be verified 21, the die bonding area of the middle chip area to be verified 23, the finger area of the middle chip area to be verified 23, the die bonding area of the outer chip area to be verified 22, the finger area of the outer chip area to be verified 22.

[0085] In a preferred embodiment, as Figure 3 shown, the internal electrical connection lines 5 between the multiple fingers in the outer chip area to be verified 22 and the multiple jacks are arranged radially and do not intersect each other.

[0086] As Figure 4As shown, in a typical embodiment, in any two adjacent chip areas to be verified 2: all the gold fingers in the inner chip area to be verified are electrically connected to the gold fingers in the outer chip area to be verified in the same direction; some of the gold fingers in the outer chip area to be verified are electrically connected to the gold fingers in the inner chip area to be verified in the same direction.

[0087] For the embodiment of the present application, the adhesive region 201 is used to fix the chip to be verified by insulating glue. Figures 5 to 7 As shown, the gold finger is used to electrically connect the PAD of the chip to be verified through the bonding wire 6.

[0088] In the embodiment of the present application, the socket 4 is used for welding the pin header.

[0089] In the embodiments of the present application, the gold fingers in each gold finger area have the same shape and size.

[0090] Regarding the number of chip regions to be verified, in a typical embodiment, Figure 1 or Figure 2 As shown, the verification substrate specifically includes an inner chip to be verified area 21, a middle chip to be verified area 23 and an outer chip to be verified area 22 which are sequentially embedded and arranged on the surface of the PCB substrate 1 from the inside to the outside. Among them, the size of the inner chip to be verified area 21 is smaller than the size of the middle chip to be verified area 23, and the size of the middle chip to be verified area 23 is smaller than the size of the outer chip to be verified area 22, that is, the middle chip to be verified area 23 is embedded and arranged inside the outer chip to be verified area 22, and the inner chip to be verified area 21 is embedded and arranged inside the middle chip to be verified area 23.

[0091] Optional, such as Figure 5 As shown, the inner chip verification area 21 includes a 2mm×2mm adhesive area 201 and a gold finger area 202 arranged around the adhesive area 201. The adhesive area 201 can fix the chip to be verified that is adapted to the size by, for example, insulating glue. The gold finger area 202 is in a rectangular ring shape, and the inside of the ring is the aforementioned adhesive area. Optionally, 8 gold fingers are arranged around the adhesive area, that is, 8 gold fingers are arranged inside the four sides of the gold finger area, and multiple PADs of the chip to be verified can be connected to the gold fingers respectively through bonding wires.

[0092] like Figure 6 As shown, the middle chip verification area includes a 5mm×5mm adhesive area 201 and a gold finger area 202 arranged around the adhesive area 201. Optionally, 12 gold fingers are arranged around the adhesive area 201, that is, 12 gold fingers are arranged inside the four sides of the gold finger area 202.

[0093] As shown Figure 7 in the figure, the area to be verified of the outer layer chip includes a die bonding area 201 with a size of 10mm×10mm, and a gold finger area 202 arranged around the die bonding area 201. Optionally, 24 gold fingers are respectively arranged around the die bonding area 201, that is, 24 gold fingers are respectively arranged inside the four sides of the gold finger area 202.

[0094] In a typical embodiment, as Figure 3 shown in the figure, 24 jacks are respectively arranged on the four peripheral edges of the PCB substrate 1, and the gold fingers in the gold finger area of the area to be verified of the outermost layer chip can be connected to the jacks one by one through the internal electrical connection lines in the PCB substrate 1. After verification, the layout of the areas to be verified of each layer of chips and the arrangement and connection methods of the gold fingers, jacks and internal electrical connection lines in the foregoing embodiments can not only ensure the insulation characteristics when the areas to be verified of each layer of chips are used, avoid the influence of the electromagnetic induction phenomenon on the chips to be verified, but also minimize the wire bonding time and the welding length to the greatest extent when welding chips to be verified with different sizes.

[0095] According to the above embodiments, as Figures 5 to 7 respectively shown are schematic diagrams of chips to be verified with different sizes installed on the verification substrate. As Figure 5 shown in the figure, in one embodiment, the chip to be verified with a size equal to or slightly smaller than 2mm×2mm is fixed inside the die bonding area 201 by, for example, insulating glue, and the PAD of the chip to be verified is connected (welded) to a suitable gold finger using a bonding wire. After welding, a soldering pin is carried out to perform the subsequent test board process.

[0096] For chips to be verified with a size equal to or slightly smaller than 5mm×5mm and 10mm×10mm, they are pasted and welded with bonding wires in a similar manner as described above. Refer to Figures 6 to 7 the figure. In addition, for multiple (for example, 2) PADs on the same side, they are welded to the relatively far gold fingers on the same side through bonding wires as much as possible to avoid interference between the bonding wires.

[0097] In one embodiment, as Figure 6 shown in the figure, 12 gold fingers are respectively arranged around the gold finger area, and the total number of gold fingers in the area to be verified of the middle layer chip 23 is 48. Therefore, the maximum number of PADs of the chip to be verified fixed in the area to be verified of the middle layer chip is 48, and can be connected to the gold fingers in the area to be verified of the middle layer chip 23 one by one. Specifically, as Figure 6As shown, a chip to be verified with 6 PADs is fixed in the die bonding area 201 according to the positions corresponding to the gold fingers. After the chip area to be verified is firmly fixed, 6 PADs of the chip to be verified are welded to the corresponding gold fingers using, for example, 30-μm silicon-aluminum wires. After the welding is completed, the chip to be verified needs to be soldered with pins for subsequent breadboarding test procedures.

[0098] In one embodiment, as Figure 7 shown, a chip to be verified with a size equal to or slightly smaller than 10 mm × 10 mm is fixed inside the die bonding area 201 using, for example, insulating glue. 24 gold fingers are arranged around the gold finger area 202 surrounding the die bonding area, and the total number of gold fingers in the chip area to be verified is 96. Therefore, the maximum number of PADs of the chip to be verified fixed in the outer chip area 22 to be verified as Figure 7 shown is 96. Specifically, as Figure 7 shown, a chip to be verified with 8 PADs is fixed in the die bonding area 201 according to the positions corresponding to the gold fingers. After being firmly fixed, 8 PADs of the chip to be verified are welded to the corresponding gold fingers using, for example, 30-μm silicon-aluminum wires. After the welding is completed, the chip to be verified needs to be soldered with pins for subsequent breadboarding test procedures.

[0099] In one embodiment of the present application, a chip verification device is provided, including:

[0100] a chip package verification substrate as described in the foregoing embodiment or its preferred or optional embodiments, and

[0101] a measuring device for measuring the chip to be verified.

[0102] The above is only the specific implementation manner of the embodiments of the present application, but the protection scope of the embodiments of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the embodiments of the present application, and all should be covered by the protection scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims

1. A chip package verification substrate, characterized in that, Comprising: A PCB substrate (1); A plurality of chip regions to be verified (2), the sizes of the plurality of chip regions to be verified (2) are different from each other, and they are nested on the surface of the PCB substrate (1); A plurality of jacks (4), which are arranged around the edge of the PCB substrate (1); Wherein, Each of the plurality of chip regions to be verified (2) includes a die bonding region (201), and a gold finger region (202) arranged around the die bonding region (201); The die bonding region (201) is used to fix the chip to be verified, and its shape and size are adapted to the chip to be verified; the gold finger region (202) includes a plurality of gold fingers (3), and the gold fingers (3) are used for electrical connection with the PADs of the chip to be verified; The plurality of gold fingers (3) in any one of the chip regions to be verified (2) are respectively electrically connected to the same number of the plurality of jacks (4).

2. The chip package verification substrate according to claim 1, wherein Among the nested plurality of chip regions to be verified (2), the gold fingers in the inner chip region to be verified are electrically connected to the jacks (4) via the gold fingers in one or more outer chip regions to be verified in sequence.

3. The chip package verification substrate according to claim 2, wherein The shapes of the plurality of chip regions to be verified (2) are adapted to the shapes of the chips to be verified, and their outer perimeters are rectangular; Wherein, the distances between the plurality of gold fingers on each side in each chip region to be verified (2) are equal, and they are aligned neatly in both the vertical and horizontal directions; Wherein, the internal electrical connection lines (5) between the gold fingers in the same direction or opposite directions are parallel to each other.

4. The chip package verification substrate according to claim 3, wherein The plurality of chip regions to be verified (2) include: An inner-layer chip region to be verified (21), including a rectangular die bonding region (201) and a gold finger region (202) surrounding the rectangular die bonding region; An outer-layer chip region to be verified (22) nested outside the inner-layer chip region to be verified (21), including a rectangular frame-shaped die bonding region and a gold finger region (202) surrounding the rectangular frame-shaped die bonding region; Wherein, the gold fingers in the inner-layer chip region to be verified (21) are electrically connected to the gold fingers in the outer-layer chip region to be verified (22) on the same side through internal electrical connection lines (5) in a butt-joint manner, and the gold fingers in the outer-layer chip region to be verified (22) are electrically connected to the jacks (4) on the same side in a one-to-one correspondence.

5. The chip package verification substrate according to claim 4, wherein The plurality of chip regions to be verified (2) further include: One or more middle-layer chip regions to be verified (23), including a rectangular frame-shaped die bonding region and a gold finger region (202) surrounding the rectangular frame-shaped die bonding region; The middle-layer chip regions to be verified (23) are nested between the inner-layer chip region to be verified (21) and the outer-layer chip region to be verified (22); The gold fingers on the same side in the inner-layer chip region to be verified (21), one or more middle-layer chip regions to be verified (23) and the outer-layer chip region to be verified (22) are electrically connected in sequence through internal electrical connection lines (5) in a butt-joint manner.

6. The chip package verification substrate according to claim 4 or 5, characterized in that The internal electrical connection lines (5) between the plurality of gold fingers in the outer-layer chip region to be verified (22) and the plurality of jacks are arranged in a radial manner and do not intersect with each other.

7. The chip package verification substrate according to any one of claims 3 to 5, characterized in that, In any two adjacent chip regions to be verified (2): All the gold fingers in the inner chip region to be verified are electrically connected in a one-to-one correspondence with the gold fingers in the outer chip region to be verified on the same side; Some of the gold fingers in the outer chip region to be verified are electrically connected in a one-to-one correspondence with the gold fingers in the inner chip region to be verified on the same side.

8. The chip package verification substrate according to any one of claims 1 to 5, wherein The die bonding area (201) is used to fix the chip to be verified through an insulating adhesive; The gold fingers are used to electrically connect the PADs of the chip to be verified through bonding wires (6).

9. The chip package verification substrate according to any one of claims 1 to 5, wherein The shapes and sizes of the gold fingers in the gold finger area are the same; The jacks (4) are used for soldering pin headers.

10. A chip verification device, characterized in that, Comprising: The chip package verification substrate according to any one of claims 1 to 9, and A measuring device for measuring the chip to be verified.

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