DRAM (Dynamic Random Access Memory) near memory packaging structure
Through the hybrid bonding and lead connection of DRAM near-memory packaging structure, the problems of high packaging costs and limited transmission broadband in the prior art are solved, and cost savings and performance improvements are achieved.
Patent Information
- Application Number
- CN202421950697.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-13
- Publication Date
- 2025-07-25
- Estimated Expiration
- 2034-08-13
AI Technical Summary
The existing DRAM packaging methods are costly, and through-silicon has an impact on the packaging structure design and stress, limiting the inter-chip transmission broadband.
It adopts a DRAM near-memory packaging structure, and by mixing bonding logic chips and memory chips, the logic chip does not require rewiring layers and through-silicon holes, and the memory chip is completely etched through. The logic chip connects the substrate through leads, supporting multi-layer logic chip stacking and memory chip expansion.
It reduces packaging costs, improves the reliability of logic chips and inter-chip transmission broadband, supports multi-layer logic chip stacking, expands memory chip capacity, and reduces production costs through lead-connected substrates.
Smart Images
Figure CN223157514U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of packaging structures, in particular to a DRAM near-memory packaging structure. Background Art
[0002] In the wafer-on-wafer stacking method, considering that the logic chip is connected with a high-speed interface, such as LPDDR, the industry adopts the DRAM / Logic F2B structure, where Logic F2B is the abbreviation of Logic Face to Back. The specific steps are as follows: (1) thinning the logic wafer and processing a redistribution layer on the logic wafer substrate; (2) processing through-silicon vias on the logic wafer, and the through-silicon vias connect the circuits on both sides of the logic wafer; (3) hybrid bonding the logic wafer and the memory wafer or two logic wafers, and at this time, the circuit surface of the logic wafer is exposed; (4) cutting the logic wafer into logic chips and flipping them onto the substrate.
[0003] The above packaging method has a high cost. The through-silicon vias in the prepared packaging structure will affect both the design and stress of the packaging structure, and will also limit the inter-chip transmission bandwidth.
[0004] It should be noted that the information disclosed in the above background art section is only used to strengthen the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Utility Model
[0005] Aiming at the above-mentioned shortcomings of the prior art, the purpose of the present utility model is to provide a DRAM near-memory packaging structure to solve the problems that the existing packaging method has a high cost, the through-silicon vias in the prepared packaging structure will affect both the design and stress of the packaging structure, and will also limit the inter-chip transmission bandwidth.
[0006] To achieve the above purpose, the technical solution of the present utility model is as follows:
[0007] A DRAM near-memory packaging structure;
[0008] It includes: a substrate; a wafer disposed on the substrate; leads respectively connecting the substrate and the wafer;
[0009] Wherein, an etching is formed on the wafer; one end of the lead is connected to the etched position on the wafer, and the other end of the lead is connected to the substrate;
[0010] The wafer includes a first chip and a second chip hybrid-bonded on the first chip;
[0011] Among them, the first chip is a logic chip or a memory chip; the second chip is different from the first chip and is hybrid-bonded on the first chip; wherein, when the first chip is a logic chip, the second chip is a memory chip; when the first chip is a memory chip, the second chip is a logic chip.
[0012] A further technical solution is that an etching is formed on the second chip to expose a metal pad; one end of the lead is connected to the metal pad on the second chip, and the other end of the lead is connected to the substrate.
[0013] A further technical solution is that when the first chip is a logic chip and the second chip is a memory chip; the second chip is etched through to expose the metal pad of the first chip; one end of the lead is connected to the metal pad on the first chip, and the other end of the lead is connected to the substrate.
[0014] A further technical solution is that when the first chip is a memory chip and the second chip is a logic chip; the wafer includes the first chip stacked on top of each other and the second chip hybrid-bonded on the first chip; the first chip stacked on top forms through-silicon vias, which are respectively connected to the second chip and the first chip stacked below.
[0015] A further technical solution is that the wafers are stacked on the substrate.
[0016] Compared with the prior art, the beneficial technical effects of the present utility model are as follows: (1) In the DRAM near-memory packaging structure, the logic chip does not need to have a redistribution layer and through-silicon vias, saving packaging costs; since the logic chip does not have the perforation of through-silicon vias, the reliability of the logic chip is relatively high, and the inter-chip transmission bandwidth is not limited.
[0017] (2) In the DRAM near-memory packaging structure, since the memory chip is completely etched through, the metal pad of the logic chip is connected to the substrate through a lead; when the IO interface needs to be modified, only the logic chip needs to be modified.
[0018] (3) In the DRAM near-memory packaging structure, the logic chip does not need to have a redistribution layer and through-silicon vias, saving packaging costs; at the same time, the logic chip is connected to the substrate through a lead, reducing production costs.
[0019] (4) When the logic chip performs calculations, it will generate a large amount of power consumption. When the logic chip is located above the memory chip, a heat dissipation structure can be installed on the DRAM near-memory packaging structure, and the heat dissipation structure can directly act on the logic chip, improving the heat dissipation efficiency of the logic chip.
[0020] (5) The DRAM near-memory packaging structure can support the stacking of multiple logic chips.
[0021] (6) The DRAM near-memory packaging structure expands the capacity of memory chips by stacking wafers on a substrate, and through-silicon vias are not required for the memory chips; meanwhile, the logic chips are connected to the substrate through leads, reducing production costs; in the fifth embodiment, the DRAM near-memory packaging structure realizes the stacking of memory chips by stacking wafers. Description of the Drawings
[0022] Figure 1 Shows a schematic structural diagram of the DRAM near-memory packaging structure in the background art.
[0023] Figure 2 Shows a schematic structural diagram of the DRAM near-memory packaging structure of the first embodiment of the present invention.
[0024] Figure 3 Shows a schematic structural diagram of the DRAM near-memory packaging structure of the second embodiment of the present invention.
[0025] Figure 4 Shows a schematic structural diagram of the DRAM near-memory packaging structure of the third embodiment of the present invention.
[0026] Figure 5 Shows a schematic structural diagram of the DRAM near-memory packaging structure of the fourth embodiment of the present invention.
[0027] Figure 6 Shows a schematic structural diagram of the DRAM near-memory packaging structure of the fifth embodiment of the present invention.
[0028] Reference numerals in the drawings: 1, substrate; 2, wafer; 21, first chip; 22, second chip; 3, lead. Detailed Embodiments
[0029] In order to make the objectives, technical solutions and advantages of the present invention clearer, the following further details the device proposed by the present invention in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and all use non-precise scales, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. In order to make the objectives, features and advantages of the present invention more obvious and understandable, please refer to the drawings. It should be noted that the structures, scales, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they do not have a technical essence. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the effects that the present invention can produce and the objectives that can be achieved, should still fall within the scope covered by the technical content disclosed by the present invention.
[0030] First Embodiment:
[0031] Figure 1 The structural schematic diagram of the DRAM near - memory package structure in the background art is shown. Figure 2 The structural schematic diagram of the DRAM near - memory package structure according to the first embodiment of the present utility model is shown. Combining Figure 1 - Figure 2 As shown, the present utility model discloses a DRAM near - memory package structure.
[0032] A DRAM near - memory package structure includes: a substrate 1, leads 3, and a wafer 2 disposed on the substrate 1.
[0033] Among them, the leads 3 are respectively connected to the substrate 1 and the wafer 2. Etching is formed on the wafer 2. One end of the lead 3 is connected to the etched position on the wafer 2, and the other end of the lead 3 is connected to the substrate 1.
[0034] The wafer 2 includes a first chip 21 and a second chip 22 hybrid - bonded on the first chip 21.
[0035] Through cleaning and activation treatment on the surfaces of the first chip 21 and the second chip 22 by hybrid bonding, by aligning and bonding the first chip 21 and the second chip 22 at room temperature, then performing a certain heat treatment to enhance the bonding strength of the bonding surface, and then through heat treatment, the metal contacts of the first chip 21 and the metal contacts of the second chip 22 are thermally expanded and diffusion - bonded.
[0036] The first chip 21 is a logic chip or a memory chip. The second chip 22 is different from the first chip 21 and is hybrid - bonded on the first chip 21. Among them, when the first chip 21 is a logic chip, the second chip 22 is a memory chip.
[0037] Etching is formed on the second chip 22, and the metal pads are exposed. One end of the lead 3 is connected to the metal pads on the second chip 22, and the other end of the lead 3 is connected to the substrate 1.
[0038] At this time, the logic chip is disposed on the substrate 1, and the memory chip is hybrid - bonded on the logic chip. The substrate of the memory chip is etched to expose the metal pads of the memory chip.
[0039] In the DRAM near - memory package structure, the logic chip does not need to make a redistribution layer and through - silicon vias, saving the packaging cost. Since there are no perforations of through - silicon vias in the logic chip, the reliability of the logic chip is relatively high, and the inter - chip transmission bandwidth is not restricted.
[0040] Second Embodiment:
[0041] Figure 3 The structural schematic diagram of the DRAM near - memory package structure according to the second embodiment of the present utility model is shown. Combining Figure 1 - Figure 3 As shown:
[0042] When the first chip 21 is a logic chip and the second chip 22 is a memory chip, the second chip 22 is etched through to expose the metal pads of the first chip 21. One end of the lead 3 is connected to the metal pads on the first chip 21, and the other end of the lead 3 is connected to the substrate 1.
[0043] The memory chip is completely etched through to expose the metal pads of the logic chip. At this time, the logic chip is connected to the substrate 1 through the lead 3, reducing the production cost.
[0044] When the IO interface needs to be modified in the DRAM near-memory packaging structure in the first embodiment, a joint design of the logic chip and the memory chip is required. The signals of the logic chip need to be mixed and bonded to the memory chip and then transmitted to the metal pads of the memory chip.
[0045] In the DRAM near-memory packaging structure in the second embodiment, since the memory chip is completely etched through, the metal pads of the logic chip are connected to the substrate 1 through the lead 3. When the IO interface needs to be modified, only the logic chip needs to be modified.
[0046] Third Embodiment:
[0047] Figure 4 Fig. shows a schematic structural diagram of the DRAM near-memory packaging structure according to the third embodiment of the present invention. Combining Figure 1 - Figure 4 as shown:
[0048] The first chip 21 is a logic chip or a memory chip. The second chip 22 is different from the first chip 21 and is hybrid-bonded on the first chip 21. Among them, when the first chip 21 is a memory chip, the second chip 22 is a logic chip.
[0049] At this time, the memory chip is disposed on the substrate 1, and the logic chip is hybrid-bonded on the memory chip. An etching is formed on the logic chip to expose the metal pads. One end of the lead 3 is connected to the metal pads on the logic chip, and the other end of the lead 3 is connected to the substrate 1.
[0050] In the DRAM near-memory packaging structure of the third embodiment, the logic chip does not need to have a redistribution layer and through-silicon vias, saving the packaging cost. At the same time, the logic chip is connected to the substrate 1 through the lead 3, reducing the production cost.
[0051] In the DRAM near-memory packaging structures of the first and second embodiments, the memory chip is thinned. Since the memory chip itself needs a certain thickness to implement the capacitor, the memory chip can only be thinned to 25 μm. In the DRAM near-memory packaging structure of the third embodiment, by thinning the substrate of the logic chip, it can be thinned to <10 μm, thereby reducing the thickness of the DRAM near-memory packaging structure.
[0052] When the logic chip performs calculations, it will generate relatively high power consumption. When the logic chip is located above the memory chip, a heat dissipation structure can be installed above the DRAM near-memory package structure, and the heat dissipation structure can directly act on the surface of the logic chip to improve the heat dissipation efficiency of the logic chip.
[0053] In the DRAM near-memory package structures of the first embodiment and the second embodiment, the memory chip is located above the logic chip. After the heat dissipation structure is installed on the DRAM near-memory package structure, the heat dissipation structure cannot directly act on the logic chip, reducing the heat dissipation efficiency of the logic chip.
[0054] Fourth Embodiment:
[0055] Figure 5 The structural schematic diagram of the DRAM near-memory package structure of the fourth embodiment of the present invention is shown. Combining Figure 1 - Figure 5 as shown:
[0056] When the first chip 21 is a memory chip and the second chip 22 is a logic chip. The wafer 2 includes a first chip 21 stacked on top of each other and a second chip 22 hybrid-bonded on the first chip 21.
[0057] Exemplarily, there are two groups of logic chips. The memory chips are stacked up and down. The logic chips are located above the memory chips. Etching is formed on the logic chips to expose the metal pads. One end of the lead 3 is connected to the metal pad on the logic chip, and the other end of the lead 3 is connected to the substrate 1. Through-silicon vias are formed in the up-down direction of the first chip 21 stacked above. The upper end of the through-silicon via is connected to the logic chip, and the lower end of the through-silicon via is connected to the memory chip stacked below.
[0058] The DRAM near-memory package structure in the fourth embodiment can support the stacking of multiple layers of logic chips.
[0059] Fifth Embodiment:
[0060] Figure 6 The structural schematic diagram of the DRAM near-memory package structure of the fifth embodiment of the present invention is shown. Combining Figure 1 - Figure 6 as shown:
[0061] The wafer 2 is stacked on the substrate 1.
[0062] Exemplarily, there are two groups of wafers 2. The wafers 2 are stacked up and down. The logic chips in the wafers 2 are located above the memory chips. Etching is formed on the logic chips to expose the metal pads. One end of the lead 3 is connected to the metal pad on the logic chip, and the other end of the lead 3 is connected to the substrate 1.
[0063] In the fifth embodiment, the DRAM near-memory packaging structure expands the capacity of the memory chips by stacking the wafer 2 on the substrate 1. Compared with the memory chips in the DRAM near-memory packaging structure of the fourth embodiment, through-silicon vias are not required. At the same time, the logic chip is connected to the substrate 1 through the lead 3, reducing the production cost. The DRAM near-memory packaging structure in the fifth embodiment realizes the stacking of memory chips by stacking the wafer 2.
[0064] Sixth embodiment:
[0065] A packaging method for a DRAM near-memory packaging structure includes the following steps:
[0066] Step 1: Hybrid bond the first chip 21 and the second chip 22 to form a wafer 2.
[0067] When the first chip 21 is a logic chip, the second chip 22 is a memory chip. In step 1, the hybrid bonding can be the wafer 2 in the first and second embodiments.
[0068] When the first chip 21 is a memory chip, the second chip 22 is a logic chip. In step 1, the hybrid bonding can be the wafer 2 in the third, fourth, and fifth embodiments.
[0069] Step 2: Thin the second chip 22.
[0070] When the second chip 22 is a memory chip, the second chip 22 can be thinned to 25 μm. When the second chip 22 is a logic chip, the second chip 22 can be thinned to <10 μm.
[0071] Step 3: Etch the wafer 2 to expose the metal pads.
[0072] In step 3, etch the first chip 21 to expose the metal pads.
[0073] When the second chip 22 is a memory chip, etch the memory chip to expose the metal pads of the memory chip.
[0074] When the second chip 22 is a logic chip, etch the logic chip to expose the metal pads of the logic chip.
[0075] Step 4: Connect one end of the lead 3 to the metal pad of the wafer 2. Connect the other end of the lead 3 to the substrate 1.
[0076] When the second chip 22 is a memory chip, connect one end of the lead 3 to the metal pad of the memory chip, and connect the other end of the lead 3 to the substrate 1.
[0077] When the second chip 22 is a logic chip, connect one end of the lead 3 to the metal pad of the logic chip, and connect the other end of the lead 3 to the substrate 1.
[0078] In step 3, the first chip 21 is etched through to expose the metal pads of the second chip 22.
[0079] When the second chip 22 is a memory chip, the memory chip is etched through to expose the metal pads of the logic chip.
[0080] Step 4: Connect one end of the lead 3 to the metal pad of the wafer 2. Connect the other end of the lead 3 to the substrate 1.
[0081] When the second chip 22 is a memory chip, one end of the lead 3 is connected to the metal pad of the logic chip, and the other end of the lead 3 is connected to the substrate 1.
[0082] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.
[0083] The above-described embodiments merely represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the utility model patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the utility model patent shall be subject to the appended claims.
Claims
1. A DRAM near-memory packaging structure, characterized in that Comprising: A substrate (1); A wafer (2), disposed on the substrate (1); Leads (3), respectively connecting the substrate (1) and the wafer (2); Wherein, an etching is formed on the wafer (2); one end of the lead (3) is connected to the etched position on the wafer (2), and the other end of the lead (3) is connected to the substrate (1); The wafer (2) includes a first chip (21) and a second chip (22) hybrid-bonded on the first chip (21); Wherein, the first chip (21) is a logic chip or a memory chip; the second chip (22) is different from the first chip (21) and is hybrid-bonded on the first chip (21); wherein, when the first chip (21) is a logic chip, the second chip (22) is a memory chip; when the first chip (21) is a memory chip, the second chip (22) is a logic chip.
2. The DRAM near-memory packaging structure according to claim 1, characterized in that: An etching is formed on the second chip (22) to expose metal pads; one end of the lead (3) is connected to the metal pads on the second chip (22), and the other end of the lead (3) is connected to the substrate (1).
3. The DRAM near-memory packaging structure according to claim 1, wherein: When the first chip (21) is a logic chip and the second chip (22) is a memory chip; the etching on the second chip (22) penetrates through and exposes the metal pads of the first chip (21); one end of the lead (3) is connected to the metal pads on the first chip (21), and the other end of the lead (3) is connected to the substrate (1).
4. The DRAM near-memory packaging structure according to claim 1, wherein: When the first chip (21) is a memory chip and the second chip (22) is a logic chip; the wafer (2) includes the first chip (21) and the second chip (22) hybrid-bonded on the first chip (21) stacked on top of each other; the first chip (21) stacked on top forms through-silicon vias respectively connecting the second chip (22) and the first chip (21) stacked below.
5. The DRAM near-memory packaging structure according to claim 1, wherein: The wafer (2) is stacked and disposed on the substrate (1).