Eye pattern testing device of semiconductor chip

Abstract

The utility model relates to the technical field of eye pattern testing, in particular to an eye pattern testing device of a semiconductor chip, which comprises a driving control module, one side of the driving control module is respectively connected with an upper computer and a power supply, and the outer side of the driving control module is provided with a signal quality analyzer. One side of the signal quality analyzer is provided with an oscilloscope, the outer side of the driving control module is also provided with a pressing jig, the driving control module also comprises a TX + port, a TX-port, an RX + port and an RX-port, and the signal quality analyzer comprises a DATA + port and a DATA-port. According to the scheme, the low-cost driving circuit and the mature oscilloscope are introduced, so that the eye pattern testing scheme of different types of chips based on the TO packaging structure, which is low in cost, short in development period and high in reliability, is realized, and the purpose of improving the production qualification rate of products is achieved.

Description

Technical Field

[0001] The utility model relates to the technical field of eye diagram testing, in particular to an eye diagram testing device for semiconductor chips. Background Art

[0002] With the expansion of modern ultra-large data information, optical communication requires higher and higher transmission rates to accelerate data processing. With the improvement of the data signal transmission rate, it is difficult to measure the transmission quality of data signals by traditional waveform parameter testing. As a new form of evaluating the transmission quality of data signals, the eye diagram has been widely used in the evaluation of data signals. In fact, the eye diagram is a statistical distribution diagram formed by naturally superimposing the data ratios at different positions of high-speed data signals according to the clock interval.

[0003] The result of eye diagram testing is an important basis for directly measuring the performance of chips. The currently used eye diagram testing device for semiconductor chips has a high cost and a long overall testing cycle, which will reduce the product production qualification rate. Therefore, an eye diagram testing device for semiconductor chips is proposed. Summary of the Invention

[0004] The purpose of the utility model is to solve the deficiencies in the prior art and propose an eye diagram testing device for semiconductor chips.

[0005] To achieve the above purpose, the utility model adopts the following technical solutions:

[0006] An eye diagram testing device for semiconductor chips includes a drive control module. One side of the drive control module is respectively connected to a host computer and a power supply. A signal quality analyzer is arranged outside the drive control module. An oscilloscope is installed on one side of the signal quality analyzer. A pressing fixture is also installed outside the drive control module. The drive control module also includes a TX+ port, a TX- port, an RX+ port, and an RX- port. The signal quality analyzer includes a DATA+ port and a DATA- port.

[0007] Preferably, the host computer is connected to the communication interface of the drive control module board through a USB cable, and a Power energy connection is formed between the power supply and the drive control module.

[0008] Preferably, the signal quality analyzer includes an integrated pulse pattern generator PPG module and an error code analyzer ED module with input sensitivity, and its wide range code rate is not less than 0.1 to 32.1 Gbit / s.

[0009] Preferably, the oscilloscope supports electrical interface and optical interface testing, supports external synchronous clock input, supports eye diagram signal integrity analysis, and the measurement bandwidth is not less than 12.5 Gbit / S.

[0010] Preferably, the TX+ port and TX- port of the drive control module are respectively connected to the DATA+ port and DATA- port of the signal quality analyzer. One end of the optical interfaces of the signal quality analyzer and the oscilloscope are connected. A Cable clock signal is set among the drive control module, the signal quality analyzer and the oscilloscope, and the three are connected by a radio frequency cable. The other end of the oscilloscope is connected to the device under test TOSA through an optical fiber Fiber. The device under test TOSA is connected to the drive control module through an FPC flexible circuit board. The press-fit fixture is also connected in the circuit between the drive control module and the device under test TOSA in the form of an FPC flexible circuit board.

[0011] Preferably, the RX- port of the drive control module is connected to the DATA- port of the signal quality analyzer. One end of the electrical interfaces of the signal quality analyzer and the oscilloscope are connected. The other end of the oscilloscope is connected to the RX+ port of the drive control module. A Cable clock signal is set among the drive control module, the signal quality analyzer and the oscilloscope, and the three are connected by a radio frequency cable. There is also a device under test ROSA arranged outside the drive control module, and the two are connected by an FPC flexible circuit board. The press-fit fixture is also connected in the circuit between the drive control module and the device under test TOSA in the form of an FPC flexible circuit board. One side of the device under test ROSA is connected to a standard light source through an optical fiber Fiber.

[0012] The beneficial effects of the present utility model are:

[0013] This solution realizes an eye diagram test solution for different types of chips based on the TO package structure with low cost, short development cycle, and high reliability by introducing a low-cost drive circuit and a mature oscilloscope, so as to achieve the purpose of improving the product production qualification rate. Description of the Drawings

[0014] Figure 1 It is a connection schematic diagram of the eye diagram test of the TOSA optical eye of an eye diagram test device for a semiconductor chip proposed by the present utility model;

[0015] Figure 2 It is a connection schematic diagram of the eye diagram test of the ROSA electrical eye of an eye diagram test device for a semiconductor chip proposed by the present utility model. Detailed Embodiments

[0016] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments.

[0017] Embodiment 1: Refer to Figure 1, An eye diagram test device for a semiconductor chip, including a drive control module. One side of the drive control module is respectively connected to a host computer and a power supply. A signal quality analyzer is arranged outside the drive control module. An oscilloscope is installed on one side of the signal quality analyzer. A pressing fixture is also installed outside the drive control module. The drive control module also includes a TX+ port, a TX- port, an RX+ port, and an RX- port. The TX port is understood as the signal to be tested of the TOSA, and the RX port is understood as the signal to be tested of the ROSA. The signal quality analyzer includes a DATA+ port and a DATA- port. The test device is applicable to the optical eye diagram test of the optical transmitter device TOSA and the electrical eye diagram test of the optical receiver device ROSA.

[0018] Specifically, the host computer is connected to the communication interface of the drive control module board through a USB cable to achieve the modulation and drive of the device under test. A Power energy connection is formed between the power supply and the drive control module, which is used for the power supply of the circuit.

[0019] Furthermore, the signal quality analyzer includes an integrated pulse pattern generator PPG module and an error code analyzer ED module with input sensitivity. Its wide range of code rates is not less than 0.1 to 32.1 Gbit / s, and it can support automatic setting of output timing.

[0020] And, the oscilloscope supports electrical interface and optical interface tests, supports external synchronous clock input, supports eye diagram signal integrity analysis, and the measurement bandwidth is not less than 12.5 Gbit / S.

[0021] In this embodiment, the TX+ port and TX- port of the drive control module are respectively connected to the DATA+ port and DATA- port of the signal quality analyzer. One end of the optical interface of the signal quality analyzer and the oscilloscope is connected. A synchronous Cable clock signal is set between the drive control module, the signal quality analyzer, and the oscilloscope. The three are connected by a radio frequency cable. The other end of the oscilloscope is connected to the device under test TOSA through an optical fiber Fiber. The optical fiber Fiber is an LC / FC optical fiber, which transmits optical signals. The device under test TOSA is packaged in a conventional TO form. The device under test TOSA is connected to the drive control module through an FPC flexible printed circuit board, so as to achieve the connection with the drive control module, achieving the effect of convenient operation. The pressing fixture is also connected in the circuit between the drive control module and the device under test TOSA in the form of an FPC flexible printed circuit board.

[0022] Working principle:

[0023] Optical eye diagram test of TOSA: The optical signal of TOSA is accessed from the device under test TOSA to the interface of the oscilloscope through an LC / FC optical fiber. The oscilloscope completes the reception of periodic signals and conducts an optical eye diagram test. Embodiment

[0024] Reference Figure 2 , based on Embodiment 1, the following technical solutions are further provided:

[0025] In this embodiment, the RX- port of the drive control module is connected to the DATA- port of the signal quality analyzer. One end of the electrical interface of the signal quality analyzer and the oscilloscope is connected, and the other end of the oscilloscope is connected to the RX+ port of the drive control module. Cable clock signals are provided between the drive control module and the signal quality analyzer, between the signal quality analyzer and the oscilloscope, and between the oscilloscope and the drive control module. The three are connected by RF cables. A device under test (DUT) ROSA is also provided outside the drive control module. The DUT ROSA is packaged in a conventional TO form, and the two are connected by an FPC flexible printed circuit board. The pressing fixture is also connected in the circuit between the drive control module and the DUT ROSA by an FPC flexible printed circuit board. One side of the optical fiber Fiber of the DUT ROSA is connected to a standard light source, and Data is the information to be tested.

[0026] Working principle:

[0027] ROSA eye diagram test: A standard optical signal source is used to provide the light source required for the ROSA eye diagram test. It is introduced into the DUT ROSA through an LC optical fiber. The electrical signal generated by the DUT ROSA is connected to the electrical interface of the oscilloscope through the RX- port of the drive control module, so as to complete the reception of periodic signals and perform the eye diagram test.

[0028] The content not described in detail in this specification belongs to the prior art well-known to those skilled in the art.

[0029] The standard parts used in the present invention can all be purchased from the market. The special-shaped parts can be customized according to the description in the specification and the drawings. The specific connection methods of each part all adopt conventional means such as bolts, rivets, and welding that are mature in the prior art. The machines, parts, and equipment all adopt conventional models in the prior art, and the circuit connection adopts the conventional connection method in the prior art, which will not be elaborated here.

[0030] The above is only the preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention, according to the technical solution and the inventive concept of the present invention, makes equivalent substitutions or changes, and should be covered by the protection scope of the present invention.

Claims

1. An eye diagram test device for a semiconductor chip, characterized in that, Including: A drive control module, one side of the drive control module is respectively connected to a host computer and a power supply. A signal quality analyzer is arranged outside the drive control module. An oscilloscope is installed on one side of the signal quality analyzer. A press-fitting fixture is also installed outside the drive control module. The drive control module also includes a TX+ port, a TX- port, an RX+ port, and an RX- port. The signal quality analyzer includes a DATA+ port and a DATA- port.

2. The eye diagram testing device for a semiconductor chip according to claim 1, wherein The host computer is connected to the communication interface of the drive control module board through a USB cable, and a Power energy connection is formed between the power supply and the drive control module.

3. The eye diagram test device for a semiconductor chip according to claim 1, characterized in that The signal quality analyzer includes an integrated pulse pattern generator PPG module and an error code analyzer ED module with input sensitivity, and has a wide range of bit rates from not less than 0.1 to 32.1 Gbit / s.

4. The eye diagram test device for a semiconductor chip according to claim 1, characterized in that The oscilloscope supports electrical interface and optical interface tests, supports external synchronous clock input, supports eye diagram signal integrity analysis, and the measurement bandwidth is not less than 12.5 Gbit / S.

5. The eye diagram testing device for a semiconductor chip according to claim 1, characterized in that The TX+ port and the TX- port of the drive control module are respectively connected to the DATA+ port and the DATA- port of the signal quality analyzer. One end of the optical interface of the signal quality analyzer and the oscilloscope are connected. A Cable clock signal is set between the drive control module, the signal quality analyzer, and the oscilloscope, and the three are connected by a radio frequency cable. The other end of the oscilloscope is connected to the device under test TOSA through an optical fiber Fiber. The device under test TOSA is connected to the drive control module through an FPC flexible printed circuit board. The press-fitting fixture is also connected in the circuit between the drive control module and the device under test TOSA through an FPC flexible printed circuit board.

6. The eye diagram testing device for a semiconductor chip according to claim 1, wherein The RX- port of the drive control module is connected to the DATA- port of the signal quality analyzer. One end of the electrical interface of the signal quality analyzer and the oscilloscope are connected. The other end of the oscilloscope is connected to the RX+ port of the drive control module. A Cable clock signal is set between the drive control module, the signal quality analyzer, and the oscilloscope, and the three are connected by a radio frequency cable. A device under test ROSA is also arranged outside the drive control module, and the two are connected by an FPC flexible printed circuit board. The press-fitting fixture is also connected in the circuit between the drive control module and the device under test TOSA through an FPC flexible printed circuit board. One side of the device under test ROSA is connected to a standard light source through an optical fiber Fiber.

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