JTAG link self-diagnosis interface structure
By designing the 10PIN JTAG link self-diagnosis interface and integrating self-diagnosis function and locking mechanism, the complex diagnosis and connection instability of the existing JTAG interface are solved, and efficient fault location and stable connection are achieved.
Patent Information
- Application Number
- CN202422292062.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-20
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-09-20
AI Technical Summary
The existing JTAG interface lacks self-diagnosis function, resulting in complex link diagnosis and long maintenance time, unstable connections and easy to fall off, affecting testing efficiency.
A 10PIN JTAG link self-diagnosis interface is designed, which integrates self-diagnosis function, realizes step-by-step link diagnosis through control switches, and uses a flat cable interface and locking mechanism to ensure stable connection.
It realizes efficient self-diagnosis of JTAG links, quickly locates fault points, and prevents connections from falling off through locking mechanisms, improving testing efficiency and stability.
Smart Images
Figure CN223166913U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to electronic test equipment, and more particularly to an interface structure for self-diagnosis of JTAG links. Background Art
[0002] JTAG is the abbreviation of Joint Test Action Group, and is the common name of IEEE standard 1149.1 named Standard Test Access Port and Boundary Scan Architecture.
[0003] In the prior art, most JTAG interfaces adopt a 5-wire or 6-wire design, lacking sufficient self-diagnosis functions and stability guarantee measures. The JTAG interface is a special interface where 4 or 5 JTAG signals are connected to a chip, and the JTAG pins are connected together in a daisy chain manner, and an integrated circuit only needs to be connected to one "JTAG port" to access all integrated circuits on a printed circuit board. As an internationally widely used standard test protocol, the JTAG interface is mainly used for internal testing and debugging of various chips. However, in actual applications, the connection of the JTAG link may cause the entire JTAG link to fail to work due to the disconnection of the JTAG signal of one of the chips, resulting in a complex diagnostic process of the link, a long maintenance time, and low diagnostic test efficiency.
[0004] In the prior art, the standard pins of the JTAG interface are as follows:
[0005] 1. TDI (Test Data Input);
[0006] 2. TDO (Test Data Output);
[0007] 3. TCK (Test Clock);
[0008] 4. TMS (Test Mode Select);
[0009] 5. TRST (Test Reset) is optional;
[0010] 6. GND Signal reference ground wire.
[0011] As Figure 1 shown, Figure 1It is a schematic diagram of the connection of the JTAG interface on a traditional circuit board. In the following description, the JTAG interface uses a 5-wire method and does not use the TRST signal. If any one of the TDO to TDI signals between the ICs in the JTAG link fails, the signal is interrupted, or there is a problem with the IC itself (the downward arrow indicates the position), it will cause the JTAG link to be interrupted, and the JTAG master controller cannot communicate with the downstream ICs. When communication fails, the specific fault point cannot be located. Only the link can be disconnected, and all JTAG wiring and ICs are checked. First, connect IC1 to the master controller, connect the TDO of IC1 to the TDI of the master controller, and test IC1. If IC1 can work, then disconnect the TDO of IC1 to the TDI of the JTAG controller, connect the TDI and TDO of IC2 in series in the link, and test whether IC1 and IC2 can work. Debug step by step like this until the last IC is connected in series to the JTAG link, so as to complete the link detection work. It takes a relatively long time to do the detection work, and the efficiency is low.
[0012] There is another problem with the traditional JTAG connection method: the JTAG hardware connection uses a plug-and-play connector without a locking mechanism, and it is easy to drop the connector plug during vibration, resulting in signal connection interruption, which is also one of the reasons why the link is prone to problems.
[0013] In view of this, the JTAG interface structure and its corresponding circuit in the prior art need to be improved. Summary of the Utility Model
[0014] Aiming at the deficiencies in the prior art, the technical problem to be solved by the present utility model is to provide an interface structure for self-diagnosis of the JTAG link. The purpose of designing this interface structure is to ensure the stable connection and efficient testing of the JTAG link.
[0015] To solve the above technical problems, the present utility model is realized through the following solutions: An interface structure for self-diagnosis of the JTAG link of the present utility model, the interface structure includes a JTAG interface and an interface circuit connected to the JTAG interface. The JTAG interface is provided with a first TDO pin for testing data output, a first TCK pin for testing the clock, a first TMS pin for testing mode selection, and a GND pin for the signal reference ground wire. The JTAG interface further includes a TDI_IN pin for switching the strobe signal, and 3 spare signal pins;
[0016] The interface circuit includes multiple IC chips, and a control switch K is arranged one-to-one in the link of each IC chip;
[0017] The IC chip has a TDI pin, a second TDO pin, a second TMS pin, a second TCK pin, and a TDO_EN pin. The first TDO pin is connected to the TDI pin of the first IC chip. The first TCK pin is connected to the second TCK pins of each IC chip. The first TMS pin is connected to the second TMS pins of each IC chip.
[0018] Each control switch K is a change-over switch. The control switch K has an A pin, a B pin, and a C pin. One end of the change-over pin of the control switch K is connected to the A pin, and its outer end can be switched between the B pin and the C pin. The C pins of each control switch K are interconnected and connected to the TDI_IN pin.
[0019] In the circuits of two adjacent IC chips: the A pin is connected to the second TDO pin of one of the IC chips, and the B pin is connected to the TDI pin of the other IC chip.
[0020] In the last control switch K, the A pin is connected to the second TDO pin of the last IC chip, and the B pin and the C pin in the last control switch K are interconnected.
[0021] Each control switch K is provided with an enable signal e port and a control signal k port. In any IC chip and the control switch K corresponding to this IC chip, the TDO_EN pin is connected to the control signal k port.
[0022] In the first control switch K corresponding to the first IC chip, the enable signal e port of this first control switch K is connected to the enable signal output pin of the JTAG interface.
[0023] Except for the first control switch K, the enable signal e ports of the remaining control switches K are respectively connected to the TDO_EN pins of the adjacent upper group of IC chips.
[0024] Further, among the three spare signal pins, one of the spare signal pins is a TRST pin for test reset.
[0025] Further, the JTAG interface is a flat ribbon cable interface.
[0026] Further, the JTAG interface further includes a locking mechanism.
[0027] Furthermore, the locking mechanism includes barbs provided on both sides of the male end, guiding grooves provided on both sides of the female end, and a convex buckle is provided in the guiding groove. After the male end and the female end are butted, the barbs can be buckled into the convex buckle.
[0028] Compared with the prior art, the beneficial effects of the present utility model are:
[0029] 1. The interface of the JTAG link self-diagnosis of the present utility model improves the existing JTAG interface, upgrades from 5PIN to 10PIN, integrates the self-diagnosis function, and ensures the efficient testing of the JTAG link.
[0030] 2. In the JTAG link of the present utility model, a switching switch is provided for each IC chip one-to-one. The corresponding electronic switch is controlled by the JTAG instruction to realize the control of the JTAG signal, realize the self-diagnosis function of the link, and can complete the step-by-step diagnosis of the JTAG daisy chain, and immediately report the fault point when a problem occurs.
[0031] 3. The JTAG interface of the present utility model is provided with a locking mechanism. The locking mechanism forms an anti-disconnection mechanism between the male end and the female end to ensure the stability of the JTAG link. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 It is a schematic diagram of the connection of the JTAG interface on a traditional circuit board.
[0033] Figure 2 It is a schematic diagram of the structure of the control switch K of the present utility model.
[0034] Figure 3 It is a schematic diagram of the operation of the JTAG link of 3 chips in Embodiment 2 of the present utility model.
[0035] Figure 4 It is a schematic diagram of the operation of the JTAG link of 3 chips in Embodiment 2 of the present utility model.
[0036] Figure 5 It is a schematic diagram of the operation of the JTAG link of 3 chips in Embodiment 2 of the present utility model.
[0037] Figure 6 It is a schematic diagram of the structure of the male end in the JTAG interface of the present utility model.
[0038] Figure 7 It is a schematic diagram of the structure of the female end in the JTAG interface of the present utility model.
[0039] Reference numerals in the drawings: barb 101, convex buckle 102. DETAILED DESCRIPTION OF THE INVENTION
[0040] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention. Obviously, the described embodiments of the present invention are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.
[0041] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.
[0042] Embodiment 1: The specific structure of the present invention is as follows:
[0043] Please refer to the attached Figure 2-7 , an interface structure for self-diagnosis of a JTAG link of the present invention, the interface structure includes a JTAG interface and an interface circuit connected to the JTAG interface. The JTAG interface is provided with a first TDO pin for testing data output, a first TCK pin for testing the clock, a first TMS pin for testing mode selection, and a GND pin for the signal reference ground wire. The JTAG interface further includes a TDI_IN pin for switching the strobe signal, and three spare signal pins; among the three spare signal pins, one of the spare signal pins is a TRST pin for testing reset, and the second spare signal pin is an enable signal output pin.
[0044] The interface circuit includes a plurality of IC chips, and a control switch K is provided one-to-one in the link of each IC chip. As Figure 2 shown, the present invention adds a control switch K to the original circuit. The control switch K is used to control the TDO output of each IC chip. Each control switch has an enable signal e port and a control signal k port. When the enable signal e port is at a high level, the control switch K does not work, and the A, B, and C pins are not connected. When the enable signal e port is at a low level, the control switch K starts to work. The state of the control switch depends on the level of the control signal k port. When the control signal k port is at a high level, the A and B pins are closed. When the control signal k port is at a low level, the A and C pins are closed.
[0045] The IC chip has a TDI pin, a second TDO pin, a second TMS pin, a second TCK pin, and a TDO_EN pin. The first TDO pin is connected to the TDI pin of the first IC chip. The first TCK pin is connected to the second TCK pins of each IC chip. The first TMS pin is connected to the second TMS pins of each IC chip.
[0046] Each control switch K is a toggle switch. The control switch K has an A pin, a B pin, and a C pin. One end of the switching pin of the control switch K is connected to the A pin, and its outer end can be switched between the B pin and the C pin. The C pins of each control switch K are interconnected and connected to the TDI_IN pin.
[0047] In the circuits of two adjacent IC chips: the A pin is connected to the second TDO pin of one of the IC chips, and the B pin is connected to the TDI pin of the other IC chip.
[0048] The A pin of the terminal control switch K is connected to the second TDO pin of the terminal IC chip, and the B pin and the C pin of the terminal control switch K are interconnected.
[0049] In any IC chip and the corresponding control switch K, the TDO_EN pin is connected to the control signal k port.
[0050] In the first control switch K corresponding to the first IC chip, the enable signal e port of this first control switch K is connected to the enable signal output pin of the JTAG interface.
[0051] Except for the first control switch K, the enable signal e ports of the remaining control switches K are respectively connected to the TDO_EN pins of the adjacent upper group of IC chips, as Figure 3 shown.
[0052] As Figure 3 shown, Figure 3 This is a schematic diagram of the JTAG link operation of three chips in Embodiment 2 of the present invention. Figure 3 An example of the JTAG link connection of three chips is given. The following describes how the system implements the JTAG self-diagnosis function. Figure 3 In [the example], the enable signal e port of switch K1 is at a low level, the level of the control signal k port is at a high level, the state of K1 is that the A pin and the C pin are in a closed state, and K2 and K3 are in a non-operating state. At this time, for the IC1 accessed by the JTAG link, the IC1 can be controlled to be tested through JTAG instructions, and the first-level JTAG link can be diagnosed whether it is working according to the test results.
[0053] Figure 4This is the second schematic diagram of the JTAG link operation for the three-chip in Embodiment 2 of the present utility model. After IC1 passes the test, a control instruction can be given to IC1 to make the signal output of its TDO_EN pin low, and send it to the control signal k port of K1 and the control signal e port of K2, so that AB of K1 is closed and AC of K2 is closed. At this time, IC1 and IC2 can be controlled through JTAG instructions, and whether the second-level link works can be diagnosed through the test results.
[0054] Figure 5 This is the third schematic diagram of the JTAG link operation for the three-chip in Embodiment 2 of the present utility model. After the second-level link passes the test, a control instruction can be given to IC2 to make the signal output of the TDO_EN pin low, and send it to the control signal k port of K2 and the control signal e port of K3, so that AB of K2 is closed and AC of K3 is closed. At this time, IC1, IC2, and IC3 can be controlled through JTAG instructions, and whether the third-level link works can be diagnosed through the test results.
[0055] If more IC chips need to be connected, the circuit connection structure of the present utility model can be used to connect more IC chips in series to the JTAG link, and the function of diagnosing each level of the link can be realized.
[0056] As Figure 6-7 shown, the JTAG interface is a flat ribbon cable interface. The JTAG interface also includes a locking mechanism. The locking mechanism includes barbs 101 provided on both sides of the male end, guiding grooves provided on both sides of the female end, and a convex buckle 102 is provided in the guiding groove. After the male end and the female end are docked, the barb 101 can be buckled into the convex buckle 102. The self-diagnostic interface structure of the JTAG link of the present utility model is to solve the problem of unreliable connection caused by vibration when multiple card connections are made. At the same time, an electrical interface for JTAG interconnection is also designed. The interface adopts a flat ribbon cable method, and the flat ribbon cable is then connected to a plastic connector. The plastic connector has a hook, which can hook the socket after being inserted into the socket on the PCB board and will not fall off when encountering vibration, and the connection is reliable.
[0057] The electrical interface uses a 2.0-pitch connector. The wire uses an 8-pin or 10-pin ribbon cable or a multi-core shielded wire. The plastic connector has a hook, which can hook the socket after being inserted into the socket on the PCB board and will not fall off when encountering vibration, and the connection is reliable.
[0058] In summary, through the above circuit structure, the JTAG interface of the present utility model can realize the function of gradually self-diagnosing the JTAG link through JTAG instructions, quickly find the fault point. And the problem of electrical connection reliability is solved through an innovative electrical connection method.
[0059] The above are only the preferred embodiments of the present utility model, and do not thereby limit the patent scope of the present utility model. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present utility model, or directly or indirectly applied in other related technical fields, shall similarly be included within the patent protection scope of the present utility model.
Claims
1. An interface structure for JTAG link self-diagnosis, the interface structure includes a JTAG interface and an interface circuit connected to the JTAG interface. The JTAG interface is provided with a first TDO pin for test data output, a first TCK pin for test clock, a first TMS pin for test mode selection, and a GND pin for signal reference ground wire, characterized in that, The JTAG interface further includes a TDI_IN pin for switching the strobe signal, and three spare signal pins; The interface circuit includes a plurality of IC chips, and control switches K are arranged one-to-one in the links of each IC chip; The IC chip has a TDI pin, a second TDO pin, a second TMS pin, a second TCK pin, and a TDO_EN pin. The first TDO pin is connected to the TDI pin of the first IC chip. The first TCK pin is connected to the second TCK pins of each IC chip. The first TMS pin is connected to the second TMS pins of each IC chip; Each control switch K is a change-over switch. The control switch K has a pin A, a pin B, and a pin C. One end of the switching pin of the control switch K is connected to the pin A, and its outer end can be switched between the pin B and the pin C. The pins C of each control switch K are interconnected and connected to the TDI_IN pin; In the circuits of two adjacent IC chips: the pin A is connected to the second TDO pin of one of the IC chips, and the pin B is connected to the TDI pin of the other IC chip; In the end control switch K, the pin A is connected to the second TDO pin of the end IC chip, and the pin B and the pin C in the end control switch K are interconnected; Each control switch K is provided with an enable signal e port and a control signal k port. In any IC chip and the control switch K corresponding to this IC chip, the TDO_EN pin and the control signal k port are connected; In the first control switch K corresponding to the first IC chip, the enable signal e port of this first control switch K is connected to the enable signal output pin of the JTAG interface; Except for the first control switch K, the enable signal e ports of the remaining control switches K are respectively connected to the TDO_EN pins of the adjacent upper group of IC chips.
2. The interface structure for self-diagnosis of JTAG link according to claim 1, characterized in that Among the three spare signal pins, one of the spare signal pins is a TRST pin for test reset.
3. The interface structure for self-diagnosis of a JTAG link according to claim 1, characterized in that, The JTAG interface is a flat flexible cable interface.
4. The interface structure for self-diagnosis of a JTAG link according to claim 1, characterized in that, The JTAG interface further includes a locking mechanism.
5. An interface structure for self-diagnosis of a JTAG link according to claim 4, characterized in that, The locking mechanism includes barbs (101) provided on both sides of the male end, guiding grooves provided on both sides of the female end, and a protruding buckle (102) is provided in the guiding groove. After the male end and the female end are docked, the barbs (101) can be buckled into the protruding buckle (102).