Interface circuit and electronic equipment

Abstract

The utility model provides an interface circuit and electronic equipment, the interface circuit comprises a concentrator, a first universal serial bus C-type interface and a change-over switch, and the change-over switch is connected with two first configuration channel pins of the first universal serial bus C-type interface. And the control module is used for controlling the downlink interface and the uplink interface in the change-over switch corresponding to the group of first high-speed signal pins in the working state to be connected when one group of the two groups of first high-speed signal pins is determined to be in the working state according to the pin voltages of the two first configuration channel pins. According to the interface circuit provided by the embodiment of the invention, the first universal serial bus type C can be connected with one downlink interface of the concentrator through the change-over switch, so that a multiplexer can be prevented from being connected with the first universal serial bus type C, and the hardware cost of the interface circuit can be reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and more particularly, to an interface circuit and an electronic device. Background Art

[0002] A hub is provided in the interface circuit of a Universal Serial Bus (USB) interface. Each downstream interface of the hub can be connected to a USB interface, so as to achieve unified management of multiple USB interfaces.

[0003] In order to support reversible plugging and unplugging, generally two groups of high-speed signal pins are provided in a Universal Serial Bus Type-C interface. In order to manage the Universal Serial Bus Type-C interface, a multiplexer (MUX) is usually provided in the interface circuit. Two downstream interfaces of the multiplexer are respectively connected to the two groups of high-speed signal pins of the Universal Serial Bus Type-C interface, and the upstream interface of the multiplexer is connected to a downstream interface of the hub. Through the multiplexer, a group of high-speed signal pins in the working state can be determined from the two groups of high-speed signal pins, and the group of high-speed signal pins in the working state is connected to the hub. The problem with this method is that the cost of the multiplexer is relatively high, resulting in a relatively high hardware cost of the interface circuit. Summary of the Utility Model

[0004] This application provides an interface circuit and an electronic device, and the interface circuit can reduce the hardware cost of the interface circuit.

[0005] In a first aspect, an interface circuit is provided. The interface circuit includes: a hub, a first Universal Serial Bus Type-C interface, and a switching switch; the first Universal Serial Bus Type-C interface has two groups of first high-speed signal pins and two first configuration channel pins, and the two groups of first high-speed signal pins correspond to the two first configuration channel pins one by one; the switching switch has two downstream interfaces and one upstream interface, the two downstream interfaces are respectively connected to the two groups of first high-speed signal pins, and the one upstream interface is connected to the first downstream interface of the hub; the switching switch is connected to the two first configuration channel pins, and is configured to control the connection between the downstream interface and the upstream interface in the switching switch corresponding to a group of the first high-speed signal pins in the working state when determining that a group of the first high-speed signal pins is in the working state according to the pin voltages of the two first configuration channel pins.

[0006] In the embodiment of the present application, a hub, a first Universal Serial Bus Type-C interface, and a switching switch are provided in the interface circuit. The switching switch is connected to two groups of first high-speed signal pins of the first Universal Serial Bus Type-C, and is also connected to a downstream interface of the hub. During the operation of the interface circuit, the switching switch can connect a group of first high-speed signal pins in the working state to the hub, so that the two groups of first high-speed signal pins can share a downstream interface of the hub. In this way, the first Universal Serial Bus Type-C can be connected to only one downstream interface of the hub, so that the hub can be connected to more USB interfaces. At the same time, the use of a multiplexer to connect the first Universal Serial Bus Type-C can be avoided, thereby reducing the hardware cost of the interface circuit.

[0007] Optionally, the interface circuit further includes a delay switch; the first Universal Serial Bus Type-C interface has two power pins, and the two power pins correspond to the two groups of first high-speed signal pins one by one; the control end of the delay switch is connected to the two first configuration channel pins, the delay switch is respectively connected to the two power pins, and is also connected to the power supply end in the interface circuit; the delay switch is used to delay the connection of a power pin corresponding to a group of first high-speed signal pins in the working state and the power supply end when it is determined according to the pin voltages of the two first configuration channel pins that one of the groups of first high-speed signal pins is in the working state.

[0008] In the embodiment of the present application, the delay switch can control the interface circuit to supply power to the slave device through the corresponding power pin after a certain delay after one of the groups of first high-speed signal pins is connected to the high-speed signal pins in the slave device, which can ensure that the Type-C interface of the slave device and the first Universal Serial Bus Type-C interface start to work only after the switching switch connects the first high-speed signal pins in the working state to the hub.

[0009] Optionally, the power pin is connected to the delay switch through a current-limiting branch, or the power supply end is connected to the delay switch through a current-limiting branch.

[0010] In the embodiment of the present application, a current-limiting branch is provided in the interface circuit. The current-limiting branch can limit the current input from the power supply end in the interface circuit to the power pin, so that over-current protection can be provided for the slave device connected to the first Universal Serial Bus Type-C interface.

[0011] Optionally, the interface circuit further includes two pull-up resistors, and the two pull-up resistors correspond to the two first configuration channel pins one by one; one end of each pull-up resistor is connected to the corresponding first configuration channel pin, and the other end is connected to the power supply end in the interface circuit.

[0012] Optionally, the interface circuit further includes: a second Type-C Universal Serial Bus (USB-C) interface; the second Type-C USB interface has two groups of second high-speed signal pins, one group of the second high-speed signal pins is connected to the second downstream interface of the hub, and the other group of the second high-speed signal pins is connected to the third downstream interface of the hub.

[0013] In an embodiment of the present application, the interface circuit includes a second Type-C USB interface, and the second Type-C USB interface has two groups of second high-speed signal pins. One group of the second high-speed signal pins is connected to the second downstream interface of the hub, and the other group of the second high-speed signal pins is connected to the third downstream interface of the hub. In this way, it is not necessary to set a corresponding multiplexer for the second Type-C USB interface in the interface circuit, thereby reducing the hardware cost of the interface circuit.

[0014] Optionally, the interface circuit further includes an interlock switch. The second Type-C USB interface further has two second configuration channel pins, and the two second configuration channel pins correspond to the two groups of second high-speed signal pins one by one; the interlock switch has two downstream interfaces and two upstream interfaces. The two downstream interfaces are respectively connected to the two groups of second high-speed signal pins, and the two upstream interfaces are respectively connected to the second downstream interface and the third downstream interface; the interlock switch is connected to the two second configuration channel pins, and is configured to control the connection between the upstream interface and the downstream interface of the interlock switch corresponding to the group of second high-speed signal pins in the working state and control the disconnection between the upstream interface and the downstream interface of the interlock switch corresponding to the other group of second high-speed signal pins when determining that one group of the second high-speed signal pins is in the working state according to the pin voltages of the two second configuration channel pins.

[0015] In this embodiment, the interlock switch can implement the interlock of the two groups of second high-speed signal pins, so that when a slave device is inserted, the interface circuit can only control one of the two groups of second high-speed signal pins to be connected to the hub, thereby avoiding interference of the other group of first high-speed signals on the group of high-speed signal pins in the working state.

[0016] Optionally, the interface circuit further includes two current-limiting branches; the second Type-C USB interface further has two power pins, and the two power pins correspond to the two groups of second high-speed signal pins one by one. The two power pins are respectively connected to the power supply terminal in the interface circuit through one of the current-limiting branches.

[0017] In an embodiment of the present application, current-limiting branches are provided in the interface circuit to limit the current input from the power supply terminal in the interface circuit to the power pins through the current-limiting branches, so as to provide over-current protection for the slave device connected to the second Type-C USB interface.

[0018] Optionally, the second Type-C interface further has one or two groups of low-speed signal pins, and each group of the low-speed signal pins is connected to a fourth downstream interface of the hub.

[0019] In the embodiment of the present application, the second Type-C interface has one or two groups of low-speed signal pins, and each group of low-speed signal pins is connected to a first downstream interface of the hub, so that the interface circuit can support slave devices communicating through the low-speed signal pins.

[0020] Optionally, the interface circuit further includes a Type-A interface, and the Type-A interface is connected to a fifth downstream interface of the hub.

[0021] In the embodiment of the present application, the interface circuit includes one or more Type-A interfaces, so that the interface circuit can uniformly manage the multiple Type-A interfaces, and thus the master device can be connected to one or more devices with Type-A interfaces.

[0022] In a second aspect, there is provided an electronic device, including: a universal serial bus controller, and the interface circuit as described in the first aspect, wherein the upstream interface of the hub is connected to the universal serial bus controller. Description of the Drawings

[0023] Figure 1 is a schematic diagram of the principle of an interface circuit in the related art;

[0024] Figure 2 is a schematic diagram of the pins of a socket in a Type-C interface in the related art;

[0025] Figure 3 is a schematic diagram of the pins of a plug in a Type-C interface in the related art;

[0026] Figure 4 is a schematic diagram of the principle of an interface circuit provided by an embodiment of the present application;

[0027] Figure 5 is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application;

[0028] Figure 6 is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application;

[0029] Figure 7 is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application;

[0030] Figure 8 is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application;

[0031] Figure 9 It is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application. Specific embodiments

[0032] Hereinafter, the technical solutions in the present application will be clearly and elaborately described in conjunction with the accompanying drawings. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means "or". For example, A / B may mean A or B. The "and / or" in the text is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B may mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of the present application, "a plurality of" means two or more than two.

[0033] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as implying or suggesting relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features.

[0034] See Figure 1 , Figure 1 is a schematic diagram of the principle of an interface circuit in the related art. As Figure 1 shown, the interface circuit 10 includes a hub (HUB) and a plurality of USB interfaces. The plurality of USB interfaces include one or more universal serial bus type C interfaces (hereinafter referred to as Type-C interfaces) and one or more universal serial bus type A interfaces (hereinafter referred to as Type-A interfaces). Each USB interface corresponds to a downstream interface of the hub, and the upstream interface of the hub is connected to the host device. When a certain USB interface (which can be a Type-A interface or a Type-C interface) in the interface circuit is connected to the USB interface of a slave device, the hub can connect the slave device to the host device.

[0035] Among them, the host device is, for example, an electronic device such as a computer, a notebook, and a server, and the slave device is, for example, a USB flash drive, a mobile phone, and a tablet. The interface circuit can be an integrated circuit module in the host device or an independent circuit module provided outside the host device.

[0036] As Figure 1As shown in the figure, the Type-C interface corresponds to a downstream interface of the hub. In order to connect a group of high-speed signal pins in the working state in the Type-C interface to the hub, a multiplexer corresponding to the Type-C interface is provided in the interface circuit. The multiplexer has two downstream interfaces. One downstream interface is connected to a group of high-speed signal pins (i.e., RX1 / TX1 pins) in the Type-C interface, and the other downstream interface is connected to another group of high-speed signal pins (i.e., RX2 / TX2 pins) in the Type-C interface. The upstream interface of the multiplexer is connected to a downstream interface of the hub.

[0037] The Type-C interface includes a socket and a plug. The socket is also called a USB female head, and the plug is also called a USB male head. The Type-C interface in the interface circuit can be a socket. When the Type-C interface (plug) of the slave device is inserted into the Type-C interface in the interface circuit, the multiplexer can determine whether the Type-C interface of the slave device is inserted correctly or reversely. When the Type-C interface is inserted correctly, a group of high-speed signal pins in the correct insertion working state are connected to the hub; when the Type-C interface is inserted reversely, another group of high-speed signal pins in the reverse insertion working state are connected to the hub. The problem with this interface circuit is that the cost of the multiplexer is relatively high, resulting in a relatively high hardware cost of the interface circuit.

[0038] Among them, the high-speed signal pins refer to the high-speed signal pins for data transmission in the Type-C interface, which are also called Super Speed differential signal pins or High Speed differential signal pins.

[0039] Such as Figure 2 and Figure 3 shown, Figure 2 is a schematic diagram of the pins of a socket in a Type-C interface in the related art, Figure 3 is a schematic diagram of the pins of a plug in a Type-C interface in the related art. The Type-C interface has group A pins and group B pins. The pins TX1+ and TX1- in group A pins and the pins RX1+ and RX1- in group B pins form a group of high-speed signal pins, and the pins TX2+ and TX2- in group B pins and the pins RX2+ and RX2- in group A pins form another group of high-speed signal pins.

[0040] Among them, the working state can also be called the connected state. The high-speed signal pins in the working state refer to a group of high-speed signal pins that are interconnected with a corresponding group of high-speed signal pins in the opposite end when the plug of the Type-C interface is connected to the socket. Such as Figure 2 and Figure 3As shown, taking a socket as an example, when a plug is inserted into the socket in the forward direction, if the pin RX1+ in the socket is connected to the pin RX1+ in the plug, the pin RX1- in the socket is connected to the pin RX1- in the plug, the pin TX1- in the socket is connected to the pin TX1- in the plug, and the pin TX1+ in the socket is connected to the pin TX1+ in the plug, then a set of high-speed signal pins in the socket that are in the working state are the pins composed of pin TX1+, pin TX1-, pin RX1+ and pin RX1-.

[0041] To solve the problem of relatively high hardware cost of the interface circuit, an embodiment of the present application provides an interface circuit, which includes: a hub, a first Universal Serial Bus Type-C interface, and a switching switch.

[0042] Among them, the first Universal Serial Bus Type-C interface has two sets of first high-speed signal pins and two first configuration channel pins, and the two sets of first high-speed signal pins correspond one-to-one with the two first configuration channel pins; the switching switch has two downstream interfaces and one upstream interface, the two downstream interfaces are respectively connected to the two sets of first high-speed signal pins, and one upstream interface is connected to the first downstream interface of the hub; the switching switch is connected to the two first configuration channel pins, and is used for controlling the connection between the downstream interface and the upstream interface in the switching switch corresponding to the set of first high-speed signal pins in the working state when determining that one of the two sets of first high-speed signal pins is in the working state according to the pin voltages of the two first configuration channel pins.

[0043] The first Universal Serial Bus Type-C interface refers to the Universal Serial Bus Type-C interface in all the Universal Serial Bus Type-C interfaces provided in the interface circuit that is connected to a downstream interface of the hub through a switching switch. The first high-speed signal pins refer to the high-speed signal pins in the first Universal Serial Bus Type-C interface. The first configuration channel (Configuration Channel, CC) pins refer to the CC pins in the first Universal Serial Bus Type-C interface. The first downstream interface refers to one of all the downstream interfaces of the hub that matches the Type-C interface and can be connected to the Type-C interface.

[0044] As Figure 2 shown, the two CC pins in the first Universal Serial Bus Type-C interface are respectively the CC1 pin and the CC2 pin, and the CC1 pin and the CC2 pin are the two first configuration channel pins. A set of first high-speed signal pins composed of pin TX1+, pin TX1-, pin RX1+ and pin RX1- corresponds to the CC1 pin, and this set of first high-speed signal pins corresponds to the CC1 pin; a set of first high-speed signal pins composed of pin TX2+, pin TX2-, pin RX2+ and pin RX2- forms another set of first high-speed signal pins, and this set of first high-speed signal pins corresponds to the CC2 pin.

[0045] The switching switch can also be referred to as a switch circuit. The switching switch is used to switch between two groups of first high-speed signal pins, and switch the group of first high-speed signal pins in the working state among the two groups of first high-speed signal pins to be connected to the first downstream interface of the hub.

[0046] The hub supports protocols such as USB3.0, USB3.1, and USB3.2, enabling the first downstream interface to be matched and connected to a Type-C interface. It should be understood that the hub can also support USB2.0 and USB1.0 protocols, enabling other downstream interfaces in the hub to be matched and connected to a Type-A interface.

[0047] See Figure 4 , Figure 4 is a schematic diagram of the principle of an interface circuit provided by an embodiment of the present application. As Figure 4 shown, the interface circuit 20 includes a hub HUB, a switching switch 21, and a Type-C interface corresponding to the switching switch 21. The Type-C interface is connected to the hub through the switching switch 21, and this Type-C interface is the first Universal Serial Bus Type-C interface.

[0048] As Figure 4 shown, a pull-up resistor 22 corresponding to each first channel configuration pin is provided in the interface circuit 20. One end of each pull-up resistor 22 is connected to the power supply terminal VCC, and the other end is connected to the corresponding first channel configuration pin. The switching switch 21 has two control terminals, namely the control terminal A and the control terminal B shown in Figure 4 shown. One of the first channel configuration pins (CC1) is connected to the control terminal A, and the other first channel configuration pin CC2 is connected to the control terminal B. The switching switch 21 can detect the pin voltage of the CC1 pin through the control terminal A and detect the pin voltage of the CC2 pin through the control terminal B. When the pin voltage of the CC1 pin is a low-level voltage and the pin voltage of the CC2 pin is a high-level voltage, the switching switch 21 can determine that a group of first high-speed signal pins corresponding to the CC1 pin is in the working state, and can control a downstream interface of the switching switch 21 corresponding to this group of first high-speed signal pins to be connected to the upstream interface of the switching switch 21, so that this group of first high-speed signal pins is connected to the first downstream interface of the hub. At the same time, the other group of first high-speed signal pins is in the non-working state, and a downstream interface of the switching switch 21 corresponding to this group of first high-speed signal pins is disconnected from the upstream interface in the switching switch 21, so that the connection between this group of first high-speed signal pins and the first downstream interface of the hub is disconnected.

[0049] Similarly, when the pin voltage of the CC2 pin of the switching switch 21 is at a low level voltage and the pin voltage of the CC1 pin is at a high level voltage, it can be determined that a group of first high-speed signal pins corresponding to the CC2 pin are in a working state, and a downstream interface of the switching switch 21 corresponding to this group of first high-speed signal pins can be controlled to be connected to the upstream interface of the switching switch 21, so that this group of first high-speed signal pins are connected to the first downstream interface of the hub. At the same time, another group of first high-speed signal pins are in a non-working state, and a downstream interface of the switching switch 21 corresponding to this group of first high-speed signal pins is disconnected from the upstream interface in the switching switch 21, so that the connection between this group of first high-speed signal pins and the first downstream interface of the hub is disconnected.

[0050] Exemplarily, when the interface circuit is integrated in a host device (such as a computer), the upstream interface of the hub can be connected to a USB controller in the computer, and the USB controller can be connected to a south bridge chip in the computer through a Peripheral Component Interconnect (PCI) bus, and the south bridge chip is connected to a processor in the computer. In this way, when the first universal serial bus type-C interface in the interface circuit is connected to the Type-C interface of a slave device, the slave device can be connected to the processor of the computer through the hub.

[0051] Exemplarily, the interface circuit can also be used as an independent circuit module and arranged outside the host device. At this time, the upstream interface of the hub can be connected to a USB interface of the host device, so that the slave device connected to the downstream interface of the hub can be connected to the host device. It should be understood that the application scenarios of the interface circuit can include but are not limited to the above examples.

[0052] It should be noted that the interface circuit may include one or more first universal serial bus type-C interfaces, and each first universal serial bus type-C interface can be connected to the hub in the Figure 4 shown manner.

[0053] In the embodiment of the present application, a hub, a first universal serial bus type-C interface, and a switching switch are arranged in the interface circuit. The switching switch is connected to two groups of first high-speed signal pins of the first universal serial bus type-C and is also connected to a downstream interface of the hub. During the working process of the interface circuit, the switching switch can connect a group of first high-speed signal pins in a working state to the hub, so that the two groups of first high-speed signal pins can share a downstream interface of the hub. In this way, the first universal serial bus type-C can be connected to only one downstream interface of the hub, so that the hub can be connected to more USB interfaces. At the same time, the use of a multiplexer to connect the first universal serial bus type-C can be avoided, and thus the hardware cost of the interface circuit can be reduced.

[0054] Optionally, the interface circuit may further include a delay switch; the first USB Type-C interface has two power pins, and the two power pins correspond to two groups of first high-speed signal pins one by one; the control end of the delay switch is connected to the two first configuration channel pins, the delay switch is respectively connected to the two power pins and is connected to the power supply end in the interface circuit; the delay switch is configured to delay the connection between one power pin corresponding to the group of first high-speed signal pins in the working state and the power supply end when it is determined that one group of first high-speed signal pins is in the working state according to the pin voltages of the two first configuration channel pins.

[0055] Among them, the delay switch may also be referred to as a delay switch circuit, which has delay and switch functions. The delay switch is configured to control the power pin corresponding to the group of first high-speed signal pins to be connected to the power supply end in the interface circuit after a period of delay when it is determined that one group of first high-speed signal pins is in the working state according to the pin voltages of the two first configuration channel pins, so as to supply power to the slave device connected to the first USB Type-C interface.

[0056] See Figure 5 , Figure 5 which is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application. As Figure 5 shown, a delay switch 23 is provided in the interface circuit 20. The first USB Type-C interface has two power pins (VBUS), and each power pin corresponds to one of the two groups of first high-speed signal pins. Specifically, two switching elements 231 may be provided in the delay switch 23, and the two switching elements 231 correspond to the two power pins one by one, that is, each switching element 231 corresponds to one power pin, and the power pin corresponding to each group of first high-speed signal pins is connected to the power supply end VCC in the interface circuit 20 through one of the switching elements 231.

[0057] As Figure 5 shown, the delay switch 23 has two control ends, namely control end C and control end D. The control end C is connected to the CC1 pin and can detect the pin voltage of the CC1 pin. The control end D is connected to the CC2 pin and can detect the pin voltage of the CC2 pin. When the delay switch 23 detects that the pin voltage of the CC1 pin becomes a low-level voltage and the pin voltage of the CC2 pin remains a high-level voltage, it can be determined that a group of second high-speed signals corresponding to the CC1 pin enters the working state. After that, the delay switch 23 can start timing. After the timing duration reaches the preset duration, the switching element corresponding to the group of first high-speed signal pins is controlled to close, so that the power pin corresponding to the group of first high-speed signal pins is connected to the power supply end.

[0058] Similarly, when the pin voltage of the CC2 pin of the delay switch 23 becomes a low-level voltage and the pin voltage of the CC1 pin remains a high-level voltage, it can be determined that a group of second high-speed signals corresponding to the CC2 pin is in a working state. After that, the delay switch 23 can start timing. After the timing duration reaches a preset duration, the switch element corresponding to the first high-speed signal pin of this group is controlled to close, so that the power supply pin corresponding to the first high-speed signal pin of this group is connected to the power supply terminal.

[0059] It can be seen from Figure 5 that when the delay switch 23 is provided in the interface circuit 20, when the Type-C interface of the slave device is inserted into the first Universal Serial Bus Type-C interface, the power supply pin of the first Universal Serial Bus Type-C interface is not directly connected to the power supply terminal VCC of the interface circuit 20, but is connected to the power supply terminal VCC after a preset delay duration. That is, after the Type-C interface of the slave device is inserted into the first Universal Serial Bus Type-C interface for a period of time, the interface circuit 20 will supply power to the slave device through one of the power supply pins.

[0060] In the embodiment of the present application, through the delay switch, after one group of first high-speed signal pins is connected to the high-speed signal pins in the slave device, after a certain delay duration, it is controlled that the interface circuit supplies power to the slave device through the corresponding power supply pin, which can ensure that after the switching switch connects the first high-speed signal pin in the working state to the hub, the Type-C interface of the slave device and the first Universal Serial Bus Type-C interface start to work.

[0061] Optionally, the power supply pin is connected to the delay switch through a current-limiting branch, or the power supply terminal is connected to the delay switch through a current-limiting branch.

[0062] Among them, the current-limiting branch can be a current-limiting integrated circuit (IC) composed of one or more electronic components such as a resistor, a capacitor, and an inductor, which is used to reduce the current input from the power supply pin to the delay switch or reduce the current input from the power supply terminal to the delay switch.

[0063] Refer to Figure 6 , Figure 6 which is a schematic diagram of the principle of another interface circuit provided by the embodiment of the present application. As Figure 6As shown in the figure, a current-limiting IC is provided in the interface circuit 20. The delay switch 23 can be connected to the power supply pin VBUS through the current-limiting IC. When a certain switch element in the delay switch 23 is closed, a power supply pin VBUS corresponding to the switch element is connected to the power supply terminal VCC through the current-limiting IC. At this time, the power supply terminal VCC can input current to the power supply pin VBUS, and supply power to the connected slave device through the power supply pin VBUS. At the same time, the current IC can reduce the current input from the power supply terminal VCC to the power supply pin VBUS, thereby protecting the slave device. Similarly, the current-limiting IC can also be provided between the power supply terminal (VCC) and the delay switch 23, and this embodiment does not limit this.

[0064] In the embodiment of the present application, a current-limiting branch is provided in the interface circuit. The current input from the power supply terminal in the interface circuit to the power supply pin can be limited through the current-limiting branch, so that over-current protection can be provided for the slave device connected to the first Universal Serial Bus Type-C interface.

[0065] Optionally, the interface circuit further includes two pull-up resistors, and the two pull-up resistors correspond to the two first configuration channel pins one by one; one end of each pull-up resistor is connected to the corresponding first configuration channel pin, and the other end is connected to the power supply terminal in the interface circuit.

[0066] As Figure 6 shown in the figure, two pull-up resistors 22 are provided in the interface circuit. Each pull-up resistor 22 corresponds to a CC pin and is connected to the corresponding CC. At the same time, the pull-up resistor 22 is connected to the power supply terminal VCC in the interface circuit. The pull-up resistor 22 is connected to the power supply terminal. When a corresponding group of first high-speed signal pins are in a non-working state, the pull-up resistor can pull up the pin voltage of the corresponding CC pin to a high-level voltage.

[0067] For each group of first high-speed signal pins, when the Type-C interface of the slave device is inserted into the first Universal Serial Bus Type-C interface, if the Type-C interface of the slave device pulls down the voltage of the corresponding CC pin to a low-level voltage, it is determined that this group of first high-speed signal pins are in a working state. If the voltage of the corresponding CC pin remains at a high-level voltage, it is determined that this group of first high-speed signal pins are in a non-working state.

[0068] Optionally, the interface circuit includes a second Universal Serial Bus Type-C interface; the second Universal Serial Bus Type-C interface has two groups of second high-speed signal pins. One group of second high-speed signal pins is connected to the second downstream interface of the hub, and the other group of second high-speed signal pins is connected to the third downstream interface of the hub.

[0069] Among them, the second Universal Serial Bus Type-C interface refers to the Type-C interface in all the Type-C interfaces provided in the interface circuit, where each group of high-speed signal pins is directly connected to a downstream interface in the hub. The second high-speed signal pins refer to the high-speed signal pins in the second Universal Serial Bus Type-C interface. The second downstream interface and the third downstream interface refer to two downstream interfaces among all the downstream interfaces of the hub that are compatible with the Type-C interface and can be connected to the Type-C interface.

[0070] See Figure 7 , Figure 7 which is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application. As Figure 7 shown, in addition to the first Universal Serial Bus Type-C interface in this interface circuit, it further includes a Type-C interface directly connected to the hub. This Type-C interface is the second Universal Serial Bus Type-C interface. The two groups of high-speed signal pins of this Type-C interface are two groups of second high-speed signal pins. The two groups of second high-speed signal pins are respectively connected to a downstream interface in the hub. One group of second high-speed signal pins is connected to the second downstream interface of the hub, and the other group of second high-speed signal pins is connected to the third downstream interface of the hub. The second downstream interface and the third downstream interface are interfaces of the same type as the first downstream interface.

[0071] Combined with Figure 2 shown, when the second Universal Serial Bus Type-C interface is a receptacle in the Type-C interface, each group of second high-speed signal pins in the second Universal Serial Bus Type-C interface has 4 pins. One group of second high-speed signal pins includes pin TX1+, pin TX1-, pin RX1+, and pin RX1-. The other group of second high-speed signal pins includes pin TX2+, pin TX2-, pin RX2+, and pin RX2-.

[0072] Correspondingly, the second downstream interface and the third downstream interface are the same two downstream interfaces, each having 4 pins. Four pins of one of the second downstream interface and the third downstream interface are respectively connected to pin TX1+, pin TX1-, pin RX1+, and pin RX1-. Four pins of the other are respectively connected to pin TX2+, pin TX2-, pin RX2+, and pin RX2-.

[0073] As Figure 7 shown, when the second Universal Serial Bus Type-C interface in the interface circuit is a receptacle, the Type-C interface in the slave device is a plug. Combined with Figure 3As shown, only one set of high-speed signal pins can be set in the Type-C interface of the slave device. At this time, regardless of whether the Type-C interface in the slave device is inserted forward or backward into the second Universal Serial Bus Type-C interface, one set of high-speed signal pins in the Type-C interface (plug) of the slave device can be connected to one set of second high-speed signal pins in the second Universal Serial Bus Type-C interface. One set of second high-speed signal pins connected to the high-speed signal pins in the slave device is in the working state, and the other set of second high-speed signal pins is floating and in the non-working state (i.e., the idle state). At this time, the hub can be connected to the slave device through one set of second high-speed signal pins in the working state, and the slave device can be connected to the master device.

[0074] Optionally, the second Universal Serial Bus Type-C interface also has two power pins and two ground pins. As Figure 2 shown, the two power pins are the VBUS pin in group A and the VBUS pin in group B respectively, and the two ground pins are the GND pin in group A and the GND pin in group B respectively. The two power pins correspond one-to-one with the two sets of second high-speed signal pins, and the two ground pins correspond one-to-one with the two sets of second high-speed signal pins. When the Type-C interface in the slave device is connected to the second Universal Serial Bus Type-C interface in the interface circuit, the power pin corresponding to one set of second high-speed signal pins in the working state is connected to the power supply terminal in the interface circuit, which can supply power to the slave device, and the ground pin is short-circuited with the GND pin of the slave device.

[0075] Exemplarily, when the interface circuit is integrated in the master device (such as a computer), the upstream interface of the hub can be connected to the USB controller in the computer, the USB controller can be connected to the south bridge chip in the computer through the PCI bus, and the south bridge chip is connected to the processor in the computer. In this way, when the second Universal Serial Bus Type-C interface in the interface circuit is connected to the Type-C interface of the slave device, the slave device can be connected to the processor of the computer through the hub.

[0076] It should be noted that the interface circuit may include one or more second Universal Serial Bus Type-C interfaces, and each second Universal Serial Bus Type-C interface can be connected to the hub in the Figure 7 shown manner.

[0077] In the embodiment of the present application, the interface circuit includes a second Universal Serial Bus Type-C interface, and the second Universal Serial Bus Type-C interface has two sets of second high-speed signal pins. One set of second high-speed signal pins is connected to the second downstream interface of the hub, and the other set of second high-speed signal pins is connected to the third downstream interface of the hub. In this way, a corresponding multiplexer does not need to be set for the second Universal Serial Bus Type-C interface in the interface circuit, thereby reducing the hardware cost of the interface circuit.

[0078] Optionally, the interface circuit further includes two current-limiting branches; the second USB Type-C interface further has two power pins, and the two power pins correspond to two groups of second high-speed signal pins one by one. The two power pins are respectively connected to the power supply terminal in the interface circuit through a current-limiting branch.

[0079] See Figure 8 , Figure 8 FIG. Figure 8 shows a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application. As shown in

[0080] In the embodiment of the present application, a current-limiting branch is provided in the interface circuit to limit the current input from the power supply terminal in the interface circuit to the power pin, so as to provide over-current protection for the slave device connected to the second USB Type-C interface.

[0081] Optionally, the second USB Type-C interface further has one or two groups of low-speed signal pins, and each group of low-speed signal pins is connected to a fourth downstream interface of the hub.

[0082] Among them, the low-speed signal pins can also be called low-speed differential signal pins, and the low-speed signal pins in the Type-C interface are used to be compatible with the USB2.0 protocol. The fourth downstream interface refers to a downstream interface among the multiple downstream interfaces of the hub that matches the low-speed signal pins and can be connected to the low-speed signal pins.

[0083] As shown in Figure 2 when the second USB Type-C interface is a socket in the Type-C interface, two groups of low-speed signal pins can be provided in the Type-C interface. One group of low-speed signal pins includes pin D+ and pin D- in group A of the pins, and the other group of low-speed signal pins includes pin D- and pin D+ in group B of the pins. Alternatively, only one of the two groups of low-speed signal pins can be provided in the Type-C interface.

[0084] As shown in Figure 8As shown, when two sets of low-speed signal pins are provided in the second USB Type-C interface, each set of low-speed signal pins is connected to a fourth downstream interface of the hub. Each set of low-speed signal pins includes two pins, namely pin D+ and pin D-. The fourth downstream interface has two corresponding pins, and the low-speed signal pins can be connected to the corresponding fourth downstream interface.

[0085] Among them, when two sets of low-speed signal pins are provided in the second USB Type-C interface, one set of low-speed signal pins can be provided in the Type-C interface of the slave device. During the use of the interface circuit, when the Type-C interface (plug) of the slave device is inserted into the second USB Type-C interface, regardless of whether the Type-C interface of the slave device is inserted forward or backward, one set of low-speed signal pins in the Type-C interface of the slave device can be connected to one set of low-speed signal pins in the second USB Type-C interface, enabling communication between the slave device and the master device through the interconnected low-speed signal pins.

[0086] When one set of low-speed signal pins is provided in the second USB Type-C interface, one set of low-speed signal pins can be provided in the Type-C interface of the slave device. During the use of the interface circuit, when the Type-C interface (plug) of the slave device is inserted into the second USB Type-C interface, whether the Type-C interface of the slave device is inserted forward or backward, one set of low-speed signal pins in the Type-C interface of the slave device is connected to one set of low-speed signal pins in the second USB Type-C interface, enabling communication between the slave device and the master device through the interconnected low-speed signal pins.

[0087] In the embodiment of the present application, the second USB Type-C interface has one or two sets of low-speed signal pins, and each set of low-speed signal pins is connected to a first downstream interface of the hub, enabling the interface circuit to support slave devices that communicate through low-speed signal pins.

[0088] Optionally, the interface circuit further includes an interlock switch. The second USB Type-C interface further has two second configuration channel pins, and the two second configuration channel pins correspond to two sets of second high-speed signal pins one by one; the interlock switch has two downstream interfaces and two upstream interfaces. The two downstream interfaces are respectively connected to the two sets of second high-speed signal pins, and the two upstream interfaces are respectively connected to the second downstream interface and the third downstream interface; the interlock switch is connected to the two second configuration channel pins and is used to control the connection between the upstream interface and the downstream interface of the interlock switch corresponding to the set of second high-speed signal pins in the working state and control the disconnection between the upstream interface and the downstream interface of the interlock switch corresponding to the other set of second high-speed signal pins when determining that one set of second high-speed signal pins is in the working state according to the pin voltages of the two second configuration channel pins.

[0089] Among them, the second configuration channel pin refers to the CC pin in the second Universal Serial Bus Type-C interface. The interlock switch is used to implement the interlock of two groups of second high-speed signal pins. When one group of second high-speed signal pins is in the working state, the connection between the other group of second high-speed signal pins and the downstream interface of the corresponding hub can be disconnected, so that the other group of second high-speed signal pins is in the non-working state.

[0090] As Figure 2 shown, the two CC pins in the second Universal Serial Bus Type-C interface are the CC1 pin and the CC2 pin respectively. The CC1 pin corresponds to a group of second high-speed signal pins composed of the pin TX1+, the pin TX1-, the pin RX1+ and the pin RX1-. The CC2 pin corresponds to a group of second high-speed signal pins composed of the pin TX2+, the pin TX2-, the pin RX2+ and the pin RX2-.

[0091] See Figure 9 , Figure 9 is a schematic diagram of the principle of another interface circuit provided by an embodiment of the present application. As Figure 9 shown, an interlock switch 24 corresponding to the second Universal Serial Bus Type-C interface is provided in the interface circuit. The interlock switch 24 has two downstream interfaces, each downstream interface is used to connect a group of high-speed signal pins. The interlock switch also has two upstream interfaces, one upstream interface is connected to the second downstream interface of the hub, and the other upstream interface is connected to the third downstream interface of the hub.

[0092] At the same time, two pull-up resistors 22 can be provided in the interface circuit 20. Each pull-up resistor corresponds to a CC pin. One end of each pull-up resistor is connected to the corresponding CC pin, and the other end is connected to the power supply terminal VCC in the interface circuit. When the Type-C interface of the slave device is not inserted into the second Universal Serial Bus Type-C interface, the pull-up resistor can pull up the pin voltage of the corresponding CC pin to a high-level voltage. Correspondingly, the CC pin in the Type-C interface of the slave device can be connected to a pull-down resistor, and the pin voltage of the CC pin is pulled down to a low-level voltage through the pull-down resistor.

[0093] The control end of the interlock switch 24 is connected to the CC1 pin and the CC2 pin. When the Type-C interface of the slave device is not inserted into the second Universal Serial Bus Type-C interface, the pin voltages of the two CC pins in the second Universal Serial Bus Type-C interface are pulled up to high-level voltages by the pull-up resistors. When the Type-C interface of the slave device is inserted into the Type-C interface in the interface circuit in the forward direction, the pin voltage of the CC1 pin is pulled down to a low-level voltage, and the pin voltage of the CC2 pin remains at a high-level voltage; while when the Type-C interface of the slave device is inserted into the Type-C interface in the interface circuit in the reverse direction, the pin voltage of the CC1 pin remains at a high-level voltage, and the pin voltage of the CC2 pin is pulled down to a low-level voltage.

[0094] Correspondingly, when the pin voltage of the CC1 pin of the interlock switch is pulled down to a low level voltage and the pin voltage of the CC2 pin is a high level voltage, it can be determined that a group of first high-speed signals corresponding to the CC1 pin are in the working state. The interlock switch can control the connection of a downstream interface and an upstream interface of the interlock switch corresponding to the group of second high-speed signal pins, so that the group of second high-speed signal pins are connected to the hub. At the same time, the interlock switch can control a group of second high-speed signal pins corresponding to the CC2 pin to be in a non-working state, and can control the disconnection of a downstream interface and an upstream interface of the interlock switch corresponding to the group of second high-speed signal pins, ensuring the disconnection of the connection between the group of second high-speed signal pins and the hub.

[0095] Similarly, when the pin voltage of the CC1 pin of the interlock switch is a high level voltage and the pin voltage of the CC2 pin is pulled down to a low level voltage, it can be determined that a group of first high-speed signals corresponding to the CC2 pin are in the working state. The interlock switch can control the connection of a downstream interface and an upstream interface of the interlock switch corresponding to the group of second high-speed signal pins, so that the group of second high-speed signal pins are connected to the hub. At the same time, the interlock switch can control a group of second high-speed signal pins corresponding to the CC1 pin to be in a non-working state, and can control the disconnection of a downstream interface and an upstream interface of the interlock switch corresponding to the group of second high-speed signal pins, ensuring the disconnection of the connection between the group of second high-speed signal pins and the hub.

[0096] In this embodiment, the interlock switch can implement the interlock of two groups of second high-speed signal pins, so that when a slave device is inserted, the interface circuit can only control one of the two groups of second high-speed signal pins to be connected to the hub, thereby avoiding interference from the other group of first high-speed signals to the group of high-speed signal pins in the working state.

[0097] Optionally, the interface circuit further includes a Universal Serial Bus Type-A interface, and the Universal Serial Bus Type-A interface is connected to the fifth downstream interface of the hub.

[0098] Wherein, the fifth downstream interface refers to the downstream interface in the hub that matches the Type-A interface and can be connected to the Type-A interface.

[0099] As Figures 4 - 9 shown, the interface circuit may include one or more Type-A interfaces, the hub has a plurality of fifth downstream interfaces, and each Type-A interface is connected to one of the fifth downstream interfaces. In this way, the interface circuit can be connected to multiple slave devices with Type-A interfaces.

[0100] In an embodiment of the present application, the interface circuit includes one or more Universal Serial Bus Type-A interfaces, enabling the interface circuit to uniformly manage multiple Universal Serial Bus Type-A interfaces, so that the host device can be connected to one or more devices with Type-A interfaces.

[0101] An embodiment of the present application further provides an electronic device, which includes a Universal Serial Bus controller and the interface circuit in the above example, and the upstream interface in the hub is connected to the USB controller. Among them, the electronic device can be a computer, a laptop, an intelligent interactive tablet, etc., but is not limited thereto.

[0102] The above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. An interface circuit, characterized in that, The interface circuit includes: a hub, a first Universal Serial Bus Type-C interface, and a switching switch; The first Universal Serial Bus Type-C interface has two groups of first high-speed signal pins and two first configuration channel pins, and the two groups of first high-speed signal pins correspond to the two first configuration channel pins one by one; The switching switch has two downstream interfaces and one upstream interface. The two downstream interfaces are respectively connected to the two groups of first high-speed signal pins, and the one upstream interface is connected to the first downstream interface of the hub; The switching switch is connected to the two first configuration channel pins, and is configured to control the connection between the downstream interface and the upstream interface in the switching switch corresponding to the group of first high-speed signal pins in a working state when it is determined that one of the two groups of first high-speed signal pins is in a working state according to the pin voltages of the two first configuration channel pins.

2. The interface circuit according to claim 1, characterized in that, The interface circuit further includes a delay switch; The first Universal Serial Bus Type-C interface has two power pins, and the two power pins correspond to the two groups of first high-speed signal pins one by one; The control end of the delay switch is connected to the two first configuration channel pins. The delay switch is respectively connected to the two power pins and is also connected to the power supply terminal in the interface circuit; The delay switch is configured to delay the connection between one of the power pins corresponding to the group of first high-speed signal pins in a working state and the power supply terminal when it is determined that one of the two groups of first high-speed signal pins is in a working state according to the pin voltages of the two first configuration channel pins.

3. The interface circuit according to claim 2, wherein The power pin is connected to the delay switch through a current-limiting branch, or the power supply terminal is connected to the delay switch through a current-limiting branch.

4. The interface circuit according to claim 1, wherein The interface circuit further includes two pull-up resistors, and the two pull-up resistors correspond to the two first configuration channel pins one by one; One end of each pull-up resistor is connected to the corresponding first configuration channel pin, and the other end is connected to the power supply terminal in the interface circuit.

5. The interface circuit according to claim 1, wherein The interface circuit includes: a second Universal Serial Bus Type-C interface; The second Universal Serial Bus Type-C interface has two groups of second high-speed signal pins. One group of the second high-speed signal pins is connected to the second downstream interface of the hub, and the other group of the second high-speed signal pins is connected to the third downstream interface of the hub.

6. The interface circuit according to claim 5, wherein The interface circuit further includes an interlock switch. The second Universal Serial Bus Type-C interface further has two second configuration channel pins, and the two second configuration channel pins correspond to the two groups of second high-speed signal pins one by one; The interlock switch has two downstream interfaces and two upstream interfaces. The two downstream interfaces are respectively connected to the two groups of second high-speed signal pins, and the two upstream interfaces are respectively connected to the second downstream interface and the third downstream interface; The interlock switch is connected to the two second configuration channel pins, and is configured to control the connection of the upstream interface and the downstream interface in the interlock switch corresponding to one set of the second high-speed signal pins and control the disconnection of the upstream interface and the downstream interface in the interlock switch corresponding to the other set of the second high-speed signal pins when it is determined that one set of the second high-speed signal pins is in an operating state according to the pin voltages of the two second configuration channel pins.

7. The interface circuit according to claim 6, wherein The interface circuit further includes two current-limiting branches; The second USB Type-C interface further has two power pins, the two power pins corresponding to the two sets of second high-speed signal pins one by one, and the two power pins are respectively connected to a power supply terminal in the interface circuit through one of the current-limiting branches.

8. The interface circuit according to claim 6, characterized in that, The second USB Type-C interface further has one or two sets of low-speed signal pins, and each set of the low-speed signal pins is connected to a fourth downstream interface of the hub.

9. The interface circuit according to any one of claims 1-8, characterized in that, The interface circuit further includes a USB Type-A interface, and the USB Type-A interface is connected to a fifth downstream interface of the hub.

10. An electronic device, characterized in that, Comprising: Comprising a universal serial bus controller and the interface circuit according to any one of claims 1-9, wherein an upstream interface of the hub is connected to the universal serial bus controller.

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