Charging and discharging compensation circuit, display screen and electronic equipment

Abstract

The utility model discloses a charging and discharging compensation circuit, a display screen and electronic equipment, and belongs to the technical field of display. The charging and discharging compensation circuit comprises a load capacitor, a preprocessing circuit, a current mirror circuit, a switching circuit, a sampling detection circuit and a capacitance compensation circuit. The preprocessing circuit adjusts the voltage of the load capacitor to a preset value; the current mirror image circuit outputs mirror image current for charging or discharging the load capacitor; the switching circuit is used for controlling the charging or discharging time of the load capacitor; the sampling detection circuit generates a mirror current calibration signal or a load capacitor calibration signal based on the magnitude between the capacitor voltage on the load capacitor and the target voltage; the capacitance compensation circuit compensates the load capacitance based on the load capacitance calibration signal. According to the utility model, load capacitance of all pixel columns can be compensated through the capacitance compensation circuit, pixel voltage difference caused by charging and discharging current difference between different pixel columns can be compensated, and image display quality is improved.

Description

Technical Field

[0001] The present utility model relates to the field of display technology, and particularly to a charge-discharge compensation circuit, a display screen having the charge-discharge compensation circuit, and an electronic device having the display screen. Background Art

[0002] Currently, as the human-computer interaction interface, display screens are increasingly widely used, and their application fields include but are not limited to devices such as smart phones, tablet computers, laptop computers, televisions, desktop monitors, AR / VR / MR / XR, HUD, etc. In a display screen, each pixel unit corresponds to a pixel circuit, and the pixel circuit is arranged at the intersection of scan lines arranged in the row direction for supplying control signals and data lines arranged in the column direction for supplying data signals to drive the corresponding pixel unit to display an image. During the image display process, it is necessary to charge the capacitor in the pixel circuit so that the capacitor can control the light-emitting element to emit light during the light-emitting stage.

[0003] With the increase in the size of the display, the number of pixels increases, and the differences between pixel columns due to manufacturing processes become larger and larger, seriously affecting the picture quality of the display. The traditional pixel column compensation method is achieved by adjusting the magnitude of the charge-discharge current of the pixel column. However, because the charge-discharge current of the pixel column itself is relatively small, the amplitude of current compensation will be even smaller, and it becomes increasingly difficult to accurately control the current, thereby affecting the accuracy of the pixel data voltage and resulting in an unsatisfactory display picture compensation effect.

[0004] The information disclosed in this background art section is only intended to enhance the overall understanding of the present utility model and should not be regarded as an admission or any form of suggestion that this information constitutes prior art already known to those of ordinary skill in the art. Summary of the Utility Model

[0005] An object of the present utility model is to provide a charge-discharge compensation circuit that can compensate for all column load capacitors, eliminate the pixel voltage difference caused by the difference in the charge-discharge current of the pixel column, and improve the image display quality.

[0006] Another object of the present utility model is to provide a display screen and an electronic device that can compensate for all column load capacitors, eliminate the pixel voltage difference caused by the difference in the charge-discharge current of the pixel column, and improve the image display quality.

[0007] To achieve the above object, a specific embodiment of the present utility model provides a charge-discharge compensation circuit, including

[0008] at least one load capacitor;

[0009] At least one preprocessing circuit, each of the preprocessing circuits corresponding to one of the load capacitors, the preprocessing circuit being connected to the corresponding load capacitor to form a connection point, and the preprocessing circuit being configured to adjust the voltage of the corresponding load capacitor to a preset value;

[0010] A current mirror circuit, the current mirror circuit being configured to mirror a reference current and output, through at least one output branch, a mirror current for charging or discharging the load capacitor, each of the output branches corresponding to one of the connection points;

[0011] At least one switch circuit, each of the switch circuits corresponding to one of the output branches, each of the output branches being connected to the corresponding connection point through the corresponding switch circuit, the switch circuit being configured to control the preprocessing circuit to adjust the voltage of the corresponding load capacitor to a preset value and the charging or discharging time of the load capacitor;

[0012] A sampling and detection circuit, the sampling and detection circuit being configured to generate a mirror current calibration signal for adjusting the reference current based on the magnitude relationship between the capacitance voltage on the load capacitor and the target voltage in the first mode, and generate a load capacitor calibration signal based on the magnitude relationship between the capacitance voltage on the load capacitor and the target voltage in the second mode;

[0013] At least one capacitance compensation circuit, each of the capacitance compensation circuits corresponding to one of the load capacitors, the capacitance compensation circuit being connected to the connection point, and the capacitance compensation circuit compensating the load capacitor based on the load capacitor calibration signal so as to obtain a corresponding capacitance voltage based on the mirror current through the compensated load capacitor.

[0014] In one or more embodiments of the present invention, each of the preprocessing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to a preset value.

[0015] In one or more embodiments of the present invention, the preprocessing circuit includes:

[0016] A first MOS transistor, the source terminal being connected to a reference voltage source or ground, the drain terminal being connected to the load capacitor to form the connection point, and the gate terminal being connected to the control signal.

[0017] In one or more embodiments of the present invention, the current mirror circuit includes:

[0018] A second MOS transistor, the drain terminal being connected to a reference current source, the source terminal being connected to a voltage source or ground, and the gate terminal being connected to the drain terminal;

[0019] At least one third MOS transistor, the drain terminal of each third MOS transistor serving as an output branch, the source terminals being commonly connected to a voltage source or ground, and the gate terminals being all connected to the gate terminal of the second MOS transistor.

[0020] In one or more embodiments of the present invention, the switching circuit includes:

[0021] The fourth MOS transistor has a source terminal connected to the output branch, a drain terminal connected to the connection point, and a gate terminal connected to the control signal.

[0022] In one or more embodiments of the present invention, the sampling detection circuit includes:

[0023] Detection resistor;

[0024] Several calibration circuits, each corresponding to a pixel column, and each calibration circuit is connected to a voltage source or ground through a detection resistor to form a detection point. Each calibration circuit is used to receive the capacitor voltage and target voltage on the load capacitor, and select to convert the capacitor voltage on the corresponding load capacitor into a sampling current or convert the target voltage into a comparison current and input it into the detection resistor;

[0025] At least one detection circuit is used to generate a mirror current calibration signal in a first mode based on the magnitude of a sampling voltage generated by the sampling current in the detection resistor and the magnitude of a comparison voltage generated by the comparison current in the detection resistor, and to generate a load capacitance calibration signal in a second mode based on the magnitude of a sampling voltage generated by the sampling current in the detection resistor and the magnitude of a comparison voltage generated by the comparison current in the detection resistor.

[0026] In one or more embodiments of the present invention, all pixel columns share a detection circuit.

[0027] In one or more embodiments of the present invention, the calibration circuit includes:

[0028] a fifth MOS transistor, connected in series with the detection resistor between the voltage source and the ground;

[0029] a first switch, one end of which is connected to a reference voltage, and an opposite end of which is connected to a gate terminal of a fifth MOS transistor;

[0030] A second switch, one end of which is connected to the capacitor voltage on the load capacitor, and the opposite end of which is connected to the gate terminal of the fifth MOS transistor;

[0031] a third switch, one end of which is connected to a voltage source, and an opposite end of which is connected to a gate terminal of the fifth MOS transistor;

[0032] The switch control circuit is connected to the first switch, the second switch and the third switch, and is used to control the closing or opening of the first switch, the second switch and the third switch.

[0033] In one or more embodiments of the present utility model, the switch control circuit is a logic circuit composed of gate-level circuits, with inputs being calibration_mode0, calibration_mode1, and data[M], and outputs being Q1, Q2, and Q3. The Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

[0034] In one or more embodiments of the present utility model, the switch circuit for controlling the charging or discharging time of the load capacitance includes:

[0035] During charging or discharging, the M-bit counter counts the charging or discharging time from 0 to 2 M -1, and when the counter counts from zero to the grayscale value corresponding to a column of pixels, the switch circuit corresponding to that column of pixels is turned off. M is the display color depth and M is an integer greater than 0.

[0036] In one or more embodiments of the present utility model, the capacitance compensation circuit includes a compensation control circuit, a switch unit, and a compensation capacitance array. The compensation capacitance array is connected to the connection point through the switch unit. The compensation control circuit generates a load capacitance compensation control signal based on the load capacitance calibration signal to control the opening and closing of the switch unit, so as to control the number of compensation capacitances connected to the connection point in the compensation capacitance array.

[0037] In one or more embodiments of the present utility model, the compensation capacitance array includes a plurality of compensation capacitances, and the switch unit includes a plurality of switches. Each switch is turned on and off based on the control of the corresponding load capacitance compensation control signal, and each compensation capacitance is connected to the connection point through the corresponding switch.

[0038] In one or more embodiments of the present utility model, the switch unit further includes a main switch that is turned on and off under the control of the load capacitance compensation control signal, and each of the switches is connected to the connection point through the main switch.

[0039] An embodiment of the present utility model provides a display screen, including the charge-discharge compensation circuit described above.

[0040] An embodiment of the present utility model provides an electronic device, including the display screen described above.

[0041] Compared with the prior art, the utility model can quickly charge or discharge the capacitors of all pixel circuits in each column, so that the voltage values of the capacitors meet the actual use requirements. Moreover, when charging or discharging the capacitors of each column of pixel circuits, independent constant current control is adopted, which can avoid interference between columns. At the same time, through the capacitor compensation circuit to compensate the load capacitors of all pixel columns, the difference in pixel voltages caused by the difference in the charging and discharging currents of different pixel columns can be compensated, and the image display quality can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings described below are only some embodiments recorded in the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0043] Figure 1 is a schematic structural diagram of a charge-discharge compensation circuit according to an embodiment of the present utility model;

[0044] Figure 2 is a partial circuit diagram of a charge-discharge compensation circuit according to an embodiment of the present utility model;

[0045] Figure 3 is a partial circuit diagram of a charge-discharge compensation circuit according to another embodiment of the present utility model;

[0046] Figure 4 is a circuit diagram of charge-discharge time control according to an embodiment of the present utility model;

[0047] Figure 5 is a schematic structural diagram of a sampling detection circuit according to an embodiment of the present utility model;

[0048] Figure 6 is a circuit diagram of a sampling detection circuit according to an embodiment of the present utility model;

[0049] Figure 7 is a circuit diagram of a sampling detection circuit according to another embodiment of the present utility model;

[0050] Figure 8 is a circuit diagram of a capacitor compensation circuit according to an embodiment of the present utility model;

[0051] Figure 9 is a schematic diagram of a ramp voltage according to an embodiment of the present utility model;

[0052] Figure 10 is a schematic diagram of a ramp voltage according to another embodiment of the present utility model. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the technical solutions in the present utility model, the following will clearly and completely describe the technical solutions in the embodiments of the present utility model with reference to the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments in the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0054] In the specification, "coupled" or "connected" or "linked" includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrical conduction medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include a connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes, such as a connection through circuits or components such as switches and follower circuits. In addition, in the utility model, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0055] In the detailed description of the specification, reference is made to the accompanying drawings that form a part thereof, in which the same reference numerals always denote the same components, and which are shown by way of exemplary embodiments that can be implemented. It should be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered limiting.

[0056] The various operations in the specification can be described as a plurality of discrete actions or operations in the order that is most helpful for understanding the claimed subject matter. However, the described order should not be construed as implying that these operations must be order-related. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed in additional embodiments and / or the described operations may be omitted.

[0057] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B) or (A and B). For the purposes of the present disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C).

[0058] Various components and devices may be referred to or shown in the singular form in this document (e.g., "MOS transistor", "transistor", "switch", etc.), but this is merely for the convenience of discussion, and any element referred to in the singular form may include a plurality of such elements in accordance with the teachings herein.

[0059] The specification describes the use of the phrases "in one embodiment", "in other embodiments", or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "comprising", "including", "having", etc. used with respect to the embodiments of the present disclosure are synonymous.

[0060] As Figures 1 to 4 shown, a charge-discharge compensation circuit according to a preferred embodiment of the present invention can quickly charge or discharge the capacitors of all pixel circuits in each column, so that the voltage of the capacitors meets the actual usage requirements, and the capacitors of each column of pixel circuits are independent of each other and do not interfere with each other during charging or discharging.

[0061] Specifically, as combined with Figures 1 to 8 shown, the charge-discharge compensation circuit includes at least one load capacitor, at least one preprocessing circuit 10, a current mirror circuit 20, a sampling and detection circuit, at least one switching circuit 30, and at least one capacitor compensation circuit 40. Among them, the load capacitor is used to store charges. Here, the load capacitor is the equivalent load capacitor of all pixel circuits in each column. Therefore, the number of load capacitors can be determined according to the number of columns.

[0062] The preprocessing circuits 10 correspond one-to-one with the load capacitors, that is, each preprocessing circuit 10 corresponds to one load capacitor. The preprocessing circuit 10 is connected to the corresponding load capacitor to form a connection point A. The preprocessing circuit 10 can adjust the voltage value of the load capacitor to a preset value, such as by charging the load capacitor to adjust the voltage value of the load capacitor to the preset value, or by discharging the load capacitor to adjust the voltage value of the load capacitor to the preset value, which can be selected according to actual needs.

[0063] The current mirror circuit 20 is used to mirror the reference current I REF and output it through at least one output branch to provide a mirror current I proportional to the reference current I REF for charging or discharging the load capacitor. Here, the output branches correspond one-to-one with the connection point A, or rather, the output branches correspond one-to-one with the load capacitors. At the same time, the proportionality here includes but is not limited to 1:1 and can be adjusted according to actual needs.

[0064] The switching circuit 30 corresponds to each output branch one by one. Each output branch is connected to the corresponding connection point A through the corresponding switching circuit 30, that is, the switching circuit 30 is connected between the connection point A and the output branch. The switching circuit 30 can control the preprocessing circuit 10 to control the charging or discharging time of the load capacitor, so that the voltage value of the capacitor voltage on the load capacitor reaches the actually required voltage value (preset value). The charging or discharging time here refers to the time experienced by the load capacitor from the current voltage value to the actually required voltage value.

[0065] The sampling and detection circuit is used to generate a mirror current calibration signal for adjusting the reference current based on the magnitude relationship between the capacitor voltage on the load capacitor and the target voltage in the first mode, and generate a load capacitor calibration signal based on the magnitude relationship between the capacitor voltage on the load capacitor and the target voltage in the second mode. In one embodiment, the first mode is the calibration_mode0 mode, and the second mode is the calibration_mode1 mode. The external device or module is controlled by the mirror current calibration signal to adjust the reference current.

[0066] The capacitance compensation circuit 40 corresponds to each load capacitor one by one. The capacitance compensation circuit 40 is connected to the connection point A. The capacitance compensation circuit 40 compensates the load capacitor based on the load capacitor calibration signal to obtain the corresponding capacitor voltage based on the compensated load capacitor and the mirror current I, so as to compensate the differences between different pixel columns and improve the display effect.

[0067] In specific implementation, the preprocessing circuit 10 first charges or discharges the corresponding load capacitor to make its voltage value reach the preset value, and the switching circuit 30 is in the off state during the charging or discharging process of the preprocessing circuit 10 to the load capacitor.

[0068] When the voltage value of the load capacitor reaches the preset value, the preprocessing circuit 10 is disconnected, and the current mirror circuit 20 starts to work. It mirrors the reference current I REF and outputs a mirror current I proportional to the reference current I REF through the output branch. At the same time, the switching circuit 30 is in the closed state. At this time, due to the existence of the mirror current I in the output branch, the voltage value of the capacitor voltage on the load capacitor continuously decreases or increases from the preset value, that is, the load capacitor is discharged or charged.

[0069] When the charging or discharging time of the load capacitor reaches, the switching circuit 30 is disconnected. At this time, there is no current in the loop, so the capacitor voltage of the load capacitor no longer decreases or increases. At this time, the voltage value of the capacitor voltage is the required voltage value.

[0070] Combined with Figure 2 and Figure 3As shown, the preprocessing circuit 10 includes a first MOS transistor. Among them, the gate terminal of the first MOS transistor is connected to a control signal, the source terminal is connected to a reference voltage source V H or ground, and the drain terminal is connected to the corresponding load capacitor to form a connection point A. In a specific implementation, the control signal controls the first MOS transistor to conduct, and the reference voltage source is electrically connected to the load capacitor. Furthermore, the voltage value of the load capacitor can be adjusted to the same voltage value as the reference voltage source by charging or discharging.

[0071] In this embodiment, all the preprocessing circuits 10 are controlled by the same control signal, so that the preprocessing circuit 10 adjusts the voltage value of the capacitance voltage of the corresponding load capacitor to a preset value, such as Figure 2 As shown, the gate terminals of all the first MOS transistors are controlled by the control signal S0. Of course, in other embodiments, each first MOS transistor can also be individually controlled by different control signals, which can be selected according to actual requirements.

[0072] Combined with Figure 2 and Figure 3 As shown, the current mirror circuit 20 includes a second MOS transistor and at least one third MOS transistor. Among them, the drain terminal of the second MOS transistor is connected to a reference current I REF , the source terminal is connected to the voltage source VDD or ground, and the gate terminal is connected to the drain terminal. The drain terminal of each third MOS transistor serves as an output branch for outputting the mirror current I, the source terminals are commonly connected to the voltage source VDD or ground, and the gate terminals are all connected to the gate terminal of the second MOS transistor. The second MOS transistor can form a basic current mirror with a third MOS transistor to mirror the reference current I REF to the corresponding output branch.

[0073] In this embodiment, the second MOS transistor and the third MOS transistor are selected from one of PMOS transistors or NMOS transistors, which can be selected according to actual requirements.

[0074] Combined with Figure 2 and Figure 3 As shown, the switch circuit 30 includes a fourth MOS transistor, which is selected from one of PMOS transistors or NMOS transistors. Among them, the source terminal of the fourth MOS transistor is connected to the corresponding output branch, the drain terminal is connected to the corresponding connection point A, and the gate terminal is connected to a control signal. In a specific implementation, the control signal controls the fourth MOS transistor to conduct, and then the output branch and the corresponding load capacitor can form a loop, so that a current is generated in the loop. Furthermore, as time goes by, the voltage value of the capacitance voltage of the load capacitor changes.

[0075] In this embodiment, each fourth MOS transistor is controlled by a different control signal. That is to say, each fourth MOS transistor is controlled by the corresponding control signal. Combined with Figure 2 and Figure 3As shown, each fourth MOS transistor is controlled by a different control signal. By enabling each fourth MOS transistor to be controlled by a different control signal, the charging or discharging time of each load capacitor can be individually controlled.

[0076] In this embodiment, each switching circuit 30 further includes a counter and a comparison circuit. The first input terminal of the comparison circuit is used to receive a grayscale value. The second input terminal of the comparison circuit is connected to the output terminal of the counter. The output terminal of the comparison circuit is connected to the gate terminal of the fourth MOS transistor. An M-bit counter is used to count the charging or discharging time from 0 to 2 M -1, where M is an integer greater than 0. As Figure 4 shown, when the counter counts from 0 to the grayscale value corresponding to the pixels in a certain column, the fourth MOS transistor in the switching circuit 30 corresponding to the pixels in that column is controlled to turn off by the control signal output by the corresponding comparison circuit. At this time, the loop is disconnected and no current flows through, thereby stopping the discharge of the load capacitor, and the voltage of the load capacitor is fixed. Here, the grayscale value is pixel data. For example, for a display with a color depth of 10, the pixel data is 10’h200, etc.

[0077] Combined with FIGS. 5 to Figure 7 shown, the sampling and detection circuit includes a detection resistor R, a plurality of calibration circuits, and at least one detection circuit. Among them, each calibration circuit is connected to a voltage source or grounded (GND) through the detection resistor R, and a detection point P is formed. Each calibration circuit is used to receive the capacitance voltage on the load capacitor and the target voltage, and selectively convert the capacitance voltage on the corresponding load capacitor into a sampling current or convert the target voltage into a comparison current and input it into the detection resistor. The detection circuit is used to generate a mirror current calibration signal according to the magnitudes of the sampling voltage generated by the sampling current on the detection resistor R and the comparison voltage generated by the comparison current on the detection resistor R in the calibration_mode0 mode, and generate a load capacitor calibration signal according to the magnitudes of the sampling voltage generated by the sampling current on the detection resistor R and the comparison voltage generated by the comparison current on the detection resistor R in the calibration_mode1 mode.

[0078] In specific implementation, in the calibration_mode0 mode, first, a full row of pixel data is sent. Among them, the pixel data of the first pixel column is 10’h200, and the pixel data of other columns is 10’h000, to determine the discharge or charge time of the load capacitance. Among them, the most significant bit of the pixel data of the first pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0. The detection circuit will obtain the sampling voltage Cal_Vdata generated by the calibration circuit corresponding to the first pixel column through the detection resistor R; then, a full row of pixel data is sent again. The pixel data of the second pixel column is 10’h200, and the pixel data of other pixel columns is 10’h000. Among them, the most significant bit of the pixel data of the second pixel column is configured as 1, and each bit of the pixel data of other columns is configured as 0. The detection circuit will obtain the sampling voltage Cal_Vdata generated by the calibration circuit of the second pixel column through the detection resistor R; repeating the above process, the sampling voltage Cal_Vdata corresponding to all pixel columns can be obtained to confirm the difference between pixel columns.

[0079] Based on the pixel column with the minimum or maximum sampling voltage Cal_Vdata, the pixel data 10’h300 is selected to determine the charge or discharge time of the load capacitance for subsequent calibration. Selecting a relatively large value such as 10’h300 for the pixel data can reduce the calibration error. Obtain the sampling voltage Cal_Vdata of the pixel column with the slowest discharge or charge, and detect whether the sampling voltage Cal_Vdata is equal to the comparison voltage Vdata_p corresponding to the pixel data 10’h300. If they are equal, save the current configuration for this charge or discharge; otherwise, continue to adjust the reference current I through the detection circuit to generate a mirror current calibration signal REF , and continuously send the pixel data 10’h300 for detection until the obtained sampling voltage Cal_Vdata is equal to the comparison voltage Vdata_p, and save the current configuration for charge or discharge at this time. The current configuration for charge or discharge obtained here is used as the current for charge or discharge of the display screen for the displayed image.

[0080] In the calibration_mode1 mode, use the adjusted charging or discharging current above, and then send a full line of pixel data, where the pixel data of the first pixel column is 10’h300, and the pixel data of other columns is 10’h000. The detection circuit will obtain the sampling voltage Cal_Vdata corresponding to the first pixel column, and will compare the sampling voltage Cal_Vdata with the comparison voltage Vdata_p. If it is too small or too large, a load capacitance calibration signal will be generated to increase the configuration value of the compensation capacitance of the load capacitance of the first pixel column by 1. Repeat this process until the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p. At this time, the configuration value of the compensation capacitance of the load capacitance of the first column is the final configuration value of the compensation capacitance of this pixel column. Then repeat the above steps to obtain the final configuration value of the compensation capacitance of each pixel column.

[0081] In this embodiment, all pixel columns share a detection circuit. Of course, in other embodiments, a corresponding detection circuit can also be set separately for each pixel column, which can be set according to actual requirements.

[0082] Combined with Figure 6 and Figure 7 As shown, the calibration circuit includes a fifth MOS transistor T, a first switch K1, a second switch K2, and a third switch K3. Among them, the fifth MOS transistor T is connected in series with the detection resistor R between the reference voltage source V H and the ground (GND). One end of the first switch K1 is connected to the calibration voltage Vcal, and the opposite end is connected to the gate terminal of the fifth MOS transistor T. One end of the second switch K2 is connected to the capacitance voltage Vdata of the load capacitance, and the opposite end is connected to the gate terminal of the fifth MOS transistor T. One end of the third switch K3 is connected to the reference voltage source V H , and the opposite end is connected to the gate terminal of the fifth MOS transistor T.

[0083] In specific implementation, at the beginning of the detection, the first switch K1 is closed, and the second switch K2 circuit and the third switch K3 are opened, so that the calibration voltage Vcal can be input into the calibration circuit; in the subsequent detection, the first switch K1 and the third switch K3 are opened, and the second switch K2 is closed, so that the capacitance voltage Vdata of the pixel circuit can be input into the calibration circuit.

[0084] In this embodiment, the first switch K1, the second switch K2, and the third switch K3 can be controlled to be turned on or off through the switch control circuit (Control) shown in the figure. The switch control circuit here is a simple logic circuit composed of gate-level circuits, with its inputs being calibration_mode0, calibration_mode1, and data[M], and the output control signals being Q1, Q2, and Q3. Q1, Q2, and Q3 can respectively control the closing or opening of the first switch K1, the second switch K2, and the third switch K3. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit of the grayscale value of the pixels in this column (M is the color depth of the grayscale).

[0085] The relationships between calibration_mode0, calibration_mode1, data[M] and the first switch K1, the second switch K2, and the third switch K3 are shown in the following table.

[0086]

[0087] Furthermore, taking the color depth of 10 and compensating the first pixel column as an example, how the sampling detection circuit conducts detection will be described in detail.

[0088] First, configure calibration_mode0 and calibration_mode1 to 1 and 0 respectively. Then, receive a whole row of pixel data, where the pixel data of the first column is 10’h200 (it is necessary to ensure that the highest bit is 1), and the pixel data of other columns is 10’h000. Under the control of the switch control circuit (Control), the first switch K1 corresponding to the first pixel column is closed, the second switch K2 and the third switch K3 are open, and the gate terminal of the fifth MOS transistor T is connected to the calibration voltage Vcal. At this time, the calibration voltage Vcal will generate a first current I1 from the source terminal S to the drain terminal D of the fifth MOS transistor T, and the first current I1 will flow through the resistor R. Since data[M] corresponding to other pixel columns is 0, the third switch K3 is closed, the first switch K1 and the second switch K2 are open, and no current is generated in the fifth MOS transistor T. Therefore, only the first current I1 flows through the detection resistor R. At this time, the voltage at the detection point P detected by the detection circuit represents the calibration voltage Vcal, and the converted data is the comparison voltage Vdata_p corresponding to the first pixel column.

[0089] Secondly, configure calibration_mode0 and calibration_mode1 to 0 and 1 respectively. Then, receive a whole line of pixel data, where the pixel data in the first column is 10’h300, and the pixel data in other columns is 10’h000. Under the control of the switch control circuit (Control), the second switch K2 is closed, the first switch K1 and the third switch K3 are opened, and the gate terminal of the fifth MOS transistor T is connected to the capacitance voltage Vdata of the load capacitor. The voltage of the capacitance voltage Vdata depends on the pixel data corresponding to the input of the first pixel column. At this time, the capacitance voltage Vdata of the load capacitor will generate a second current I1' from the source terminal S to the drain terminal D of the fifth MOS transistor T, and the second current I1' will flow through the detection resistor R. Since the data[M] corresponding to other pixel columns is 0, therefore, the third switch K3 is closed, the first switch K1 and the second switch K2 are opened, and the fifth MOS transistor T does not generate current. Thus, only the second current I1' flows through the detection resistor R. At this time, the voltage at the detection point P detected by the detection circuit represents the capacitance voltage Vdata of the first pixel column, and the converted data is the sampling voltage Cal_Vdata corresponding to the first pixel column.

[0090] Finally, determine whether the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p, and adjust the load capacitor according to the determination result. That is, for the circuit that uses the discharge method to make the load capacitor reach the target voltage, if the sampling voltage Cal_Vdata is less than the comparison voltage Vdata_p, the configuration value of the load compensation capacitor for the first pixel column is incremented by 1. That is, for the circuit that uses the charging method to make the load capacitor reach the target voltage, if the sampling voltage Cal_Vdata is greater than the comparison voltage Vdata_p, the configuration value of the load compensation capacitor for the first pixel column is incremented by 1.

[0091] Repeat the above process until the sampling voltage Cal_Vdata is the same as the comparison voltage Vdata_p. At this time, the actual load capacitor of the first pixel column is equal to the original load capacitor plus the compensated capacitor. The configuration values of the load compensation capacitors for the remaining pixel columns are obtained in the same way and stored in the memory. When the chip is powered on and started, the charge and discharge current configurations and the load compensation capacitor configuration values are loaded.

[0092] As Figure 1 described, each capacitance compensation circuit 40 corresponds to a load capacitor. The capacitance compensation circuit is connected to the connection point A. The capacitance compensation circuit compensates the load capacitor based on the load capacitor calibration signal so that the corresponding capacitance voltage can be obtained based on the mirror current I through the compensated load capacitor.

[0093] As Figure 8As described above, the capacitance compensation circuit includes a compensation control circuit, a switching unit, and a compensation capacitor array. The compensation capacitor array is connected to connection point A through the switching unit. The compensation control circuit generates a load capacitance compensation control signal based on the load capacitance calibration signal to control the on and off of the switching unit, so as to control the compensation capacitors in the compensation capacitor array that are connected to connection point A.

[0094] The compensation capacitor array includes a plurality of compensation capacitors C11, C12, C13~C1n, and the switching unit includes a plurality of switches K11, K12, K13~K1n. Each switch is turned on and off based on the control of the corresponding load capacitance compensation control signal. Each compensation capacitor is connected to connection point A through the corresponding switch. The switching unit further includes a main switch K10 that is turned on and off under the control of the load capacitance compensation control signal. Each switch is connected to connection point A through the main switch. In other embodiments, the main switch K10 may not be provided.

[0095] The values of the compensation capacitors C11, C12, C13~C1n may be the same or different, and the number of closed switches K11, K12, K13~K1n can obtain different sizes of compensation capacitors. When it is detected that the sampled voltage Cal_Vdata is not equal to the comparison voltage Vdata_p and a load capacitance calibration signal is generated, that is, when compensation is required, the compensation control circuit generates a corresponding load capacitance compensation control signal. The main switch K10 is closed under the load capacitance compensation control signal. When the switch K11 is closed under the corresponding load capacitance compensation control signal, the load capacitance is compensated by the compensation capacitor C11, that is, the compensated load capacitance can be considered as the compensation capacitor C11 plus the load capacitance in the original circuit. When the switch K12 is closed, the load capacitance is compensated by the compensation capacitor C12.

[0096] It can be seen that the load capacitance compensation control signals for controlling the switches K11, K12, K13~K1n can be a string of digital values such as a combination of 1 and 0, so as to control the on and off of the switches K11, K12, K13~K1n. This string of digital values is the load compensation capacitor configuration value. For example, if it is desired to compensate with the compensation capacitors C11 and C12, the signals for controlling the switches K11 and K12 are 1, and the signals for the remaining control switches are 0. If it is necessary to add the compensation capacitor C13 for compensation, the signal for controlling the switch K13 becomes 1, that is, the load compensation capacitor configuration is incremented by 1.

[0097] Taking two embodiments as examples below, the charging and discharging parts of the charging and discharging compensation circuit described in the present invention will be described in detail.

[0098] Embodiment 1

[0099] As Figure 2As shown, the charge and discharge compensation circuit includes n preprocessing circuits 10, n switching circuits 30, and the current mirror circuit 20 has n output branches. Among them, the first MOS transistor in the preprocessing circuit 10 is a PMOS transistor, the second MOS transistor and the third MOS transistor in the current mirror circuit 20 are both NMOS transistors, and the fourth MOS transistor in the switching circuit 30 is an NMOS transistor. Among them, the source terminal of each first MOS transistor (denoted as T11 to Tn1) is connected to the reference voltage source V H , the drain terminal is connected to the corresponding load capacitor (denoted as C1 to Cn) to form a connection point A, and the gate terminal is connected to the control signal S0; the drain terminal of the second MOS transistor (denoted as T0) is connected to the reference current source I bias , the source terminal is grounded, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS transistor (denoted as T13 to Tn3) serves as an output branch, the source terminal is grounded, and the gate terminal is connected to the gate terminal of the second MOS transistor; the source terminal of each fourth MOS transistor (denoted as T12 to Tn2) is connected to the drain terminal of the corresponding third MOS transistor, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signal (denoted as S1 to Sn).

[0100] In specific implementation, after the start of a row time, the control signal S0 controls all the first MOS transistors (T11 to Tn1) to conduct. At the same time, the control signals (S1 to Sn) control the corresponding fourth MOS transistors (T12 to Tn2) to turn off. For example, the control signal S1 controls the fourth MOS transistor T12 to turn off. At this time, the voltage values of all the load capacitors (C1 to Cn) are increased to the high-voltage reference voltage value V H .

[0101] Furthermore, the control signal S0 controls all the first MOS transistors to turn off. At the same time, the control signals (S1 to Sn) control the corresponding fourth MOS transistors (T12 to Tn2) to conduct, and the charge and discharge compensation circuit starts to discharge. At this time, the current mirror circuit 20 can mirror a mirror current I in each output branch, and the mirror current I is proportional to the reference current I REF . In specific implementation, the aspect ratio of the width to length of the second MOS transistor and the third MOS transistor can be adjusted to control the proportional relationship between the mirror current I and the reference current I REF , and then a current with a suitable magnitude can be selected according to actual needs.

[0102] Furthermore, the discharge time of the load capacitor is controlled by a counting method. For example, an M-bit counter is used to count the discharge time from 0 to 2 M -1, and M is an integer greater than 0. For example Figure 4As shown, when the counter counts from 0 to the gray scale value corresponding to a certain pixel column, the fourth MOS transistor in the switch circuit corresponding to the pixels in this column is controlled to be turned off by the corresponding control signal. At this time, the loop is disconnected and no current flows through, and thus the discharge of the load capacitor stops, and the capacitance voltage of the load capacitor is fixed. The capacitance voltage at this time is the capacitance voltage corresponding to the gray scale value of this column of pixels, and this voltage will be stored by the load capacitor. After the load capacitors of all columns are discharged, they will be written into the pixel driving circuit of a certain row together. The gray scale value here is pixel data.

[0103] Embodiment 2

[0104] As Figure 3 shown, different from Embodiment 1, the first MOS transistor of the preprocessing circuit 10 is an NMOS transistor, the second and third MOS transistors in the current mirror circuit 20 are both PMOS transistors, and the fourth MOS transistor in the switch circuit 30 is a PMOS transistor. Among them, the source terminal of each first MOS transistor is connected to the reference voltage source V L , the drain terminal is connected to the load capacitor to form a connection point A, and the gate terminal is connected to the control signal S0; the drain terminal of the second MOS transistor is connected to the reference current I REF , the source terminal is connected to the voltage VDD, and the gate terminal is connected to the drain terminal; the drain terminal of each third MOS transistor is used as the output branch, the source terminal is connected to the voltage VDD, and the gate terminal is connected to the gate terminal of the second MOS transistor; the source terminal of each fourth MOS transistor T12~Tn2 is connected to the drain terminal of the third MOS transistor, the drain terminal is connected to the connection point A, and the gate terminal is connected to the corresponding control signals S1~Sn.

[0105] In specific implementation, after the start of the time of a row, the control signal S0 controls all the first MOS transistors T11~Tn1 to be turned on. At the same time, the control signals S1~Sn control the corresponding fourth MOS transistors T12~Tn2 to be turned off. At this time, the voltage values of all load capacitors are adjusted to the low-voltage reference voltage value V L .

[0106] Further, the control signal S0 controls all the first MOS transistors to be turned off. At the same time, the control signals S1~Sn control the corresponding fourth MOS transistors T12~Tn2 to be turned on, and the charge-discharge compensation circuit starts to charge. At this time, the current mirror circuit 20 can mirror an image current I in each output branch, and the image current I is proportional to the reference current I REF .

[0107] Further, the charging time of the load capacitor is controlled by a counting method. For example, an M-bit counter is used to count the charging time from 0 to 2 M -1, where M is an integer greater than 0. As Figure 4As shown, when the counter counts from 0 to the gray scale value corresponding to the pixels in a certain column, where the gray scale value is pixel data, the fourth MOS transistor in the switching circuit corresponding to this column is controlled to be turned off by the corresponding control signal. At this time, the loop is disconnected and no current flows through, thus stopping the charging of the load capacitor, and the voltage of the load capacitor is fixed. The voltage at this time is the voltage corresponding to the gray scale value of the pixels in this column, and this voltage will be stored by the load capacitor. After all the load capacitors of all columns are charged, they will be written into the pixel driving circuit of a certain row together.

[0108] In this embodiment, the charging and discharging of the capacitive load can be realized through the above specific circuit. Of course, in other embodiments, the charging and discharging of the capacitive load can also be realized in other ways.

[0109] Based on the above circuit, the present invention also discloses a charging and discharging compensation method for a charging and discharging compensation circuit, including:

[0110] Adjust the voltage of the corresponding load capacitor to a preset value through each preprocessing circuit 10.

[0111] Mirror the reference current I through the current mirror circuit 20 REF and output the mirrored current I through at least one output branch to charge or discharge the load capacitor.

[0112] Control the preprocessing circuit to adjust the voltage of the corresponding load capacitor to the preset value and control the charging or discharging time of the load capacitor through the switching circuit 30.

[0113] Generate a mirror current calibration signal for adjusting the reference current based on the magnitude relationship between the capacitor voltage on the load capacitor and the target voltage in the first mode through the sampling detection circuit 40, and generate a load capacitor calibration signal based on the magnitude relationship between the capacitor voltage on the load capacitor and the target voltage in the second mode through the sampling detection circuit 40; specifically, first, in the first mode, select a target voltage from the ramp voltage and sample the target voltage to obtain a comparison voltage. In one embodiment, the ramp voltage can be evenly divided into 2 M parts, where M is the display color depth; when discharging, select the voltage close to the minimum value in the ramp voltage as the target voltage, and when charging, select the voltage close to the maximum value in the ramp voltage as the target voltage.

[0114] Secondly, set the discharge or charge time, sample the capacitance voltage on the load capacitance after discharging or charging the selected pixel columns to obtain a sampled voltage, generate a mirror current calibration signal for adjusting the reference current based on the magnitude between the sampled voltage and the comparison voltage, and calibrate the mirror current by adjusting the reference current. In one embodiment, set the discharge time and discharge each pixel column starting from the maximum value in the ramp voltage, or set the charge time and charge each pixel column starting from the minimum value in the ramp voltage, and determine the pixel column with the slowest discharge or charge. In one embodiment, an M-bit counter can be used to count the charge or discharge time from 0 to 2 M -1, and end the discharge or charge when the counter counts from zero to the grayscale value corresponding to a column of pixels, thereby setting the charge or discharge time. M is the display color depth and M is an integer greater than 0.

[0115] In the second mode, sample the capacitance voltage generated on the load capacitance of each pixel column based on the calibrated mirror current to obtain a corresponding sampled voltage; determine the load capacitance calibration signals corresponding to the remaining pixel columns based on the magnitude between the sampled voltage and the comparison voltage.

[0116] Compensate the load capacitance through a capacitance compensation circuit based on the load capacitance calibration signal to obtain a corresponding capacitance voltage based on the mirror current through the compensated load capacitance. In one embodiment, if the sampled voltage is less than the comparison voltage, the output load capacitance calibration signal controls the capacitance compensation circuit to compensate the load capacitance, so that a compensation capacitance can be added to the original load capacitance.

[0117] The following details how to perform compensation separately for the discharge and charge processes. <{

[0118] (1) Discharge process

[0119] As Figure 9 shown, it is a schematic diagram of the ramp voltage, which can be expressed by the following formula:

[0120] V data =V H -(I L / C L )*t, that is, C L =I L *t / (V H -V data );

[0121] where t is T*P W , T is the number of clock cycles, the range is the counting range 0~2 M -1 of the counter, P W is the cycle time length; C L is the load capacitance; V datais the capacitance voltage on the load capacitance; I L is the pixel column discharge current; V H is the reference voltage value, and C can be obtained when all parameters are fixed L .

[0122] The discharge currents I of different pixel columns L are not equal, so the load capacitance C cannot be directly obtained by calculation L . However, the load capacitance C after pixel column compensation L , can be determined by inputting the test pixel gray scale value to determine the discharge time and detecting the compensated capacitance voltage. C L +△C max corresponds to the load capacitance after compensation of the pixel column with the fastest discharge, and C L +△C k is the load capacitance after compensation of any pixel column

[0123] In specific implementation, the preprocessing circuit 10 will first adjust each load capacitance to a preset value, that is, adjust it to the reference voltage value V H . To achieve compensation for the discharge process, the present invention first selects a target voltage Vcal between the reference voltage values V H and V L . The target voltage Vcal here can be selected in the following way: Divide the voltage between V L and V H into 2 M parts, corresponding to pixel gray scale values from 2 M -1 to 0. Among them, V H corresponds to the minimum pixel gray scale value 0, and V L corresponds to the maximum pixel gray scale value 2 M -1

[0124] For the pixel points on any pixel column, the corresponding gray scale value formula G k =(2 M -1)*(I L / C L )*tk0 / (V H -V L ). G k is the gray scale value of the pixel points on any pixel column, t k0 is the corresponding discharge time of the pixel points on any pixel column, I L is the actual discharge current of any pixel column, and C L is the actual load capacitance of any pixel column

[0125] In this embodiment, in order to achieve better calibration accuracy, reuse the Latch circuit, and ensure that all pixel columns with the largest differences can be covered during calibration, the target voltage Vcal is preferably selected to be close to the voltage V L .

[0126] Further, after the target voltage Vcal is selected, all pixel columns are discharged in sequence, and the discharge time is (2 M - 1)*(V H - Vcal) / (V H - V L ) clock cycles. When the discharge time ends, the pixel column with the slowest discharge is determined. During specific implementation, the pixel column with the slowest discharge can be determined through a detection circuit. For example, the detection circuit determines whether the pixel column is discharged to the target voltage Vcal to determine whether it is the pixel column with the slowest discharge, and so on.

[0127] After the pixel column with the slowest discharge is determined, the reference current I REF of the current mirror circuit 20 is further adjusted. By changing the reference current I REF , the mirror current mirrored and output by the current mirror circuit 20 in this pixel column is changed. At the same time, this pixel column is discharged, and the discharge time is (2 M - 1)*(V H - Vcal) / (V H - V L ) clock cycles. Meanwhile, it is judged whether the capacitance voltage V data of this pixel column is the same as the target voltage Vcal. If the capacitance voltage V data of this pixel column is the same as the target voltage Vcal, the calibration is completed, and the current reference current I REF is the calibrated reference current. At this time, the configuration parameters of the current reference current I REF are stored to facilitate subsequent calibration of other pixel columns using the reference current I REF . If the capacitance voltage V data of this pixel column is not the same as the target voltage Vcal, the reference current I REF of the current mirror circuit 20 is continuously adjusted until its capacitance voltage V L data is the same as the target voltage Vcal when discharging for (2 M - 1)*(V H - Vcal) / (V H - V L ) clock cycles.

[0128] Further, after calibrating the pixel column with the slowest discharge time, the compensation capacitors corresponding to the remaining pixel columns are determined based on the discharge current of the pixel column with the slowest discharge. Specifically, in implementation, the compensation capacitors corresponding to the remaining pixel columns can be obtained through the following method:

[0129] As can be seen from the above and combined with Figure 9 shown, the time taken for the pixel column with the slowest discharge to discharge from voltage V H to Vcal is (2 M -1)*(V H -Vcal) / (V H -V L ) clock cycles, and the load capacitance of the corresponding pixel column is C L =(2 M -1)*P w *I L / (V H -V L ). For the first pixel column in the remaining pixel columns, it discharges from V H to Vcal, where the discharge time (2 M -1)*(V H -Vcal) / (V H -V L ) is fixed and the discharge current I L is also fixed. Adjust the compensation capacitance value △C of the capacitance compensation circuit so that the capacitance voltage V data of the pixel column corresponds to the target voltage Vcal. If the capacitance voltage V data of this pixel column corresponds to the target voltage Vcal, stop the detection and save the load compensation capacitance configuration value of the capacitance compensation circuit at this time; otherwise, continue to change the load compensation capacitance configuration value of the capacitance compensation circuit until the capacitance voltage V data of this pixel column corresponds to the target voltage Vcal, stop the detection, and save the load compensation capacitance configuration value of the capacitance compensation circuit at this time. The finally actual load capacitance of the corresponding pixel column at this time is the load capacitance C L of this pixel column plus the compensation capacitance △C of the capacitance compensation circuit corresponding to this pixel column. And so on, the load compensation capacitance configuration values of the capacitance compensation circuits corresponding to the remaining pixel columns are obtained in the same way.

[0130] As described above, the capacitance compensation circuit consists of N parallel compensation capacitors, each with an individual switch control. The capacitance values of the compensation capacitors can be the same or different. The compensation capacitors and the load capacitor are connected in parallel to the charge and discharge compensation circuit. When the pixel column does not require capacitance compensation, the main switch is turned off; when the pixel column requires capacitance compensation, the main switch is turned on, and the control switches in the capacitance compensation circuit are turned on or off according to the configured value of the load compensation capacitor. The configured value of the load compensation capacitor is stored in the memory and loaded after the display is powered on to improve the display effect of the display.

[0131] (2) Charging process

[0132] As Figure 10 shown, it is a schematic diagram of a ramp voltage, which can be expressed by the following formula:

[0133] V data = V L + (I L / C L ) * t, that is, C L = I L * t / (V data - V L );

[0134] Among them, t is T * P W , T is the number of clock cycles, and the range is the counting range of the counter 0 to 2 M - 1, P W is the cycle time length; C L is the load capacitor; V data is the capacitor voltage on the load capacitor; I L is the pixel column charging current; V L is the reference voltage value, and C L can be obtained when all parameters are fixed.

[0135] The charging currents I L of different pixel columns are not equal, so the load capacitor C L cannot be directly obtained by calculation. However, the load capacitor C L after pixel column compensation can be determined by inputting the test pixel gray scale value to determine the charging time and detecting the capacitor voltage after compensation. C L + △C max corresponds to the load capacitor after compensation of the pixel column with the fastest charging speed, and C L + △C k is the load capacitor after compensation of any pixel column.

[0136] In specific implementation, the preprocessing circuit 10 will first adjust each load capacitor to a preset value, that is, adjust it to the voltage V L, in order to achieve compensation for the charging process, the present utility model first selects a target voltage Vcal between voltages V H and V L . The target voltage Vcal here can be selected in the following way: divide the voltage between V L and V H into 2 M equal parts, corresponding to pixel gray values from 2 M -1 to 0. Among them, V L corresponds to the minimum pixel gray value of 0, and V H corresponds to the maximum pixel gray value of 2 M -1.

[0137] In this embodiment, in order to achieve better calibration accuracy, reuse the Latch circuit, and ensure that all pixel columns can be calibrated with the maximum difference covered, the target voltage Vcal is preferably selected at a point close to voltage V H .

[0138] Further, after the target voltage Vcal is selected, all pixel columns are charged in sequence, and the charging time is (2 M -1)*(Vcal - V L ) / (V H - V L ) clock cycles (Clock Cycle). When the charging time ends, determine the pixel column with the slowest charging. In specific implementation, the pixel column with the slowest charging can be determined through a detection circuit, such as the detection circuit determines whether the pixel column is charged to the target voltage Vcal to determine whether it is the pixel column with the slowest charging, etc.

[0139] Further, after determining the pixel column with the slowest charging, further adjust the reference current I REF of the current mirror circuit 20. By changing the reference current I REF , change the mirror current mirrored and output by the current mirror circuit 20 in this pixel column. At the same time, charge this pixel column, and the charging time is (2 M -1)*(Vcal - V L ) / (V H - V L ) clock cycles. Meanwhile, judge whether the capacitor voltage V data of this pixel column is the same as the target voltage Vcal. If the capacitor voltage V data of this pixel column is the same as the target voltage Vcal, then the current reference current I REF is the calibrated reference current. At this time, store the configuration parameters of the current reference current I REF for subsequent use of this reference current I REFCalibrate other pixel columns. If the capacitance voltage V of this pixel column data is not the same as the target voltage Vcal, continue to adjust the reference current I of the current mirror circuit 20 REF , until its capacitance voltage V M is the same as the target voltage Vcal after charging for (2 L -1)*(Vcal-V H ) / (V L ) clock cycles. data

[0140] Furthermore, after calibrating the pixel column with the slowest charging time, determine the compensation capacitors corresponding to the remaining pixel columns based on the charging current of this pixel column with the slowest charging time. Specifically, in implementation, the compensation capacitors corresponding to the remaining pixel columns can be obtained through the following method:

[0141] As can be seen from the above and combined with Figure 10 shown, the time taken for the pixel column with the slowest charging time to charge from voltage V L to Vcal is (2 M -1)*(Vcal-V L ) / (V H -V L ) clock cycles, and the load capacitance of the corresponding pixel column is C L =(2 M -1)*P w *I L / (V H -V L ). For the first pixel column in the remaining pixel columns, it charges from V L to Vcal, where the charging time (2 M -1)*(Vcal-V L ) / (V H -V L ) is fixed and the charging current I L is also fixed. Adjust the compensation capacitance value △C of the capacitance compensation circuit so that the capacitance voltage V data of the pixel column corresponds to the target voltage Vcal. If the capacitance voltage V data of this pixel column corresponds to the target voltage Vcal, stop the detection and save the load compensation capacitance configuration value of the capacitance compensation circuit at this time; otherwise, continue to change the load compensation capacitance configuration value of the capacitance compensation circuit until the capacitance voltage V data of this pixel column corresponds to the target voltage Vcal, stop the detection, and save the load compensation capacitance configuration value of the capacitance compensation circuit at this time. The finally actual load capacitance of the corresponding pixel column at this time is the load capacitance C L ​Add the compensation capacitor △C of the capacitor compensation circuit corresponding to this pixel column. And so on, the load compensation capacitor configuration values of the capacitor compensation circuits corresponding to the remaining pixel columns are obtained in the same way.

[0142] As can be seen from the above, the capacitor compensation circuit is composed of N parallel compensation capacitors, each compensation capacitor has a separate switch control, the capacitance values of the compensation capacitors can be the same or different, and the compensation capacitors and the load capacitors are connected in parallel to the charge and discharge compensation circuit. When the pixel column does not require capacitor compensation, the main switch is disconnected; when the pixel column requires capacitor compensation, the main switch is closed, and the control switches in the capacitor compensation circuit are determined to be disconnected or closed according to the load compensation capacitor configuration value. The load compensation capacitor configuration value is stored in the memory and is loaded after the display is powered on to improve the display effect of the display.

[0143] The present utility model also discloses a display screen, which has the charge and discharge compensation circuit described above, and can charge or discharge the load capacitors in the pixel circuits of all columns in the same row, so that the voltage values of the load capacitors meet the actual use requirements, and the charging or discharging of the load capacitors in each column of pixel circuits is independent of each other and does not interfere with each other. The display screen here includes but is not limited to OLED / LED / LCD / LCOS / MICRO-LED / MICRO-OLED display screens.

[0144] At the same time, the present utility model also discloses an electronic device, which has the display screen described above, and can charge or discharge the load capacitors in the pixel circuits of all columns in the same row in a short time, so that the voltage values of the load capacitors meet the actual use requirements, and the charging or discharging of the load capacitors in each column of pixel circuits is independent of each other and does not interfere with each other. The electronic device here includes but is not limited to smart phones, tablet computers, laptop computers, televisions, desktop monitors, VR / AR / MR / XR, HUD devices.

[0145] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, in any regard, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed by the present utility model. Any reference signs in the claims should not be regarded as limiting the claimed rights.

[0146] In addition, it should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A charge and discharge compensation circuit, characterized in that including at least one load capacitor; at least one preprocessing circuit, each of the preprocessing circuits corresponding to one of the load capacitors, the preprocessing circuit being connected to the corresponding load capacitor to form a connection point, the preprocessing circuit being configured to adjust the voltage of the corresponding load capacitor to a preset value; a current mirror circuit configured to mirror a reference current and output a mirror current for charging or discharging the load capacitor through at least one output branch, each of the output branches corresponding to one of the connection points; at least one switching circuit, each of the switching circuits corresponding to one of the output branches, each of the output branches being connected to the corresponding connection point through the corresponding switching circuit, the switching circuit being configured to control the preprocessing circuit to adjust the voltage of the corresponding load capacitor to the preset value and the charging or discharging time of the load capacitor; a sampling and detection circuit configured to generate a mirror current calibration signal for adjusting the reference current based on the magnitude relationship between the capacitance voltage on the load capacitor and the target voltage in the first mode, and generate a load capacitor calibration signal based on the magnitude relationship between the capacitance voltage on the load capacitor and the target voltage in the second mode; at least one capacitance compensation circuit, each of the capacitance compensation circuits corresponding to one of the load capacitors, the capacitance compensation circuit being connected to the connection point, the capacitance compensation circuit compensating the load capacitor based on the load capacitor calibration signal so that the compensated load capacitor obtains a corresponding capacitance voltage based on the mirror current.

2. The charge and discharge compensation circuit according to claim 1, wherein Each of the preprocessing circuits is controlled by the same control signal to adjust the voltage of the corresponding load capacitor to the preset value.

3. The charge and discharge compensation circuit according to claim 1, characterized in that The preprocessing circuit includes: a first MOS transistor, the source terminal thereof being connected to a reference voltage source or ground, the drain terminal thereof being connected to the load capacitor to form the connection point, and the gate terminal thereof being connected to the control signal.

4. The charge and discharge compensation circuit according to claim 1, characterized in that, The current mirror circuit includes: a second MOS transistor, the drain terminal thereof being connected to a reference current source, the source terminal thereof being connected to a voltage source or ground, and the gate terminal thereof being connected to the drain terminal; at least one third MOS transistor, the drain terminal of each third MOS transistor serving as an output branch, the source terminals thereof being commonly connected to a voltage source or ground, and the gate terminals thereof being connected to the gate terminal of the second MOS transistor.

5. The charge-discharge compensation circuit according to claim 1, wherein The switching circuit includes: a fourth MOS transistor, the source terminal thereof being connected to the output branch, the drain terminal thereof being connected to the connection point, and the gate terminal thereof being connected to the control signal.

6. The charge and discharge compensation circuit according to claim 1, characterized in that, The sampling and detection circuit includes: a detection resistor; a plurality of calibration circuits, each calibration circuit corresponding to one pixel column, and each calibration circuit being connected to a voltage source or grounded through the detection resistor to form a detection point, each calibration circuit being configured to receive the capacitance voltage and the target voltage on the load capacitor and selectively convert the capacitance voltage on the corresponding load capacitor into a sampling current or convert the target voltage into a comparison current and input the same into the detection resistor; at least one detection circuit configured to generate a mirror current calibration signal according to the magnitudes of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor in the first mode, and generate a load capacitor calibration signal according to the magnitudes of the sampling voltage generated by the sampling current in the detection resistor and the comparison voltage generated by the comparison current in the detection resistor in the second mode.

7. The charge and discharge compensation circuit according to claim 6, wherein All pixel columns share one detection circuit.

8. The charge and discharge compensation circuit according to claim 6, wherein The calibration circuit includes: A fifth MOS transistor, connected in series with the detection resistor between the voltage source and the ground; A first switch, one end connected to the reference voltage, and the opposite end connected to the gate terminal of the fifth MOS transistor; A second switch, one end connected to the capacitance voltage on the load capacitor, and the opposite end connected to the gate terminal of the fifth MOS transistor; A third switch, one end connected to the voltage source, and the opposite end connected to the gate terminal of the fifth MOS transistor; A switch control circuit, connected to the first switch, the second switch, and the third switch, for controlling the closing or opening of the first switch, the second switch, and the third switch.

9. The charge-discharge compensation circuit according to claim 8, wherein, The switch control circuit is a logic circuit composed of gate-level circuits, with inputs calibration_mode0, calibration_mode1, and data[M], and outputs Q1, Q2, Q3. The Q1, Q2, and Q3 respectively control the closing or opening of the first switch, the second switch, and the third switch. Among them, calibration_mode0 and calibration_mode1 are configurable 2-bit registers, and data[M] is the highest bit value of the grayscale value corresponding to the pixel column.

10. The charge and discharge compensation circuit according to claim 1, wherein The switch circuit for controlling the charging or discharging time of the load capacitor includes: During charging or discharging, the M-bit counter counts the charging or discharging time from 0 to 2 M -1, and when the counter counts from zero to the gray value corresponding to a column of pixels, the switching circuit corresponding to that column of pixels is turned off. M is the color depth of the display and M is an integer greater than 0.

11. The charge and discharge compensation circuit according to claim 1, wherein The capacitance compensation circuit includes a compensation control circuit, a switch unit, and a compensation capacitor array. The compensation capacitor array is connected to the connection point through the switch unit. The compensation control circuit generates a load capacitor compensation control signal based on the load capacitor calibration signal to control the opening and closing of the switch unit, so as to control the number of compensation capacitors connected to the connection point in the compensation capacitor array.

12. The charge and discharge compensation circuit according to claim 11, wherein The compensation capacitor array includes a plurality of compensation capacitors, and the switch unit includes a plurality of switches. Each switch is opened and closed based on the control of the corresponding load capacitor compensation control signal, and each compensation capacitor is connected to the connection point through the corresponding switch.

13. The charge and discharge compensation circuit according to claim 12, wherein The switch unit further includes a main switch that is opened and closed under the control of the load capacitor compensation control signal, and each of the switches is connected to the connection point through the main switch.

14. A display screen, characterized in that, Including the charge and discharge compensation circuit according to any one of claims 1 to 13.

15. An electronic device, characterized in that, Including the display screen according to claim 14.

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