Semiconductor structure
By designing the non-overlapping projection and insulating layer of the conductor in the semiconductor structure to cover the unconnected area, the problem of short circuit after the conductor is burned is solved, and the risk of device burn is reduced.
Patent Information
- Application Number
- CN202422218234.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-10
- Publication Date
- 2025-07-29
- Estimated Expiration
- 2034-09-10
AI Technical Summary
During the HEMT device testing process, the wire was burned and dropped onto an unconnected electrode pad, causing the device to be short-circuited, which in severe cases caused the device to burn.
The semiconductor structure is designed so that the orthogonal projection of at least one first wire on the substrate does not overlap with the orthogonal projection of the second electrode pad on the substrate, and the orthogonal projection of at least one second wire on the substrate does not overlap with the orthogonal projection of the first electrode pad on the substrate, covering the unconnected area through the insulating layer to avoid falling after the wire is burned and dropped, causing a short circuit.
Reduces the risk of short circuit caused by wires falling on other electrode pads after they are burned, and reduces the possibility of a device burning due to short circuits.
Smart Images
Figure CN223167479U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure. Background Art
[0002] In the related art, a HEMT (High Electron Mobility Transistor) device includes a plurality of source pads, a plurality of drain pads, at least one source electrode, and at least one drain electrode. The source pads are connected to the source electrode through a plurality of wires, and the drain pads are connected to the drain electrode through a plurality of wires. At least two source pads are connected to the same source electrode, and at least two drain pads are connected to the same drain electrode.
[0003] When testing the HEMT, a current is applied to the source electrode and the drain electrode for testing, and the current is transmitted to the source pads and the drain pads through the wires. During the testing process, if a wire is burned out, the burned-out wire falling onto other electrode pads not connected to the wire will cause the device to short-circuit, and in severe cases, the device will be severely burned. Summary of the Utility Model
[0004] An embodiment of this application provides a semiconductor structure. The semiconductor structure includes:
[0005] A substrate;
[0006] A first electrode pad, a second electrode pad, a first electrode, and a second electrode located on one side of the substrate;
[0007] A plurality of wires, including a first wire and a second wire; the first electrode pad is connected to the first electrode through at least one of the first wires, and the second electrode pad is connected to the second electrode through at least one of the second wires; the orthographic projection of at least one of the first wires on the substrate does not overlap with the orthographic projection of the second electrode pad on the substrate, and / or the orthographic projection of at least one of the second wires on the substrate does not overlap with the orthographic projection of the first electrode pad on the substrate.
[0008] In one embodiment, the first electrode pad is connected to the first electrode through a plurality of the first wires, and the orthographic projections of the first wires on the substrate do not overlap with the orthographic projection of the second electrode pad on the substrate; and / or the second electrode pad is connected to the second electrode through a plurality of the second wires, and the orthographic projections of the second wires on the substrate do not overlap with the orthographic projection of the first electrode pad on the substrate.
[0009] In one embodiment, the semiconductor structure includes a central area and a peripheral area, the peripheral area includes a first sub-peripheral area and a second sub-peripheral area located on opposite sides of the central area; the first electrode pad and the second electrode pad are located in the central area; the distance between the first electrode pad and the first sub-peripheral area is smaller than the distance between the second electrode pad and the first sub-peripheral area, and the distance between the first electrode pad and the second sub-peripheral area is greater than the distance between the second electrode pad and the second sub-peripheral area; at least one first electrode is located in the first sub-peripheral area, and at least one second electrode is located in the second sub-peripheral area.
[0010] In one embodiment, in a direction perpendicular to a direction from the first sub-peripheral area to the second sub-peripheral area, the first electrode pads and the second electrode pads are alternately arranged.
[0011] In one embodiment, in the direction from the first sub-peripheral region to the second sub-peripheral region, the distance between the end of the first electrode pad away from the first sub-peripheral region and the end of the second electrode pad away from the second sub-peripheral region is less than or equal to half the size of the first electrode pad; and / or, in the direction from the first sub-peripheral region to the second sub-peripheral region, the distance between the end of the first electrode pad away from the first sub-peripheral region and the end of the second electrode pad away from the second sub-peripheral region is less than or equal to half the size of the second electrode pad.
[0012] In one embodiment, the semiconductor structure includes a central region and a peripheral region, wherein the peripheral region includes a third sub-peripheral region and a fourth sub-peripheral region located on opposite sides of the central region;
[0013] At least one of the first electrodes is located in the third sub-peripheral area, and is connected to the first electrode pad adjacent to the third sub-peripheral area and the first electrode located in the third sub-peripheral area; and / or, at least one of the first electrodes is located in the fourth sub-peripheral area; and is connected to the first electrode pad adjacent to the fourth sub-peripheral area and the first electrode located in the fourth sub-peripheral area.
[0014] In one embodiment, the semiconductor structure further includes an insulating layer, which is located on a side of the first electrode pad and the second electrode pad away from the substrate; the insulating layer covers an area where the first electrode pad is not connected to the first wire; and / or the insulating layer covers an area where the second electrode pad is not connected to the second wire.
[0015] In one embodiment, the semiconductor structure includes a central region and a peripheral region, wherein the peripheral region includes a first sub-peripheral region and a second sub-peripheral region located on opposite sides of the central region, and a third sub-peripheral region and a fourth sub-peripheral region located on opposite sides of the central region;
[0016] The first electrode pad and the second electrode pad are alternately arranged in a direction from the third sub-peripheral area to the fourth sub-peripheral area; the first electrode pad includes a first sub-electrode pad adjacent to the third sub-peripheral area, a second sub-electrode pad adjacent to the fourth sub-peripheral area, and a third sub-electrode pad located between the first sub-electrode pad and the second sub-electrode pad; the first sub-peripheral area, the third sub-peripheral area and the fourth sub-peripheral area are respectively provided with the first electrode, and the second electrode is located in the second sub-peripheral area; the first sub-electrode pad is connected to the first electrode located in the third sub-peripheral area, the second sub-electrode pad is connected to the first electrode located in the fourth sub-peripheral area, and the third sub-electrode pad is connected to the first electrode located in the first sub-peripheral area.
[0017] In one embodiment, the semiconductor structure further includes a gate pad located in the central area and a third electrode located in the first sub-peripheral area, the multiple wires include a third wire, and the gate pad is connected to the third electrode through the third wire; the gate pad is located between the first electrode pad and the first sub-peripheral area; the third electrode and the gate pad are located on the same side of the first electrode in the first sub-peripheral area.
[0018] In one embodiment, the first electrode pad is a source pad, and the second electrode pad is a drain pad; the semiconductor structure also includes a Kelvin source located in the first sub-peripheral region, and in the first sub-peripheral region, the Kelvin source is located on the side of the first electrode facing the third sub-peripheral region; the multiple wires include a fourth wire, and the first sub-electrode pad is connected to the Kelvin source through the fourth wire; the orthographic projection of the fourth wire on the substrate does not overlap with the orthographic projection of the drain pad on the substrate.
[0019] The main technical effects achieved by the embodiments of the present application are:
[0020] In the semiconductor structure provided by the embodiment of the present application, the current applied to the first electrode flows to the first electrode pad through the first wire. When the first wire is burned, since the orthographic projection of at least one first wire on the substrate does not overlap with the orthographic projection of the second electrode pad on the substrate, the risk of the burned first wire falling on the second electrode pad and causing a short circuit in the semiconductor structure can be reduced; the current applied to the second electrode flows to the second electrode pad through the second wire. When the second wire is burned, since the orthographic projection of at least one second wire on the substrate does not overlap with the orthographic projection of the first electrode pad on the substrate, the risk of the burned second wire falling on the first electrode pad and causing a short circuit in the semiconductor structure can be reduced, thereby improving the problem of the device being burned due to a short circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 is a schematic structural diagram of a semiconductor structure provided by an exemplary embodiment of the present application;
[0022] Figure 2 It is a structural schematic diagram of a semiconductor structure provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION
[0023] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
[0024] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.
[0025] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".
[0026] The following embodiments of the present application are described in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.
[0027] The present application embodiment provides a semiconductor structure. Figure 1 As shown, the semiconductor structure includes a substrate 10 , a first electrode pad 30 , a second electrode pad 40 , a first electrode 50 , a second electrode 60 , and a plurality of wires 70 .
[0028] The first electrode pad 30, the second electrode pad 40, the first electrode 50, the second electrode 60, and the plurality of wires 70 are located on one side of the substrate 10. The plurality of wires 70 include a first wire 71 and a second wire 72. The plurality of wires 70 are located on a side of the gate pad 20, the first electrode pad 30, the second electrode pad 40, the first electrode 50, and the second electrode 60 that is away from the substrate 10. The first electrode pad 30 is connected to the first electrode 50 via at least one first wire 71, and the second electrode pad 40 is connected to the second electrode 60 via at least one second wire 72. The orthographic projection of at least one first wire 71 on the substrate 10 does not overlap with the orthographic projection of the second electrode pad 40 on the substrate 10, and / or the orthographic projection of at least one second wire 72 on the substrate 10 does not overlap with the orthographic projection of the first electrode pad 30 on the substrate 10.
[0029] In the semiconductor structure provided by the embodiment of the present application, the current applied to the first electrode flows to the first electrode pad through the first wire. When the first wire is burned, since the orthographic projection of at least one first wire on the substrate does not overlap with the orthographic projection of the second electrode pad on the substrate, the risk of the burned first wire falling on the second electrode pad and causing a short circuit in the semiconductor structure can be reduced; the current applied to the second electrode flows to the second electrode pad through the second wire. When the second wire is burned, since the orthographic projection of at least one second wire on the substrate does not overlap with the orthographic projection of the first electrode pad on the substrate, the risk of the burned second wire falling on the first electrode pad and causing a short circuit in the semiconductor structure can be reduced, thereby improving the problem of the device being burned due to a short circuit.
[0030] In one embodiment, the first electrode pad 30 is connected to the first electrode 50 via a plurality of first wires 71, and the orthographic projections of the first wires 71 on the substrate 10 do not overlap with the orthographic projections of the second electrode pads 40 on the substrate 10. This further reduces the risk of a first wire 71 burning out and falling onto the second electrode pad 40, causing a short circuit in the semiconductor structure.
[0031] In one embodiment, the second electrode pad 40 is connected to the second electrode 60 via a plurality of second wires 72, and the orthographic projections of the second wires 72 on the substrate 10 do not overlap with the orthographic projections of the first electrode pads 30 on the substrate 10. This further reduces the risk of a second wire 72 burning and falling onto the first electrode pad 30, causing a short circuit in the semiconductor structure.
[0032] In one embodiment, the orthographic projection of each first conductive line 71 on the substrate 10 does not overlap with the orthographic projection of the second electrode pad 40 on the substrate 10, and the orthographic projection of each second conductive line 72 on the substrate 10 does not overlap with the orthographic projection of the first electrode pad 30 on the substrate 10. This effectively reduces the risk of a short circuit in the semiconductor structure.
[0033] In one embodiment, Figure 1 As shown, the orthographic projections of the first wires 71 on the substrate 10 do not overlap with the orthographic projections of the second electrode 60 on the substrate 10. This reduces the risk of the first wires 71 burning and falling onto the second electrode 60, causing a short circuit in the semiconductor structure.
[0034] In one embodiment, Figure 1 The orthographic projections of the second wires 72 on the substrate 10 do not overlap with the orthographic projections of the first electrode 50 on the substrate 10. This reduces the risk of the second wires 72 burning and falling onto the first electrode 50, causing a short circuit in the semiconductor structure.
[0035] In one embodiment, one of the first electrode pad 30 and the second electrode pad 40 is a source pad, and the other is a drain pad. For example, the first electrode pad 30 is a source pad, and the second electrode pad 40 is a drain pad.
[0036] In one embodiment, Figure 1 As shown, the semiconductor structure further includes a gate pad 20 and a third electrode 91 . The plurality of wires 70 include a third wire 73 . The gate pad 20 is connected to the third electrode 91 via the third wire 73 .
[0037] In one embodiment, Figure 1 As shown, the orthographic projections of the first conductive lines 71 on the substrate 10 do not overlap with the orthographic projections of the gate pad 20 and the third electrode 91 on the substrate 10; and the orthographic projections of the second conductive lines 72 on the substrate 10 do not overlap with the orthographic projections of the gate pad 20 and the third electrode 91 on the substrate 10. This further reduces the risk of short circuits in the semiconductor structure.
[0038] In one example, Figure 1As shown, the orthographic projection of the third wire 73 on the substrate 10 does not overlap with the orthographic projections of the first electrode pad 30, the second electrode pad 40, the first electrode 50, and the second electrode 60 on the substrate 10. With such an arrangement, the risk of the third wire 73 being burned out and causing a short circuit in the semiconductor structure can be avoided.
[0039] In one embodiment, as Figure 1 shown, the semiconductor structure includes a central region 101 and a peripheral region 102. The central region 101 may be the active region of the semiconductor structure, and the peripheral region 102 may be the isolation region of the semiconductor structure. The gate pad 20, the first electrode pad 30, and the second electrode pad 40 are located in the central region 101. The first electrode 50, the second electrode 60, and the third electrode 91 are located in the peripheral region 102.
[0040] In some embodiments, the peripheral region 102 may surround the central region 101. The peripheral region 102 includes a first sub-peripheral region 1021 and a second sub-peripheral region 1022 located on opposite sides of the central region 101, and a third sub-peripheral region 1023 and a fourth sub-peripheral region 1024 located on opposite sides of the central region 101.
[0041] In one embodiment, as Figure 1 shown, the distance between the first electrode pad 30 and the first sub-peripheral region 1021 is less than the distance between the second electrode pad 40 and the first sub-peripheral region 1021, and the distance between the first electrode pad 30 and the second sub-peripheral region 1022 is greater than the distance between the second electrode pad 40 and the second sub-peripheral region 1022; at least one of the first electrodes 50 is located in the first sub-peripheral region 1021, and at least one of the second electrodes 60 is located in the second sub-peripheral region 1022. Since the distance between the first electrode pad 30 and the first sub-peripheral region 1021 is less than the distance between the second electrode pad 40 and the first sub-peripheral region 1021, there is a larger space between the second electrode pad 40 and the first sub-peripheral region 1021, which helps to stagger the first wire 71 connecting the first electrode pad 30 and the first electrode 50 in the first sub-peripheral region 1021 and the second electrode pad 40 in the direction perpendicular to the substrate 10; since the distance between the first electrode pad 30 and the second sub-peripheral region 1022 is greater than the distance between the second electrode pad 40 and the second sub-peripheral region 1022, there is a larger space between the first electrode pad 30 and the second sub-peripheral region 1022, which helps to stagger the second wire 72 connecting the second electrode pad 40 and the second electrode 60 in the second sub-peripheral region 1022 and the first electrode pad 30 in the direction perpendicular to the substrate 10.
[0042] Further, as Figure 1As shown, in a direction perpendicular to the direction in which the first sub-peripheral region 1021 points to the second sub-peripheral region 1022, the first electrode pads 30 and the second electrode pads 40 are arranged alternately. With such an arrangement, the space between two adjacent first electrode pads 30 where no second electrode pad 40 is provided is relatively large, which is more conducive to staggering the first wire 71 connecting the first electrode pad 30 and the first electrode 50 in the first sub-peripheral region 1021 and the second electrode pad 40 in a direction perpendicular to the substrate 10; and the space between two adjacent second electrode pads 40 where no first electrode pad 30 is provided is relatively large, which is more conducive to staggering the second wire 72 connecting the second electrode pad 40 and the second electrode 60 in the second sub-peripheral region 1022 and the first electrode pad 30 in a direction perpendicular to the substrate 10.
[0043] The first electrode pads 30 and the second electrode pads 40 being arranged alternately may be such that there is one second electrode pad 40 between two adjacent first electrode pads 30, and there is one first electrode pad 30 between two adjacent second electrode pads 40. Figure 1 In the illustrated embodiment, the number of the first electrode pads 30 is one more than the number of the second electrode pads 40; the first electrode pad 30 includes a first sub-electrode pad 31, a second sub-electrode pad 32, and a third sub-electrode pad 33 located between the first sub-electrode pad 31 and the second sub-electrode pad 32. The first sub-electrode pad 31 is adjacent to the third sub-peripheral region 1023, the second sub-electrode pad 32 is adjacent to the fourth sub-peripheral region 1024. There is one second electrode pad 40 between the first sub-electrode pad 31 and the third sub-electrode pad 33, and there is one second electrode pad 40 between the second sub-electrode pad 32 and the third sub-electrode pad 33. Here, an electrode pad being adjacent to a sub-peripheral region means that there is no other electrode pad between them. In other embodiments, there may be two or more second electrode pads 40 between two adjacent first electrode pads 30, and there may be two or more first electrode pads 30 between two adjacent second electrode pads 40.
[0044] In one embodiment, as Figure 1 shown, in the direction in which the first sub-peripheral region 1021 points to the second sub-peripheral region 1022, the size of the first electrode pad 30 is a first size h1; the distance between the end of the first electrode pad 30 away from the first sub-peripheral region 1021 and the end of the second electrode pad 40 away from the second sub-peripheral region 1022 is d, and d is less than or equal to half of h1. With such an arrangement, the space between the second electrode pad 40 and the first sub-peripheral region 1021 can be relatively large, which is more conducive to staggering the first wire 71 connecting the first electrode pad 30 and the first electrode 50 in the first sub-peripheral region 1021 and the second electrode pad 40 in a direction perpendicular to the substrate 10.
[0045] In one embodiment, as Figure 1As shown, in the direction where the first sub-peripheral region 1021 points to the second sub-peripheral region 1022, the size of the second electrode pad 40 is the second size h2, and dcu is less than or equal to half of h2. With such a setting, the space between the first electrode pad 30 and the second sub-peripheral region 1022 can be made larger, which is more conducive to staggering the second wire 72 connecting the second electrode pad 40 and the second electrode 60 in the second sub-peripheral region 1022 and the first electrode pad 30 in the direction perpendicular to the substrate 10.
[0046] In one embodiment, as Figure 1 shown, at least one of the first electrodes 50 is located in the third sub-peripheral region 1023, and the first electrode pad 30 (i.e., the first sub-electrode pad 31) adjacent to the third sub-peripheral region 1023 is connected to the first electrode 50 located in the third sub-peripheral region 1023. Wherein the first electrode pad 30 being adjacent to the third sub-peripheral region 1023 means that there is no other electrode pad between the first electrode pad 30 and the third sub-peripheral region 1023. Thus, the first wire 71 connecting the first sub-electrode pad 31 and the first electrode 50 located in the third sub-peripheral region 1023 can extend along the direction from the third sub-peripheral region 1023 to the fourth sub-peripheral region 1024, so that these first wires 71 are staggered from the second electrode pad 40 in the direction perpendicular to the substrate 10; and the length of the first wire 71 connecting the first sub-electrode pad 31 and the first electrode 50 located in the third sub-peripheral region 1023 can be made smaller, which also helps to reduce the risk of the first wire 71 falling on the second electrode pad 40 after being burned out.
[0047] In one embodiment, as Figure 1 shown, at least one of the first electrodes 50 is located in the fourth sub-peripheral region 1024, and the first electrode pad 30 (i.e., the second sub-electrode pad 32) adjacent to the fourth sub-peripheral region 1024 is connected to the first electrode 50 located in the fourth sub-peripheral region 1024. Thus, the first wire 71 connecting the second sub-electrode pad 32 and the first electrode 50 located in the fourth sub-peripheral region 1024 can extend along the direction from the third sub-peripheral region 1023 to the fourth sub-peripheral region 1024, so that these first wires 71 are staggered from the second electrode pad 40 in the direction perpendicular to the substrate 10; and the length of the first wire 71 connecting the second sub-electrode pad 32 and the first electrode 50 located in the fourth sub-peripheral region 1024 can be made smaller, which also helps to reduce the risk of the first wire 71 falling on the second electrode pad 40 after being burned out.
[0048] In one embodiment, as Figure 1As shown, the first electrode pad 30 and the second electrode pad 40 are alternately arranged in the direction from the third sub-peripheral area 1023 to the fourth sub-peripheral area 1024; the first electrode pad 30 includes a first sub-electrode pad 31 adjacent to the third sub-peripheral area 1023, a second sub-electrode pad 32 adjacent to the fourth sub-peripheral area 1024, and a third sub-electrode pad 33 located between the first sub-electrode pad 31 and the second sub-electrode pad 32; the first sub-peripheral area 1021, the third sub-peripheral area 1023 and the fourth sub-peripheral area 1024 are respectively provided with the first electrode 50, and the second electrode 60 is located in the second sub-peripheral area 1022; the first sub-electrode pad 31 is connected to the first electrode 50 located in the third sub-peripheral area 1023, the second sub-electrode pad 32 is connected to the first electrode 50 located in the fourth sub-peripheral area 1024, and the third sub-electrode pad 33 is connected to the first electrode 50 located in the first sub-peripheral area 1021. In this way, the first wires 71 connected to each first electrode pad 30 extend from the first sub-electrode pad 31 in a direction away from the second electrode pad 40, which helps to stagger the first wires 71 and the second electrode pad 40 in a direction perpendicular to the substrate 10; the second wires 72 connected to the second electrode pad 40 extend from the second electrode pad 40 in a direction away from the first electrode pad 30, which helps to stagger the second wires 72 and the first electrode pad 30 in a direction perpendicular to the substrate 10.
[0049] In one embodiment, Figure 1 As shown, the third electrode 91 is located in the first sub-peripheral region 1021; the gate pad 20 is located between the first electrode pad 30 and the first sub-peripheral region 1021; and the third electrode 91 and the gate pad 20 are located on the same side of the first electrode 50 in the first sub-peripheral region 1021. This arrangement helps prevent the orthographic projection of the third wire 73 on the substrate 10 from overlapping with the orthographic projection of the first electrode pad 30 on the substrate 10.
[0050] In one embodiment, the first electrode pad 30 is a source pad, and the second electrode pad 40 is a drain pad. Figure 1As shown, the semiconductor structure further includes a Kelvin source 92 located in the first sub-peripheral region 1021. Within the first sub-peripheral region 1021, the Kelvin source 92 is located on the side of the first electrode 50 facing the third sub-peripheral region 1023; the plurality of wires 70 includes a fourth wire 74, and the first sub-electrode pad 31 is connected to the Kelvin source 92 through the fourth wire 73; the orthographic projection of the fourth wire 74 on the substrate 10 does not overlap with the orthographic projection of the drain pad on the substrate 10. By arranging the Kelvin source 92 in the first sub-peripheral region 1021 on the side of the first electrode 50 facing the third sub-peripheral region 1023, and connecting the Kelvin source 92 to the first sub-electrode pad 31 adjacent to the third sub-peripheral region 1023 through the fourth wire 74, the second sub-electrode pad 32 connected to the first electrode 50 in the first sub-peripheral region 1021 and the fourth wire 74 can be staggered in the direction perpendicular to the substrate 10, avoiding the risk of short circuit of the semiconductor structure caused by the fourth wire 74 breaking and falling on the second sub-electrode pad 32.
[0051] In one embodiment, as Figure 2 shown, the semiconductor structure further includes an insulating layer 80, and the insulating layer 80 is located on the side of the first electrode pad 30 and the second electrode pad 40 away from the substrate 10; the insulating layer 80 covers the region of the first electrode pad 30 that is not connected to the first wire 71. With such an arrangement, even if the second wire 72 breaks and falls on the region of the first electrode pad 30 covered by the insulating layer 80, the insulating layer insulates the second wire 72 from the first electrode pad 30, avoiding the risk of short circuit of the semiconductor device.
[0052] In one embodiment, as Figure 2 shown, the insulating layer 80 covers the region of the second electrode pad 40 that is not connected to the second wire 72. With such an arrangement, even if the first wire 71 breaks and falls on the region of the second electrode pad 40 covered by the insulating layer 80, the insulating layer insulates the first wire 71 from the second electrode pad 40, avoiding the risk of short circuit of the semiconductor device.
[0053] In one embodiment, the semiconductor structure is a HEMT. The semiconductor layer of the semiconductor structure can be a nitride semiconductor layer, for example, it can be a GaN layer.
[0054] It should be noted that in the drawings, the dimensions of layers and regions may be exaggerated for clarity of illustration. Also, it is understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or an intermediate layer may be present. Additionally, it is understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or more than one intermediate layer or element may be present. Further, it is understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or more than one intermediate layer or element may also be present. Like reference numerals throughout the specification indicate like elements.
[0055] Those skilled in the art will readily conceive of other embodiments of the present application upon considering the specification and practicing the disclosure herein. The present application is intended to cover any variations, uses, or adaptations of the present application, which follow the general principles of the present application and include known common knowledge or conventional technical means in the technical field not disclosed in the present application. The specification and examples are only to be considered exemplary, and the true scope and spirit of the present application are pointed out by the following claims.
[0056] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present application is only limited by the appended claims.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure comprises: substrate; A first electrode pad, a second electrode pad, a first electrode, and a second electrode located on one side of the substrate; A plurality of wires, including a first wire and a second wire; the first electrode pad is connected to the first electrode via at least one of the first wires, and the second electrode pad is connected to the second electrode via at least one of the second wires; an orthographic projection of at least one of the first wires on the substrate does not overlap with an orthographic projection of the second electrode pad on the substrate, and / or an orthographic projection of at least one of the second wires on the substrate does not overlap with an orthographic projection of the first electrode pad on the substrate.
2. The semiconductor structure according to claim 1, wherein The first electrode pad is connected to the first electrode via a plurality of first wires, and the orthographic projection of each of the first wires on the substrate does not overlap with the orthographic projection of the second electrode pad on the substrate; And / or, the second electrode pad is connected to the second electrode via a plurality of second wires, and an orthographic projection of each second wire on the substrate does not overlap with an orthographic projection of the first electrode pad on the substrate.
3. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a central area and a peripheral area, the peripheral area includes a first sub-peripheral area and a second sub-peripheral area located on opposite sides of the central area; the first electrode pad and the second electrode pad are located in the central area; the distance between the first electrode pad and the first sub-peripheral area is smaller than the distance between the second electrode pad and the first sub-peripheral area, and the distance between the first electrode pad and the second sub-peripheral area is larger than the distance between the second electrode pad and the second sub-peripheral area; at least one first electrode is located in the first sub-peripheral area, and at least one second electrode is located in the second sub-peripheral area.
4. The semiconductor structure according to claim 3, wherein: In a direction perpendicular to a direction from the first sub-peripheral area to the second sub-peripheral area, the first electrode pads and the second electrode pads are alternately arranged.
5. The semiconductor structure according to claim 3, characterized in that, In the direction from the first sub-peripheral region to the second sub-peripheral region, the distance between the end of the first electrode pad away from the first sub-peripheral region and the end of the second electrode pad away from the second sub-peripheral region is less than or equal to half the size of the first electrode pad; and / or, in the direction from the first sub-peripheral region to the second sub-peripheral region, the distance between the end of the first electrode pad away from the first sub-peripheral region and the end of the second electrode pad away from the second sub-peripheral region is less than or equal to half the size of the second electrode pad.
6. The semiconductor structure according to claim 1, wherein, The semiconductor structure includes a central region and a peripheral region, wherein the peripheral region includes a third sub-peripheral region and a fourth sub-peripheral region located on opposite sides of the central region; At least one of the first electrodes is located in the third sub-peripheral area, and is connected to the first electrode pad adjacent to the third sub-peripheral area and the first electrode located in the third sub-peripheral area; and / or, at least one of the first electrodes is located in the fourth sub-peripheral area; and is connected to the first electrode pad adjacent to the fourth sub-peripheral area and the first electrode located in the fourth sub-peripheral area.
7. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes an insulating layer located on a side of the first electrode pad and the second electrode pad away from the substrate; the insulating layer covers an area of the first electrode pad not connected to the first wire; and / or, the insulating layer covers an area of the second electrode pad not connected to the second wire.
8. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure includes a central region and a peripheral region, and the peripheral region includes a first sub-peripheral region and a second sub-peripheral region located on opposite sides of the central region, and a third sub-peripheral region and a fourth sub-peripheral region located on opposite sides of the central region; The first electrode pad and the second electrode pad are alternately arranged in a direction from the third sub-peripheral region to the fourth sub-peripheral region; the first electrode pad includes a first sub-electrode pad adjacent to the third sub-peripheral region, a second sub-electrode pad adjacent to the fourth sub-peripheral region, and a third sub-electrode pad located between the first sub-electrode pad and the second sub-electrode pad; the first electrode is provided in the first sub-peripheral region, the third sub-peripheral region, and the fourth sub-peripheral region respectively, and the second electrode is located in the second sub-peripheral region; the first sub-electrode pad is connected to the first electrode in the third sub-peripheral region, the second sub-electrode pad is connected to the first electrode in the fourth sub-peripheral region, and the third sub-electrode pad is connected to the first electrode in the first sub-peripheral region.
9. The semiconductor structure according to claim 8, wherein The semiconductor structure further includes a gate pad located in the central region and a third electrode located in the first sub-peripheral region, and the plurality of wires includes a third wire, and the gate pad is connected to the third electrode through the third wire; the gate pad is located between the first electrode pad and the first sub-peripheral region; the third electrode and the gate pad are on the same side of the first electrode in the first sub-peripheral region.
10. The semiconductor structure according to claim 8, wherein: The first electrode pad is a source pad, and the second electrode pad is a drain pad; the semiconductor structure further includes a Kelvin source located in the first sub-peripheral region, and in the first sub-peripheral region, the Kelvin source is located on a side of the first electrode facing the third sub-peripheral region; the plurality of wires includes a fourth wire, and the first sub-electrode pad is connected to the Kelvin source through the fourth wire; a positive projection of the fourth wire on the substrate does not overlap with a positive projection of the drain pad on the substrate.