Stacked integrated microdisplay device

Abstract

The utility model discloses a stacked and integrated micro display device, and relates to the technical field of semiconductors. The micro display device comprises a driving wafer and one or more display device layers arranged on the driving wafer, any display device layer comprises a sub-pixel and an insulating layer, and one surface, far away from the driving wafer, of the sub-pixel is a first ohmic contact layer; the insulating layer in at least one display device layer is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or partial side wall compared with the insulating layer around the same layer; the first ohmic contact layers of the sub-pixels in any display device layer are in common cathode connection through the transparent conductive layer, and the transparent conductive layer covers the first ohmic contact layer of the sub-pixels in each display device layer.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly to a stacked integrated microdisplay device. Background Art

[0002] In the field of microdisplay, in order to perform color display, there is a need for multi-color stacked integration.

[0003] In related technologies, as Figure 1 shown, by performing metal coating on the driving wafer end and the first color system target device end, bonding the two together through high-temperature metal bonding, preparing the first color system device using semiconductor processes, filling insulating substances, and then planarizing, preparing the cathode contact of the through-hole electrode at the other end of this layer and the anode contact for driving interconnection with other two color system devices; then, the second color system device and the third color system device are integrated with the anode in a similar manner to the first color system stacking; finally, a transparent electrode is made on the upper surface of the third color system device to contact the corresponding cathode contacts of the first / second / third color system devices, realizing the transparent conductive layer on the upper surface of the third color system device and completing the multi-color stacked integration solution.

[0004] Based on the above technical solution, each color system device requires process steps such as metal bonding layer, transparent electrode, insulating layer filling, planarization, through-hole electrode, etc. While the process complexity is high, the electrode contact area is relatively small. As the injection current increases, since the smaller the current area, the greater the current density, it causes a higher resistance value of the transparent conductive layer, increases the heat of the chip, deteriorates the optoelectronic performance of the chip, and reduces the reliability of the device. Summary of the Utility Model

[0005] The purpose of the utility model is to provide a stacked integrated microdisplay device, which can increase the current injection area, reduce the resistance, improve the optoelectronic efficiency of the device, and realize the preparation of high-brightness pixel units.

[0006] To achieve the above utility model purpose, the utility model proposes the following technical solution:

[0007] On the one hand, a stacked integrated microdisplay device is provided, and the microdisplay device includes a driving wafer and one or more display device layers arranged on the driving wafer;

[0008] Any one of the display device layers includes sub-pixels and an insulating layer. The side of the sub-pixel away from the driving wafer is a first ohmic contact layer, and the projections of the sub-pixels included in any one display device layer on the driving wafer do not overlap with the projections of the sub-pixels included in the other display device layers;

[0009] An insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer;

[0010] The first ohmic contact layers of the sub-pixels in any one of the display device layers are connected in a common cathode manner through a transparent conductive layer, and the transparent conductive layer is disposed above the first ohmic contact layers of the sub-pixels in each display device layer.

[0011] In a possible implementation, the top height of the insulating layer around the sub-pixel in at least one of the display device layers is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, and is not lower than the bottom height of the first ohmic contact layer of the sub-pixel in the same layer.

[0012] In a possible implementation, the number of layers of the display device layer is at least two;

[0013] In the insulating layer filled in at least one display device layer above the i-th display device layer, an opening is provided in an area aligned with the i-th sub-pixel in the i-th display device layer to expose the first ohmic contact layer of the i-th sub-pixel;

[0014] The transparent conductive layer is attached to the surface of the opening to be connected to the first ohmic contact layer of the i-th sub-pixel.

[0015] In a possible implementation, the size of the opening gradually increases in the direction away from the driving wafer.

[0016] In a possible implementation, in the top display device layer, the insulating layer is attached to the side walls of the sub-pixels in the same layer.

[0017] In a possible implementation, a metal enhancement structure is provided above the transparent conductive layer, and the projection of the metal enhancement structure on the driving wafer does not coincide with the second ohmic contact layer in the sub-pixel in any one of the display device layers.

[0018] In a possible implementation, the metal enhancement structure is provided in units of mother pixels; or, the metal enhancement structure is provided in units of sub-pixels.

[0019] In a possible implementation, the driving wafer includes anode contacts;

[0020] The sub-pixel in any one of the display device layers includes, stacked in the direction away from the driving wafer: a metal bonding layer, a second ohmic contact layer, an active layer, and a first ohmic contact layer;

[0021] A metal bonding layer is disposed at the projection position of the sub-pixel in any one of the display device layers on the display device layer below it.

[0022] The sub-pixel in any one of the display device layers is anodically connected to the anode contact in the driving wafer through the metal bonding layer in the display device layer below it.

[0023] In a possible implementation manner, in addition to the top display device layer, through-hole interconnection metal structures penetrating the current display device layer are further included in other display device layers. The bottom of the through-hole interconnection metal structure is connected to the metal bonding layer in the current display device layer, and the top is connected to the metal bonding layer in the upper display device layer.

[0024] In a possible implementation manner, the through-hole interconnection metal structure penetrates the color system compound.

[0025] In a possible implementation manner, a partial damaged layer of the first ohmic contact layer is removed.

[0026] Compared with the prior art, the present utility model has the following beneficial effects:

[0027] The micro-display device includes one or more display device layers. The insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer, and the first ohmic contact layer of the sub-pixel in any display device layer is commonly cathodically connected through a transparent conductive layer. The transparent conductive layer is disposed above the first ohmic contact layer of the sub-pixel in each display device layer, thereby greatly increasing the contact area between the transparent conductive layer and the epitaxy, increasing the current injection area, reducing the resistance, improving the optoelectronic efficiency of the device, and realizing the preparation of high-brightness pixel units. Description of the Drawings

[0028] Figure 1 is a schematic structural diagram of a stacked integrated micro-display device provided in the related art;

[0029] Figure 2 is a schematic structural diagram of a micro-display device with a single display device layer provided in an embodiment of the present application;

[0030] Figure 3 is a schematic structural diagram of a micro-display device with a single display device layer provided in an embodiment of the present application;

[0031] Figure 4It is a schematic structural diagram of a microdisplay device with a single-layer display device layer provided in an embodiment of the present application;

[0032] Figure 5 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0033] Figure 6 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0034] Figure 7 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0035] Figure 8 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0036] Figure 9 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0037] Figure 10 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0038] Figure 11 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0039] Figure 12 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0040] Figure 13 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0041] Figure 14 It is a schematic structural diagram of a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0042] Figure 15 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0043] Figure 16 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0044] Figure 17 It is a schematic structural diagram of a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0045] Figure 18 is a flowchart of a method for manufacturing a microdisplay device provided in an embodiment of the present application;

[0046] Figure 19 is a schematic diagram of the manufacturing process of a single-layer pixelization provided in an embodiment of the present application;

[0047] Figure 20 is a schematic diagram of the manufacturing process of a double-layer pixelization provided in an embodiment of the present application;

[0048] Figure 21 is a schematic diagram of the electrical connection process for a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0049] Figure 22 is a schematic diagram of the electrical connection process for a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0050] Figure 23 is a schematic diagram of the electrical connection process for a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0051] Figure 24 is a schematic diagram of the electrical connection process for a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0052] Figure 25 is a schematic diagram of the electrical connection process for a microdisplay device with a double-layer display device layer provided in an embodiment of the present application;

[0053] Figure 26 is a schematic diagram of the manufacturing process of a triple-layer pixelization provided in an embodiment of the present application;

[0054] Figure 27 is a schematic diagram of the electrical connection process for a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application;

[0055] Figure 28 is a schematic diagram of the electrical connection process for a microdisplay device with a triple-layer display device layer provided in an embodiment of the present application.

[0056] Reference numerals:

[0057] 100 - Driving wafer, 110 - Anode contact, 200 - First display device layer, 210 - First sub - pixel, 220 - First insulating layer, 300 - Second display device layer, 310 - Second sub - pixel, 320 - Second insulating layer, 400 - Third display device layer, 410 - Third sub - pixel, 420 - Third insulating layer, 500 - Transparent conductive layer, 600 - Opening, 700 - Metal enhancement structure, 800 - Through - hole interconnecting metal, 910 - Metal bonding layer, 920 - First ohmic contact layer, 930 - Second ohmic contact layer, 940 - First layer color - system compound, 950 - Second layer color - system compound, 960 - Third layer color - system compound. Detailed implementation manners

[0058] To make the objectives, technical solutions and advantages of the present utility model clearer, the technical solutions in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model. Apparently, the described embodiments are only a part rather than all of the embodiments of the present utility model. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0059] In the description of the present utility model, it should be understood that the orientation or positional relationships indicated by the terms "vertical", "upper", "lower", "top", "side", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, unless otherwise specified, the meaning of "plural" is two or more.

[0060] In the description of the present utility model, it should be noted that unless otherwise clearly specified and defined, the terms "mounted", "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0061] In the embodiments of the present application, the optimization is mainly aimed at the inherent deficiencies of misaligned bonding metals and devices in terms of manufacturing cost. By planarizing the first ohmic contact layer of the sub-pixel to the transparent conductive layer used for common cathode connection, the opening size for interconnecting the first ohmic contact layer of the sub-pixel is designed to be greater than or equal to the device epitaxial size, greatly increasing the contact area between the transparent conductive layer and the epitaxy, increasing the current injection area, reducing the resistance, improving the optoelectronic efficiency of the device, realizing the preparation of high-brightness pixel units. At the same time, the process difficulty of device preparation is reduced, the process flow is simplified, and the preparation of low-cost and high-precision pixel devices is realized.

[0062] Next, the device structure proposed in the present application will be described.

[0063] First, the embodiments of the present application provide a stacked integrated microdisplay device, as Figures 2 to 12 shown. The microdisplay device includes:

[0064] A driving wafer 100, and one or more display device layers disposed on the driving wafer 100; each display device layer includes sub-pixels and an insulating layer. The side of the sub-pixel away from the driving wafer 100 is the first ohmic contact layer, and the projection of the sub-pixels included in any display device layer on the driving wafer 100 does not coincide with the projection of the sub-pixels included in the other display device layers; the insulating layer in at least one display device layer is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer; the first ohmic contact layer of the sub-pixels in any display device layer is connected to the common cathode through a transparent conductive layer 500, and the transparent conductive layer 500 is disposed on the first ohmic contact layer of the sub-pixels in each display device layer.

[0065] In the embodiments of the present application, a microdisplay device with a single layer or multiple display device layers is provided. Each display device layer is provided with at least one sub-pixel and an insulating layer. The insulating layer in each display device layer is used for insulating protection of the sub-pixels in this layer. When the display device layer is multiple layers, the projection of the sub-pixels included in any display device layer on the driving wafer 100 does not coincide with the projection of the sub-pixels included in the other display device layers, so as to reduce the interference problem caused by multi-layer stacking display. In addition, when the microdisplay device has multiple display device layers, different display device layers can be designed to emit light with different wavelengths, so as to realize color display.

[0066] In the embodiments of the present application, at least one display device layer in the microdisplay device adopts the following structural design: an insulating layer is filled in this display device layer, and it is designed such that the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer. Specifically, in one case, the top height of the insulating layer around the sub-pixel is flush with the first ohmic contact layer of the sub-pixel in the same layer, so as to expose the upper surface of the first ohmic contact layer of this sub-pixel to contact with the transparent conductive layer 500. In another case, the top height of the insulating layer around the sub-pixel is lower than the first ohmic contact layer of the sub-pixel in the same layer, so as to expose the upper surface and part of the side wall of the first ohmic contact layer of this sub-pixel to contact with the transparent conductive layer 500, thereby further increasing the N-side current injection area. Especially when the sub-pixel is designed to be of a smaller size, the increase in the N-side current injection area is more obvious, and its power consumption advantage is more obvious.

[0067] It can be understood that the first ohmic contact layer and the second ohmic contact layer in the present application can be designed to be a P-type ohmic contact layer and an N-type ohmic contact layer respectively, or can be designed to be an N-type ohmic contact layer and a P-type ohmic contact layer respectively.

[0068] In one embodiment, as Figure 2 shown, the microdisplay device has a single display device layer: the first display device layer 200. In this first display device layer 200, the upper surface of the first ohmic contact layer of the first sub-pixel 210 is exposed and contacts the transparent conductive layer 500.

[0069] In one embodiment, as Figure 3 、 Figure 4 shown, the microdisplay device has a single display device layer: the first display device layer 200. In this first display device layer 200, the upper surface and part of the side wall of the first ohmic contact layer of the first sub-pixel 210 are exposed and contact the transparent conductive layer 500.

[0070] In one embodiment, as Figure 5 shown, the microdisplay device has a double display device layer: the first display device layer 200 and the second display device layer 300. In this first display device layer 200, the upper surface of the first ohmic contact layer of the first sub-pixel 210 is exposed and contacts the transparent conductive layer 500.

[0071] In one embodiment, as Figure 6 shown, the microdisplay device has a double display device layer: the first display device layer 200 and the second display device layer 300. In this first display device layer 200, the upper surface and part of the side wall of the first ohmic contact layer of the first sub-pixel 210 are exposed and contact the transparent conductive layer 500.

[0072] In one embodiment, as Figure 7As shown, the microdisplay device has a double-layer display device layer: a first display device layer 200 and a second display device layer 300. In this first display device layer 200, the upper surface and part of the side walls of the first ohmic contact layer of the first sub-pixel 210 are exposed. In this second display device layer 300, the upper surface of the first ohmic contact layer of the second sub-pixel 310 is exposed and is in contact with the transparent conductive layer 500.

[0073] In one embodiment, as Figure 8 、 Figure 9 As shown, the microdisplay device has a double-layer display device layer: a first display device layer 200 and a second display device layer 300. In this first display device layer 200, the upper surface and part of the side walls of the first ohmic contact layer of the first sub-pixel 210 are exposed. In this second display device layer 300, the upper surface and part of the side walls of the first ohmic contact layer of the second sub-pixel 310 are exposed and are in contact with the transparent conductive layer 500.

[0074] In one embodiment, as Figure 10 As shown, the microdisplay device has a triple-layer display device layer: a first display device layer 200, a second display device layer 300, and a third display device layer 400. In this first display device layer 200 and the second display device layer 300, the upper surfaces of the first ohmic contact layers of the corresponding sub-pixels are exposed and are in contact with the transparent conductive layer 500.

[0075] In one embodiment, as Figure 11 As shown, the microdisplay device has a triple-layer display device layer: a first display device layer 200, a second display device layer 300, and a third display device layer 400. In this first display device layer 200 and the second display device layer 300, the upper surfaces and part of the side walls of the first ohmic contact layers of the corresponding sub-pixels are exposed and are in contact with the transparent conductive layer 500.

[0076] In one embodiment, as Figure 12 As shown, the microdisplay device has a triple-layer display device layer: a first display device layer 200, a second display device layer 300, and a third display device layer 400. In these three display device layers, the upper surfaces and part of the side walls of the first ohmic contact layers of the corresponding sub-pixels are exposed and are in contact with the transparent conductive layer 500.

[0077] In one embodiment, as Figure 13 As shown, the microdisplay device has a triple-layer display device layer: a first display device layer 200, a second display device layer 300, and a third display device layer 400. In this first display device layer 200 and the second display device layer 300, the upper surfaces and part of the side walls of the first ohmic contact layers of the corresponding sub-pixels are exposed, and in the third display device layer 400, the upper surfaces of the first ohmic contact layers of the corresponding sub-pixels are exposed and are in contact with the transparent conductive layer 500.

[0078] Among them, each sub-pixel may include, stacked in a direction away from the driving wafer 100: a metal bonding layer, a second ohmic contact layer, an active layer, and a first ohmic contact layer.

[0079] Furthermore, a partial damaged layer of the above-mentioned first ohmic contact layer can be removed. In order to fully expose the upper surface of each sub-pixel and achieve good ohmic contact, an etching method can be used to remove a certain thickness of the damaged layer. In this design, the top height of the sub-pixel in this layer of the display device layer can be slightly lower than the bottom height of the metal bonding layer in the upper layer of the display device layer. In addition, good ohmic contact can also be achieved through a certain surface activation method, which is not limited in this application.

[0080] Specifically, the sub-pixel is made of a compound wafer material. The structures of some compound wafers are as follows. In some practical applications, the film layers of the compound wafer will be more complex, or there will be cross-use of materials. Without limiting the material range, it typically mainly includes a P-type material, an N-type material, and an MQW quantum well and other functional layers sandwiched between the two:

[0081]

[0082]

[0083] Among them, the transparent conductive layer 500 can be one or a combination of ITO (Indium Tin Oxide) thin film, AZO (Antimony doped Zinc Oxide) thin film, ATO (Antimony doped Tin Oxide) thin film, FTO (Fluorine doped Tin Oxide) thin film, or a metal-doped ITO single layer or stack formed by annealing a thin Al, Au, Ag film on the surface of ITO to enhance the current transmission ability of the common cathode.

[0084] Among them, the insulating layer material can include single film layers such as silicon oxide, silicon nitride, aluminum oxide, boron nitride, or a stack of two or more of these materials.

[0085] In a possible implementation manner, the top height of the insulating layer around the sub-pixel in at least one layer of the display device layer is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, and not lower than the bottom height of the first ohmic contact layer of the sub-pixel in the same layer.

[0086] In this implementation manner, when the first ohmic contact layer of the sub-pixel is exposed, the height of the insulating layer around the sub-pixel is further designed to be not lower than the bottom height of the first ohmic contact layer of this sub-pixel to avoid the leakage problem of the device.

[0087] In a possible implementation, as Figures 7 to 13 shown, the number of layers of the display device layer is at least two; in the insulating layer filled in at least one display device layer above the i-th display device layer, an opening 600 is formed that aligns with the region of the i-th sub-pixel in the i-th display device layer to expose the first ohmic contact layer of the i-th sub-pixel; the transparent conductive layer 500 is attached to the surface of the opening 600 to connect with the first ohmic contact layer of the i-th sub-pixel.

[0088] In this implementation, when the micro-display device includes multiple display device layers, if the upper display device layer of the current display device layer is designed with the insulating layer filled integrally, the first ohmic contact layer of the sub-pixel in the current display device layer is exposed by opening the opening 600 in the insulating layer of the upper device layer. Correspondingly, the transparent conductive layer 500 makes N-side contact with the sub-pixel in the current display device layer through this opening 600.

[0089] It can be understood that the number of layers of the upper display device layer can be one or more. The opening 600 penetrates through the insulating layers of one or more upper display device layers. This opening 600 can have only one stepped surface and is formed by one etching operation. Exemplarily, with reference to Figure 12 , the micro-display device has three display device layers. The third insulating layer 420 is filled integrally in the third display device layer 400, and the second insulating layer 320 is filled integrally in the second display device layer 300. Therefore, corresponding openings 600 are formed for the first sub-pixel 210 in the third insulating layer 420 and the second insulating layer 320, and corresponding openings 600 are formed for the second sub-pixel 310 in the third insulating layer 420; with reference to Figure 7 , the micro-display device has two display device layers. The second insulating layer 320 is filled integrally in the second display device layer 300. Therefore, a corresponding opening 600 is formed for the first sub-pixel 210 in the second insulating layer 320.

[0090] Furthermore, the size of the opening 600 gradually increases in the direction away from the driving wafer, which is convenient for process implementation. Exemplarily, with reference to Figures 7 to 13 , this opening 600 is used to expose the first sub-pixel 210 or the second sub-pixel 310. The size of the top of the opening 600 is significantly larger than the size of its bottom, and the size of the bottom of the opening 600 can be larger than or equal to the size of the upper surface of the first ohmic contact layer of the first sub-pixel 210 or the second sub-pixel 310.

[0091] Further, in the design where the number of display device layers is at least two, the insulating layer in the top display device layer is attached to the sidewalls of the sub-pixels in the same layer. By designing the insulating layer in the top display device layer to be attached to the sidewalls of the sub-pixels in the same layer instead of being integrally filled in the display device layer, the thickness of the integrally filled insulating layer in the micro-display device layer can be reduced, facilitating the exposure of the N surface of the sub-pixels in the lower display device layer. Exemplarily, in combination with reference to Figure 10 、 Figure 11 、 Figure 13 , the micro-display device has three display device layers, and the third insulating layer 420 is designed to be attached to the sidewalls of the third sub-pixels 410, facilitating the subsequent opening of corresponding openings 600 for the first sub-pixels 210, and exposing the first sub-pixels 210 through the openings 600; in combination with reference to Figure 5 、 Figure 6 , the micro-display device has two display device layers, and the second insulating layer 320 is designed to be attached to the sidewalls of the second sub-pixels 310, facilitating the direct exposure of the first sub-pixels 210 in the first insulating layer 220.

[0092] In a possible implementation, a metal enhancement structure 700 is provided above the transparent conductive layer 500, and the projection of the metal enhancement structure 700 on the driving wafer does not overlap with the second ohmic contact layer in the sub-pixels of any display device layer.

[0093] In this implementation, as shown in Figures 2 to 11 , by fabricating the metal enhancement structure 700 on the transparent conductive layer 500, current spreading and the improvement of the emission angle and brightness can be achieved. Among them, the metal enhancement structure 700 can be a single layer or a stack of metals such as Ni, Al, Ti, Au, etc.

[0094] Further, the metal enhancement structure 700 is set in units of mother pixels or sub-pixels. Among them, a mother pixel is a pixel unit formed by arranging a plurality of sub-pixels, and the specific setting method of the mother pixel in this application is not limited. Exemplarily, the number of sub-pixels in each display device layer can be set ≥ 1, and the sub-pixels in the three display device layers can be freely combined to form mother pixels. For example, one sub-pixel is arranged in each display device layer to form a mother pixel; two sub-pixels can also be arranged in the first display device layer 200, and one sub-pixel is arranged in each of the other two display device layers to form a mother pixel; two sub-pixels can also be arranged in the third display device layer 400, and one sub-pixel is arranged in each of the other two display device layers to form a mother pixel, etc.

[0095] Exemplarily, in combination with reference to Figure 10 , the metal enhancement structure 700 is set in units of mother pixels in the peripheral area of one mother pixel or multiple mother pixels. Figure 11 shows a scheme where the metal enhancement structure 700 is set in units of sub-pixels in the peripheral area of each sub-pixel.

[0096] In a possible implementation, as Figures 2 to 13 shown, the driving wafer 100 includes an anode contact 110; the sub-pixels in any display device layer include, stacked in a direction away from the driving wafer 100: a metal bonding layer, a second ohmic contact layer, an active layer, and a first ohmic contact layer; the sub-pixels in any display device layer are provided with a metal bonding layer at the projection position on the display device layer below it; the sub-pixels in any display device layer are anodically connected to the anode contact 110 in the driving wafer 100 through the metal bonding layer in the display device layer below it.

[0097] In this implementation, a plurality of anode contacts 110 are provided in the driving wafer 100, each sub-pixel in each display device layer corresponds to one or more anode contacts, and each sub-pixel in each display device layer is anodically connected to the corresponding anode contact 110 in the driving wafer 100. Specifically, each sub-pixel in each display device layer is provided with a metal bonding layer at the projection position on the display device layer below it, and is anodically connected to the corresponding anode contact 110 in the driving wafer 100 through the metal bonding layer in the display device layer below it.

[0098] Further, except for the top display device layer, other display device layers further include a via interconnect metal structure 800 that penetrates the current display device layer. The bottom of the via interconnect metal structure 800 is connected to the metal bonding layer in the current display device layer, and the top is connected to the metal bonding layer in the upper display device layer.

[0099] Among them, the via interconnect metal structure 800 may include a metal seed layer and its corresponding adhesion layer or barrier layer. The metal seed layer may be made of metals such as Al, Cu, W, etc., and the adhesion layer or barrier layer may be made of metals such as Ti, TiN, Ti / Cu, TaN / Cu, etc.

[0100] Exemplarily, as Figure 10As shown, a metal bonding layer and a via-interconnect metal structure 800 are provided in the first display device layer 200 and stacked in a direction away from the driving wafer. The metal bonding layer is connected to the anode contact 110 in the driving wafer 100. The bottom of the second sub-pixel 310 in the second display device layer 300 is connected to the top of the via-interconnect metal structure 800 in the first display device layer 200. Thus, the second sub-pixel 310 completes the anode connection through the via-interconnect metal structure 800 and the metal bonding layer in the first display device layer 200. Further, a metal bonding layer and a via-interconnect metal structure 800 are also provided in the second display device layer 300 and stacked in a direction away from the driving wafer. The bottom of the third sub-pixel 410 in the third display device layer 400 is connected to the top of the via-interconnect metal structure 800 in the second display device layer, and a corresponding via-interconnect metal structure 800 is also provided in the first display device layer 200 in the vertical direction. Thus, the third sub-pixel completes the anode connection through the via-interconnect metal structures 800 and the metal bonding layer in the first display device layer 200 and the second display device layer 300.

[0101] Further, as Figure 14 , Figure 15 , Figure 16 shown, the via-interconnect metal structure 800 penetrates through the color system compound, so that after pixelization preparation is completed according to the existing implementation method, the preparation of the via-interconnect metal structure can be directly carried out. Specifically, as Figure 14 , 15 shown, all the via-interconnect metal structures 800 can penetrate through the color system compound, or as Figure 16 shown, some of the via-interconnect metal structures 800 can penetrate through the color system compound.

[0102] Further, with reference to Figure 17, the setting of the relevant dimensions of the microdisplay device can be referred to as follows: the thickness B1 / B2 / B3 of the metal bonding layer is designed in the range of 10 nm to 1.5 μm, and the metal bonding layer is prepared in the direction of being thin and without voids or gaps. The optimal design thickness is different for different metal bonding methods; the thickness of the second ohmic contact layer is in the range of 5 nm to 300 nm; the thickness A1 / A2 / A3 of the first / second / third layer color system compound epitaxial layer is designed in the range of 0.2 μm to 5 μm, and the optimal design of different compound patterning sizes has different thicknesses. For example, for compound patterning ≤ 5 μm, A1 / A2 / A3 is optimal in the range of 0.2 to 2 μm. The epitaxial angle α1 / α2 / α3 of the compound is designed in the range of 90° ± 45°, and the preferred range is 90° ± 20°, which has the best performance in light extraction and pitch design; the via angle β between the second and third layer color system compounds and the via interconnect metal structure 800 is designed in the range of 90° ± 45°, and the preferred range is <90°; the thickness T1 of the transparent conductive layer is in the range of 10 nm to 500 nm. In addition, considering current spreading and transmittance at the same time, the thicker the layer, the better the current spreading, but the lower the transmittance; the thickness n of the metal enhancement structure 700 is designed in the range of 100 nm to 5000 nm. The metal enhancement structure 700 has an opening size in the sub-pixel opening size ≥ the second size of the sub-pixel color system compound epitaxy. For example, for the metal enhancement structure 700 corresponding to the first sub-pixel 210, the opening size: N1 ≥ N2, and the pixel size opening size design is similar.

[0103] In summary, the embodiment of the present application provides a stacked integrated microdisplay device. This microdisplay device includes one or more display device layers, and the insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer, and the first ohmic contact layer of the sub-pixel in any display device layer is connected to the common cathode through a transparent conductive layer. The transparent conductive layer is disposed on the first ohmic contact layer of the sub-pixel in each display device layer, thereby greatly increasing the contact area between the transparent conductive layer and the epitaxy, increasing the current injection area, reducing the resistance, improving the optoelectronic efficiency of the device, and realizing the preparation of high-brightness pixel units.

[0104] Next, a method for manufacturing a microdisplay device corresponding to the above-described structure will be described. As Figure 18 shown, the method for manufacturing a microdisplay device may include the following steps:

[0105] Step S1: Prepare a driving wafer.

[0106] Step S2: Bond and integrate one or more display device layers on the driving wafer. Any display device layer includes sub-pixels and an insulating layer. The side of the sub-pixel away from the driving wafer is the first ohmic contact layer. And the projections of the sub-pixels included in any display device layer on the driving wafer do not overlap with the projections of the sub-pixels included in the other display device layers. The insulating layer in at least one display device layer fills the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer.

[0107] Wherein, before preparing the transparent conductive layer, the following steps can also be performed: removing a part of the damaged layer of the first ohmic contact layer to achieve good ohmic contact.

[0108] If the number of display device layers is 1 layer and the display device layer only includes the first display device layer, step S2 specifically includes:

[0109] (1) Bond and integrate the first layer color system compound onto the driving wafer, and perform pixelization preparation on the first layer color system compound to form the first sub-pixels.

[0110] Among them, the preparation process of the first sub-pixels can be as Figure 19 shown, including:

[0111] The first step: Select the first layer color system compound 940 and prepare the second ohmic contact layer 930.

[0112] Specifically, prepare a contact material on the P contact surface or N contact surface of the first layer color system compound 940 to form the second ohmic contact layer 930. The contact material can be a transparent conductive thin film such as ITO, IZO, IGZO, AZO, etc., or a metal alloy thin film such as AuBe, AnZn, etc., and the thickness range is in the interval of 1 nm to 300 nm.

[0113] The second step: Bond and integrate the first layer color system compound 940 with the wafer.

[0114] Specifically, prepare bonding structures on the first layer color system compound 940 and the driving wafer 100 respectively, and bond and integrate the first layer color system compound 940 and the driving wafer 100 through wafer-level bonding to form a metal bonding layer 910.

[0115] The bonding structure can be a conductive material. The main bonding materials can be one or several of combinations such as Ni and Sn, Au and Sn, Cu and Sn, Au and In, Au and Au, Al and Al, Cu and Cu, ITO and ITO, etc. Between the bonding material and the wafer, there can be an adhesion layer (such as Cr, Ti, Ni, etc.) and a barrier depletion layer (such as Ni, Pt, Cu, etc.). The bonding structures on the compound and the driving wafer can be symmetric or asymmetric.

[0116] In one embodiment, symmetric metal bonding is used, that is, the bonding structures on the compound and the driving wafer are the same. The bonding structure is Cr(10nm, adhesion layer) / Pt(50nm, barrier depletion layer) / Au(100nm) / Sn(150nm) / Au(50nm). After high-temperature thermocompression bonding, the compound and the driving wafer complete bonding integration.

[0117] The third step: Pixelation preparation.

[0118] Remove the substrate and related structures of the first layer color system compound 940 that has completed bonding integration, exposing the first ohmic contact layer 920. After exposing the first ohmic contact layer 920, perform patterning pixel preparation on the first layer color system compound through semiconductor lithography and etching processes, using the second ohmic contact layer 930 as the etching stop layer. The etched first sub-pixels 210 correspond to the anode contacts in the driving wafer 100, which can be one-to-one or one-to-many. Subsequently, perform patterning etching to isolate the second ohmic contact layer 930, the metal bonding layer 910, etc. together to achieve independent sub-pixels.

[0119] (2) Fill the first sub-pixels with an insulating medium to form a first insulating layer, and expose the upper surface and / or part of the sidewalls of the first sub-pixels in the first insulating layer.

[0120] Specifically, based on the third step above, perform insulating medium filling to form a first insulating layer. The insulating medium includes dielectrics such as silicon oxide, silicon nitride, SiC, SiCN, PSG, BPSG, polyimide, etc. Subsequently, perform planarization and / or etching to expose the upper surface and / or part of the sidewalls of the first sub-pixels in the first insulating layer.

[0121] In one embodiment, as Figure 2 shown, through planarization, expose the surface of the first ohmic contact layer of the first sub-pixel. In one embodiment, as Figure 3 、 Figure 4 shown, through planarization and etching techniques, expose the surface and sidewalls of the first ohmic contact layer of the first sub-pixel.

[0122] If the number of layers of the display device layer is 2, and the display device layer includes a first display device layer and a second display device layer, then step S2 specifically includes:

[0123] (1) For the first display device layer, bond and integrate the first-layer color system compound onto the driving wafer, perform pixelation preparation on the first-layer color system compound to form first sub-pixels; fill the first sub-pixels with an insulating medium to form a first insulating layer, and planarize the first insulating layer until the upper surface of the first sub-pixels is exposed; prepare a via interconnect metal structure corresponding to the second sub-pixels in the first insulating layer.

[0124] Among them, the preparation process of the first display device layer can be similarly referred to the first to third steps in the above text, and as Figure 20 shown, further includes the following steps:

[0125] The fourth step: Planarization after filling with insulating material.

[0126] Specifically, perform insulating medium filling to form a first insulating layer 220. The insulating medium includes media such as silicon oxide, silicon nitride, SiC, SiCN, PSG, BPSG, and polyimide. Subsequently, perform planarization, which can be carried out by CMP, etching, or a combination of both, and the planarization stops at the upper surface of the first sub-pixels 210.

[0127] The fifth step: Preparation of via interconnect metal.

[0128] Specifically, pattern and prepare via structures in the first insulating layer 220, and then fill the vias with metal to form via interconnect metal 800.

[0129] In an embodiment, the first insulating layer further includes a color system compound whose central axis is aligned with the central axis of the second sub-pixels; preparing a via interconnect metal structure corresponding to the second sub-pixels in the first insulating layer includes: opening holes in the color system compound in the first insulating layer and backfilling with metal to form a via interconnect metal structure penetrating through the color system compound.

[0130] (2.1) For the second display device layer, bond and integrate the second-layer color system compound onto the first display device layer, perform pixelation preparation on the second-layer color system compound to form second sub-pixels; deposit an insulating medium on the sidewalls of the second sub-pixels to form a second insulating layer.

[0131] As Figure 20 shown, define the first display device layer completed in the fifth step as a new driving wafer, repeat the first to third steps, and stack until the pixelation preparation of the double layer is completed.

[0132] Further, an insulating layer is prepared, and after patterning, the epitaxial surface of the second sub-pixel is etched to form a second insulating layer on the sidewall of the second sub-pixel. Specifically, the second insulating layer can be formed by plasma deposition, sputtering, atomic layer deposition, etc., and the thickness ranges from 1 nm to 500 nm.

[0133] In one embodiment, as Figure 21 shown, the second insulating layer is formed on the sidewall of the second sub-pixel, and then the preparation of the electrical connection structure and the further preparation of the metal enhancement structure are carried out.

[0134] In one embodiment, as Figure 22 shown, after the preparation of the second insulating layer is completed, a certain thickness of the first insulating layer is removed by patterning etching to expose the sidewall surface of the first sub-pixel, and then the preparation of the electrical connection structure and the further preparation of the metal enhancement structure are carried out. The transparent conductive layer can cover the upper surface and the sidewall surface of the first ohmic contact layer of the first sub-pixel. This solution can continue to increase the N-side current injection area. Especially in the case of smaller pixel sizes, the increase in the N-side current injection area is more obvious, and its power consumption advantage is more obvious.

[0135] (2.2) For the second display device layer, the second color system compound is bonded and integrated onto the first display device layer, and the second color system compound is pixelated to form second sub-pixels; the second sub-pixels are filled with an insulating medium to form a second insulating layer, and the upper surface and / or part of the sidewalls of the second sub-pixels are exposed in the second insulating layer; the area of the second insulating layer aligned with the first sub-pixel is patterned and etched to form an opening to expose the upper surface and / or part of the sidewalls of the first sub-pixel.

[0136] As Figure 20 shown, the first display device layer completed in the fifth step is defined as a new driving wafer, and the first to third steps are repeated until the pixelation preparation of the double layer is completed.

[0137] Further, insulating medium filling is carried out, and then through planarization and / or etching techniques, the upper surface and / or part of the sidewalls of the second sub-pixels are exposed, and then the upper surface and / or part of the sidewalls of the first sub-pixels are exposed by patterning etching.

[0138] In one embodiment, as Figure 23 shown, the second display device layer is planarized to expose the first surface of the second sub-pixel, and then the first surface and the sidewalls of the first sub-pixel are patterned and etched, and then electrical connection is carried out.

[0139] In one embodiment, as Figure 24As shown, planarization technology and / or etching technology are performed on the second display device layer to expose the first surface and sidewalls of the second sub-pixel, and then the first surface and sidewalls of the first sub-pixel are patterned and etched. Then, electrical connection is performed.

[0140] In one embodiment, as Figure 25 shown, planarization is performed on the second display device layer, and an insulating layer material with a certain thickness is left above the second sub-pixel. Then, the first surfaces and sidewalls of the first sub-pixel and the second sub-pixel are patterned and exposed. Then, electrical connection is performed.

[0141] If the number of layers of the display device layer is 3, and the display device layer includes a first display device layer, a second display device layer, and a third display device layer, then step S2 specifically includes:

[0142] (1) For the first display device layer, bond and integrate the first layer of color system compound onto the driving wafer, perform pixelation preparation on the first layer of color system compound to form the first sub-pixel; perform insulating dielectric filling on the first sub-pixel to form the first insulating layer, and planarize the first insulating layer until the upper surface of the first sub-pixel is exposed; prepare via-interconnect metal structures corresponding to the second sub-pixel and the third sub-pixel in the first insulating layer.

[0143] Among them, the preparation process of the first display device layer can be similarly referred to the first step to the fifth step in the above text, which will not be elaborated here.

[0144] In one embodiment, the first insulating layer further includes a color system compound whose central axis is aligned with the central axes of the second sub-pixel and the third sub-pixel; preparing via-interconnect metal structures corresponding to the second sub-pixel and the third sub-pixel in the first insulating layer includes: opening holes in the color system compound in the first insulating layer and backfilling with metal to form via-interconnect metal structures penetrating through the color system compound.

[0145] (2) For the second display device layer, bond and integrate the second layer of color system compound onto the first display device layer, perform pixelation preparation on the second layer of color system compound to form the second sub-pixel; perform insulating dielectric filling on the second sub-pixel to form the second insulating layer, and planarize the second insulating layer until the upper surface of the second sub-pixel is exposed; prepare via-interconnect metal structures corresponding to the third sub-pixel in the second insulating layer.

[0146] Define the first display device layer completed in the fifth step as the new driving wafer, repeat the first step to the third step, stack until the pixelation preparation of the double layer is completed. Then perform insulating dielectric filling, and then expose the upper surface of the second sub-pixel through planarization, and then prepare via-interconnect metal structures.

[0147] In one embodiment, the second insulating layer further includes a color system compound whose central axis is aligned with the central axis of the third sub-pixel; preparing a via interconnect metal structure corresponding to the third sub-pixel in the second insulating layer, including: opening a hole in the color system compound in the second insulating layer and backfilling with metal to form a via interconnect metal structure penetrating through the color system compound.

[0148] (3.1) For the third display device layer, bond and integrate the third layer of color system compound onto the second display device layer, and perform pixelation preparation on the third layer of color system compound to form the third sub-pixel; deposit an insulating dielectric on the sidewalls of the third sub-pixel to form a third insulating layer; pattern-etch the area in the second insulating layer aligned with the first sub-pixel to form an opening to expose the upper surface and / or part of the sidewalls of the first sub-pixel.

[0149] As Figure 26 shown, define the prepared second display device layer as a new driving wafer, and repeat the first to third steps until the pixelation preparation of three layers is completed.

[0150] Further, prepare an insulating layer, and after patterning, etch to expose the epitaxial surface of the third sub-pixel to form a third insulating layer on the sidewalls of the third sub-pixel. Among them, the third insulating layer can be specifically formed by plasma deposition, sputtering, atomic layer deposition, etc., and the thickness range is 1 nm to 500 nm.

[0151] In one embodiment, as Figure 27 shown, the third insulating layer is formed on the sidewalls of the third sub-pixel and exposes the upper surface of the first sub-pixel through an opening, and then the preparation of the electrical connection structure and the further preparation of the metal enhancement structure are carried out.

[0152] In one embodiment, as Figure 28 shown, after the preparation of the third insulating layer is completed, further by means of pattern-etching, a certain thickness of the second insulating layer is removed to expose the sidewall surface of the second sub-pixel, and the upper surface and sidewalls of the first sub-pixel are exposed through an opening, and then the preparation of the electrical connection structure and the further preparation of the metal enhancement structure are carried out. The transparent conductive layer can cover the upper surface and sidewall surfaces of the first ohmic contact layers of the first sub-pixel and the second sub-pixel. Its solution can continue to increase the N-side current injection area. Especially in the case of smaller pixel sizes, the increase in the N-side current injection area is more obvious, and its power consumption advantage is more obvious.

[0153] (3.2) For the third display device layer, bond and integrate the third color system compound onto the second display device layer, and perform pixelation preparation on the third color system compound to form third sub-pixels; fill the third sub-pixels with an insulating medium to form a third insulating layer, and expose the upper surface and / or part of the sidewalls of the third sub-pixels in the third insulating layer; perform patterning etching on the area in the third insulating layer aligned with the second sub-pixels to form an opening to the upper surface and / or part of the sidewalls of the second sub-pixels, and perform patterning etching on the areas in the third insulating layer and the second insulating layer aligned with the first sub-pixels to form an opening to the upper surface and / or part of the sidewalls of the first sub-pixels.

[0154] As Figure 26 shown, define the prepared second display device layer as a new driving wafer, and repeat the first to third steps until the pixelation preparation of three layers is completed.

[0155] Furthermore, perform insulating medium filling, and then through planarization and / or etching techniques, expose the upper surface and / or part of the sidewalls of the third sub-pixels, and then perform patterning etching to expose the upper surface and / or part of the sidewalls of the first sub-pixels and the second sub-pixels.

[0156] In one embodiment, perform planarization on the third display device layer to expose the first surface of the third sub-pixels, then perform patterning etching to expose the first surface and sidewalls of the second sub-pixels and the first sub-pixels, and then perform electrical connection.

[0157] In one embodiment, perform planarization techniques and / or etching techniques on the third display device layer to expose the first surface and sidewalls of the third sub-pixels, then perform patterning etching to expose the first surface and sidewalls of the second sub-pixels and the first sub-pixels, and then perform electrical connection.

[0158] In one embodiment, perform planarization on the second display device layer, leaving an insulating layer material with a certain thickness above the third sub-pixels, then perform patterning to expose the first surface and sidewalls of the first sub-pixels, the second sub-pixels, and the third sub-pixels, and then perform electrical connection.

[0159] It can be understood that in the above embodiments, the first surface of each sub-pixel can be roughened to increase the light extraction efficiency. When light is emitted from the compound into the air, it is from a high refractive index medium to a low refractive index medium, and there is a total reflection phenomenon. Taking the GaN system as an example, the light generated in the active region is incident from the optically dense medium GaN (refractive index n = 2.4) to the optically sparse medium air (n = 1) during the emission process. The critical angle of total reflection is about 24.5°. That is to say, a large part of the light whose angle with the GaN / air interface is greater than 24.5° undergoes total reflection at the interface and returns to the compound. And this part of the light that returns to the compound will be affected by the bottom reflection again, reducing the light extraction efficiency again. By roughening the surface, the interface of total reflection can be reduced, the light extraction rate can be increased, and thus the brightness can be improved.

[0160] Step S3: Prepare a transparent conductive layer. The first ohmic contact layer of the sub-pixels in any display device layer is connected to the common cathode through the transparent conductive layer, and the transparent conductive layer is disposed on the first ohmic contact layer of the sub-pixels in each display device layer.

[0161] Specifically, after exposing the first surface of the sub-pixels in each display device layer, electrical connection is performed, and a transparent conductive film is deposited by sputtering, evaporation, etc. to form a transparent conductive layer.

[0162] Further, after step S3, it further includes: setting a metal enhancement structure on the transparent conductive layer, and the projection of the metal enhancement structure on the driving wafer does not coincide with the second ohmic contact layer in the sub-pixels of any display device layer.

[0163] Specifically, a metal enhancement structure is prepared on the transparent conductive layer, and the metal enhancement structure can be realized by patterned evaporation, sputtering, or by etching after coating.

[0164] In one embodiment, the metal enhancement structure is realized by Ni, Al, Ti, Au stacked patterned coating. Through this structure, better current spreading can be achieved, and at the same time, the cavity formed by this structure can confine the light emission distribution and improve the brightness.

[0165] In summary, in the method for manufacturing a microdisplay device provided by the embodiments of the present application, one or more display device layers are integrated on a driving wafer. The insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer, and the first ohmic contact layers of the sub-pixels in any display device layer are connected in a common cathode manner through a transparent conductive layer, and the transparent conductive layer is disposed above the first ohmic contact layers of the sub-pixels in each display device layer, thereby greatly increasing the contact area between the transparent conductive layer and the epitaxy, increasing the current injection area, reducing the resistance, improving the optoelectronic efficiency of the device, and realizing the preparation of high-brightness pixel units.

[0166] All of the above optional technical solutions can be combined arbitrarily to form optional embodiments of the present invention, that is, any number of embodiments can be combined to meet the requirements of different application scenarios, and all are within the protection scope of the present application, and will not be elaborated here one by one.

[0167] It should be noted that the above are only the preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A stacked integrated microdisplay device, characterized in that, The microdisplay device includes a driving wafer and one or more display device layers disposed on the driving wafer; Any one of the display device layers includes sub-pixels and an insulating layer. The side of the sub-pixel away from the driving wafer is a first ohmic contact layer, and the projections of the sub-pixels included in any one display device layer on the driving wafer do not coincide with the projections of the sub-pixels included in the other display device layers; The insulating layer in at least one of the display device layers is filled in the display device layer, and the top height of the insulating layer around the sub-pixel is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer, so that the first ohmic contact layer of the sub-pixel exposes the upper surface and / or part of the side wall compared with the surrounding insulating layer in the same layer; The first ohmic contact layers of the sub-pixels in any one of the display device layers are connected in common cathode through a transparent conductive layer, and the transparent conductive layer is disposed on the first ohmic contact layers of the sub-pixels in each display device layer.

2. The microdisplay device according to claim 1, wherein The top height of the insulating layer around the sub-pixel in at least one of the display device layers is not higher than the top height of the first ohmic contact layer of the sub-pixel in the same layer and not lower than the bottom height of the first ohmic contact layer of the sub-pixel in the same layer.

3. The microdisplay device according to claim 1, characterized in that, The number of the display device layers is at least two; In the insulating layer filled in at least one display device layer above the i-th display device layer, an opening is provided that aligns with the area of the i-th sub-pixel in the i-th display device layer to expose the first ohmic contact layer of the i-th sub-pixel; The transparent conductive layer is attached to the surface of the opening to be connected to the first ohmic contact layer of the i-th sub-pixel.

4. The microdisplay device according to claim 3, wherein The size of the opening gradually increases in the direction away from the driving wafer.

5. The microdisplay device according to claim 3, wherein In the top display device layer, the insulating layer is attached to the side walls of the sub-pixels in the same layer.

6. The microdisplay device according to claim 1, wherein A metal enhancement structure is provided above the transparent conductive layer, and the projection of the metal enhancement structure on the driving wafer does not coincide with the projection of the second ohmic contact layer in the sub-pixels in any one of the display device layers.

7. The microdisplay device according to claim 6, wherein The metal enhancement structure is provided in units of mother pixels; Or, The metal enhancement structure is provided in units of sub-pixels.

8. The microdisplay device according to claim 1, wherein The driving wafer includes an anode contact; The sub-pixels in any one of the display device layers include, stacked in the direction away from the driving wafer: a metal bonding layer, a second ohmic contact layer, an active layer, and a first ohmic contact layer; A metal bonding layer is provided at the projection position of the sub-pixels in any one of the display device layers on the lower display device layer; The sub-pixels in any one of the display device layers are anodically connected to the anode contact in the driving wafer through the metal bonding layer in the lower display device layer.

9. The microdisplay device according to claim 8, wherein Except for the display device layer at the top layer, the other display device layers further include a via interconnect metal structure that penetrates the display device layer of the current layer. The bottom of the via interconnect metal structure is connected to the metal bonding layer in the display device layer of the current layer, and the top is connected to the metal bonding layer in the display device layer of the upper layer.

10. The microdisplay device according to claim 9, characterized in that, The via interconnect metal structure penetrates through the color system compound.

11. The microdisplay device according to claim 1, wherein Part of the damaged layer of the first ohmic contact layer is removed.

Images