FT test circuit for audio chip

Abstract

The utility model discloses an FT test circuit for an audio chip, and belongs to the technical field of audio chips. Comprising a power supply module, the input end of the power supply module is connected with the output end of an upper computer, and the power supply output end of the power supply module is connected with the power supply input end of a main control sub-circuit, the power supply input end of a current test sub-circuit, the power supply input end of an IIS test sub-circuit and the power supply input end of an audio analysis sub-circuit. The output end of the main control sub-circuit is connected with the input end of a chip to be tested, the output end of the current test sub-circuit is connected with the chip to be tested, the IIS test sub-circuit is connected with a digital audio interface of the chip to be tested, and the output end of the audio analysis sub-circuit is simultaneously connected with the input end of an audio ADC interface of the chip to be tested and the input end of the upper computer. And the input end of the audio analysis sub-circuit is connected with the output end of the audio DAC interface of the chip to be tested. According to the utility model, the full-process automatic test of the audio chip is realized, the complexity of chip function and performance test is reduced, and the test efficiency is improved.

Description

Technical Field

[0001] The utility model belongs to the technical field of audio chips, and in particular relates to an FT test circuit for audio chips. Background Art

[0002] FT testing of audio chips is a rigorous and comprehensive process that uses environmental testing, aging testing, and application-specific performance testing to ensure the chips operate properly under various conditions and have good long-term stability. This testing not only ensures chip quality but also provides customers with confidence, allowing them to provide high-quality audio products to the market.

[0003] The existing FT testing of audio chips is mostly based on functional testing, while performance testing requires the use of independent test machines. If the test vectors of the audio chip cannot be fully covered, multiple test machines must be used for multiple rounds of testing, which not only increases the test steps but also increases the complexity of maintenance and calibration. Utility Model Content

[0004] Purpose of the utility model: to provide an FT test circuit for an audio chip, which solves the above-mentioned problems existing in the prior art.

[0005] Technical solution: An FT test circuit for an audio chip, comprising a power supply module, wherein the input end of the power supply module is connected to the output end of a host computer, the power supply output end of the power supply module is connected to the power supply input end of a main control subcircuit, the power supply input end of a current test subcircuit, the power supply input end of an IIS test subcircuit, and the power supply input end of an audio analysis subcircuit, and power is supplied to the main control subcircuit, the current test subcircuit, the IIS test subcircuit, and the audio analysis subcircuit. The output end of the host computer controls the connection to the input end of the main control subcircuit, the output end of the main control subcircuit is connected to the input end of a chip to be tested, the output end of the current test subcircuit is connected to the chip to be tested, and the working current of the chip to be tested is obtained through the current test subcircuit. The IIS test subcircuit is connected to the digital audio interface of the chip to be tested, the output end of the audio analysis subcircuit is simultaneously connected to the input end of the audio ADC interface of the chip to be tested and the input end of the host computer, and the input end of the audio analysis subcircuit is connected to the output end of the audio DAC interface of the chip to be tested.

[0006] Preferably, the main control subcircuit includes a communication interface, an efuse burning interface, an IIS power enable interface and a power enable interface of the chip to be tested, the communication interface is connected to the communication interface communication interface A of the chip to be tested, the efuse burning interface is connected to the efuse interface of the chip to be tested, the IIS power enable interface is connected to the input end of the IIS test subcircuit, and the power enable interface of the chip to be tested is connected to the power supply interface of the chip to be tested.

[0007] Preferably, it also includes a point cloud reference subcircuit, which is connected to the ADC interface of the chip to be tested and is used to calibrate the ADC power supply voltage and core operating voltage of the chip to be tested. The point cloud reference subcircuit includes a voltage regulator U10, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a resistor R84, a resistor R102, a capacitor C83, a capacitor C32 and a capacitor C34. One end of the capacitor C83 is connected to pin 1 of the voltage regulator U10, and the other end is grounded. One end of the resistor R102 is connected to pin 3 of the voltage regulator U10, and the other end is grounded. The resistor R80, the resistor R81, the resistor R82, the resistor R83 and the resistor R84 are connected in series with each other. The other end of the resistor R80 is simultaneously connected to pin 5 of the voltage regulator U10, one end of the capacitor C32 and one end of the capacitor C34. The other end of the capacitor C32 is simultaneously connected to the resistor R81 and pin 4 of the voltage regulator U10. The other end of the capacitor C34 is connected to the other end of the resistor R83 and is grounded.

[0008] Preferably, the system further comprises a frequency calibration module, which is connected to the OSC interface of the chip to be tested and is used to calibrate the OSC of the chip to be tested.

[0009] Preferably, the chip U1 in the main control sub-circuit is a CA51 chip.

[0010] Preferably, the voltage stabilizer U10 is a 2032-ADJ type voltage stabilizer.

[0011] Beneficial effects: The utility model relates to an FT test circuit for audio chips, which realizes full-process automated testing of audio chips, reduces the complexity of chip function and performance testing, and improves test efficiency. At the same time, data is uploaded to the server, which can record chip-related test data and statistically analyze test yields. The data can accurately find the test sites corresponding to the adverse phenomena during the test, and the system test board can be transplanted to a general machine for use, without the need to customize and develop a new test machine. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a system block diagram of the utility model;

[0013] Figure 2 The local circuit of the utility model Figure 1 ;

[0014] Figure 3 The local circuit of the utility model Figure 2 . DETAILED DESCRIPTION

[0015] like Figures 1 to 3As shown, the utility model provides a technical solution: an FT test circuit for an audio chip, comprising a power supply module, wherein the input end of the power supply module is connected to the output end of a host computer, and the power supply output end of the power supply module is connected to the power supply input end of a main control subcircuit, the power supply input end of a current test subcircuit, the power supply input end of an IIS test subcircuit, and the power supply input end of an audio analysis subcircuit, to supply power to the main control subcircuit, the current test subcircuit, the IIS test subcircuit, and the audio analysis subcircuit, and the output end of the host computer is controlled to be connected to the input end of the main control subcircuit, wherein, as Figure 2 As shown, the main control subcircuit includes a communication interface, an efuse burning interface, an IIS power enable interface and a power enable interface of the chip to be tested. The chip U1 in the main control subcircuit adopts a CA51 model chip. The communication interface is connected to the communication interface communication interface A of the chip to be tested, the efuse burning interface is connected to the efuse interface of the chip to be tested, the IIS power enable interface is connected to the input end of the IIS test subcircuit, the power enable interface of the chip to be tested is connected to the power supply interface of the chip to be tested, the OSC interface of the chip to be tested is connected to the frequency calibration module, and the frequency calibration module is used to calibrate the OSC of the chip to be tested. The output end of the current test subcircuit is connected to the chip to be tested, and the working current of the chip to be tested is obtained through the current test subcircuit. The IIS test subcircuit is connected to the digital audio interface of the chip to be tested, wherein the IIS test subcircuit is as shown in FIG. Figure 3 As shown, the output end of the audio analysis sub-circuit is connected to the input end of the audio ADC interface of the chip under test and the input end of the host computer at the same time, and the input end of the audio analysis sub-circuit is connected to the output end of the audio DAC interface of the chip under test.

[0016] In a further embodiment, Figure 2 As shown, it also includes a point cloud reference subcircuit, which is connected to the ADC interface of the chip to be tested and is used to calibrate the ADC power supply voltage and core operating voltage of the chip to be tested. The point cloud reference subcircuit includes a voltage regulator U10, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a resistor R84, a resistor R102, a capacitor C83, a capacitor C32 and a capacitor C34. The voltage regulator U10 adopts a 2032-ADJ type voltage regulator. One end of the capacitor C83 is connected to the lead of the voltage regulator U10. Pin 1, the other end is grounded, one end of the resistor R102 is connected to pin 3 of the voltage regulator U10, and the other end is grounded, the resistor R80, the resistor R81, the resistor R82, the resistor R83 and the resistor R84 are connected in series, the other end of the resistor R80 is simultaneously connected to pin 5 of the voltage regulator U10, one end of the capacitor C32 and one end of the capacitor C34, the other end of the capacitor C32 is simultaneously connected to the resistor R81 and pin 4 of the voltage regulator U10, the other end of the capacitor C34 is connected to the other end of the resistor R83 and grounded.

[0017] Through the above technical solution, the utility model can achieve the following working process:

[0018] Power on the main control subcircuit, cooperate with the host computer to configure the test vector project for the main control subcircuit, and start the test at the same time. Burn the test program into the flash of the chip under test through the main control subcircuit. After burning, the chip under test communicates with the main control subcircuit through communication unit A, informing the main control subcircuit that the test can be started;

[0019] First, the main control subcircuit provides a reference voltage input to the ADC of the chip under test, and the chip under test performs self-calibration. After the self-calibration is completed, the main control subcircuit collects the VDD_CORE and VDD_ANA of the chip under test to determine whether the calibration is successful. If the calibration is successful, the next test station is carried out. Otherwise, the test is terminated and the test chip is judged as a NG chip.

[0020] When the calibration is successful, the main control sub-circuit provides a 1K square wave reference frequency to the IO of the chip under test, and the chip under test performs self-calibration. After the self-calibration is completed, the specific IO port outputs a low level for 200ms. The main control sub-circuit collects the IO low level time to determine whether the calibration is successful. If the calibration is successful, the next test station will be carried out. Otherwise, the test is terminated and the test chip is determined to be NG.

[0021] When the main control subcircuit successfully collects the IO low-level calibration, the main control subcircuit sends a command to put the chip under test into the normal state. The current sensing amplifier collects the current in the current state through the sampling resistor. The main control determines whether the current value is within the qualified range to determine whether the current indicator of the chip under test is qualified. If it is qualified, it proceeds to the next test station. Otherwise, the test is terminated and the test chip is determined to be NG.

[0022] When the current value is within the qualified range, the main control sub-circuit sends a command to the chip under test to perform a communication unit self-test. The communication unit transmits and receives data through IIC / SPI / UART, and then compares the data. If the data is consistent, it indicates that the test item has passed and the next station test will proceed. Otherwise, the test is terminated and the test chip is determined to be NG.

[0023] When the data is consistent, the main control sub-circuit sends an instruction to the IIS test module. The module sends a fixed known audio data through the standard protocol. After receiving the audio data, the chip under test performs self-consistency. If the data is consistent, it indicates that the test item has passed and the next test station is tested. Otherwise, the test is terminated and the test chip is judged as NG.

[0024] When the audio data is consistent, the main control subcircuit sends a test audio instruction to the host computer, which in turn sends the test instruction to the audio analyzer. The audio analyzer outputs a 1K@5mV sine wave to the ADC of the chip under test. At the same time, it collects the DAC of the chip under test after audio operation and calculates whether its SNR and THD+N values are within the qualified range to determine whether the audio performance indicators of the chip under test are qualified. If qualified, it proceeds to the next test station. Otherwise, the test is terminated and the test chip is determined to be NG.

[0025] When the audio performance is qualified, the main control sub-circuit writes key parameters such as the chip ID and voltage and frequency calibration values into the efuse of the chip under test to facilitate subsequent chip maintenance; after burning is completed, the main control chip reads the parameters in the efuse to see if they are correct and uploads these parameters to the server. The chip U1 in the main control sub-circuit burns the customized function into the flash of the chip under test, thus completing the entire test process.

[0026] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details of the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all fall within the scope of protection of the present invention.

Claims

1. A FT test circuit for an audio chip, characterized in that: The present invention comprises a power supply module, wherein the input end of the power supply module is connected to the output end of the host computer, the power supply output end of the power supply module is connected to the power supply input end of the main control subcircuit, the power supply input end of the current test subcircuit, the power supply input end of the IIS test subcircuit and the power supply input end of the audio analysis subcircuit, and supplies power to the main control subcircuit, the current test subcircuit, the IIS test subcircuit and the audio analysis subcircuit. The output end of the host computer controls the connection with the input end of the main control subcircuit, the output end of the main control subcircuit is connected to the input end of the chip to be tested, the output end of the current test subcircuit is connected to the chip to be tested, and the working current of the chip to be tested is obtained through the current test subcircuit. The IIS test subcircuit is connected to the digital audio interface of the chip to be tested, the output end of the audio analysis subcircuit is simultaneously connected to the input end of the audio ADC interface of the chip to be tested and the input end of the host computer, and the input end of the audio analysis subcircuit is connected to the output end of the audio DAC interface of the chip to be tested.

2. The FT test circuit for an audio chip according to claim 1, characterized in that: The main control subcircuit includes a communication interface, an efuse burning interface, an IIS power enable interface and a power enable interface of the chip to be tested. The communication interface is connected to the communication interface A of the chip to be tested, the efuse burning interface is connected to the efuse interface of the chip to be tested, the IIS power enable interface is connected to the input end of the IIS test subcircuit, and the power enable interface of the chip to be tested is connected to the power supply interface of the chip to be tested.

3. The FT test circuit for an audio chip according to claim 1, characterized in that: It also includes a point cloud reference subcircuit, which is connected to the ADC interface of the chip to be tested and is used to calibrate the ADC power supply voltage and core operating voltage of the chip to be tested. The point cloud reference subcircuit includes a voltage regulator U10, a resistor R80, a resistor R81, a resistor R82, a resistor R83, a resistor R84, a resistor R102, a capacitor C83, a capacitor C32 and a capacitor C34. One end of the capacitor C83 is connected to pin 1 of the voltage regulator U10, and the other end is grounded. One end of the resistor R102 is connected to pin 3 of the voltage regulator U10, and the other end is grounded. The resistor R80, the resistor R81, the resistor R82, the resistor R83 and the resistor R84 are connected in series with each other. The other end of the resistor R80 is simultaneously connected to pin 5 of the voltage regulator U10, one end of the capacitor C32 and one end of the capacitor C34. The other end of the capacitor C32 is simultaneously connected to the resistor R81 and pin 4 of the voltage regulator U10. The other end of the capacitor C34 is connected to the other end of the resistor R83 and is grounded.

4. The FT test circuit for an audio chip according to claim 1, characterized in that: It also includes a frequency calibration module, which is connected to the OSC interface of the chip to be tested and is used to calibrate the OSC of the chip to be tested.

5. The FT test circuit for an audio chip according to claim 1, characterized in that: The chip U1 in the main control sub-circuit adopts a CA51 chip.

6. The FT test circuit for an audio chip according to claim 3, characterized in that: The voltage regulator U10 is a 2032-ADJ type voltage regulator.

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