OSC power supply circuit, integrated OSC circuit and integrated circuit chip

Abstract

The utility model provides an OSC power supply circuit, an integrated OSC circuit and an integrated circuit chip, and the OSC power supply circuit comprises a current source module which is used for outputting a constant current; the circuit comprises a first PMOS tube, a first resistor, a second PMOS tube, a first NMOS tube, a second NMOS tube and a third NMOS tube. A power supply is provided for the OSC circuit through voltage division of the first PMOS tube, the first resistor, the second PMOS tube and the first NMOS tube, the voltage of the power supply is equal to the sum of voltage drops of the first resistor, the second PMOS tube and the first NMOS tube and is not affected by high-level voltage, the MOS tubes in the circuit work in a saturation region at the same time, the voltage needed by the MOS tubes is small, and even if the OSC power supply circuit works at low voltage, the OSC power supply circuit is not affected by high-level voltage. And the MOS tubes in the circuit can still work in a saturation region at the same time, so that the stability of the power supply is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and in particular to an OSC power supply circuit, an integrated OSC circuit and an integrated circuit chip. Background Art

[0002] Many electronic circuits require clock signals to function properly. Typically, integrated oscillator (OSC) circuits output clock signals to ensure the proper functioning of other electronic circuits. To ensure the proper functioning of the integrated OSC circuit, a power supply circuit is also required in addition to the main OSC circuit.

[0003] In the related art, there are a large number of NMOS tubes in the power supply circuit. If you want all NMOS tubes to work in the saturation region, you need to input a higher high-level voltage. That is to say, when the power supply circuit in the related art works at low voltage, it cannot output a stable voltage, which in turn affects the power supply to the OSC circuit.

[0004] It should be pointed out that the information disclosed in the background technology section of this application is only intended to deepen the understanding of the general background technology of this application, and should not be regarded as an admission or any form of implication that the information constitutes prior art already known to those skilled in the art. Utility Model Content

[0005] In view of this, the present application provides an OSC power supply circuit, an integrated OSC circuit and an integrated circuit chip, so as to solve the problem in the prior art that the power supply circuit cannot output a stable voltage when working at a low voltage, thereby affecting the power supply to the OSC circuit.

[0006] In a first aspect, an embodiment of the present application provides an OSC power supply circuit, comprising:

[0007] Current source module, used to output constant current;

[0008] a first PMOS transistor, wherein a source of the first PMOS transistor is used to connect to a high level, and a gate of the first PMOS transistor is electrically connected to the first output end of the current source module;

[0009] a first resistor, wherein a first end of the first resistor is electrically connected to the drain of the first PMOS transistor;

[0010] a second PMOS transistor, wherein a source of the second PMOS transistor is electrically connected to the second end of the first resistor, and a gate of the second PMOS transistor is electrically connected to a drain of the second PMOS transistor;

[0011] a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the drain of the second PMOS transistor, respectively, and a source of the first NMOS transistor is grounded;

[0012] a second NMOS transistor, wherein the drain of the second NMOS transistor is electrically connected to the second output end of the current source module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded;

[0013] a third NMOS transistor, wherein the gate of the third NMOS transistor is electrically connected to the drain of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor is grounded;

[0014] Wherein, the drain of the first PMOS tube is used to output power supply.

[0015] In the embodiment of the present application, a power supply is provided to the OSC circuit through voltage division by the first PMOS transistor, the first resistor, the second PMOS transistor, and the first NMOS transistor. The voltage of the power supply is equal to the sum of the voltage drops across the first resistor, the second PMOS transistor, and the first NMOS transistor, and is not affected by high-level voltages. Moreover, the voltage required for the MOS transistors in the circuit to operate simultaneously in the saturation region is relatively small. Even if the OSC power supply circuit operates at a low voltage, the MOS transistors in the circuit can still be ensured to operate simultaneously in the saturation region, thereby ensuring the stability of the power supply.

[0016] In a possible implementation, the first resistor is an adjustable resistor.

[0017] It can be understood that by adjusting the resistance value of the first resistor, the voltage drop across the first resistor can be adjusted, thereby adjusting the voltage of the power supply.

[0018] In a possible implementation, the OSC power supply circuit further includes:

[0019] a first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the third NMOS transistor;

[0020] a second resistor, wherein a first end of the second resistor is electrically connected to the second end of the first capacitor, and a second end of the second resistor is electrically connected to the drain of the second NMOS transistor;

[0021] a second capacitor, wherein a first end of the second capacitor is electrically connected to the gate of the first PMOS transistor, and a second end of the second capacitor is electrically connected to the drain of the first PMOS transistor;

[0022] A third capacitor, wherein a first end of the third capacitor is electrically connected to the drain of the first PMOS transistor, and a second end of the third capacitor is electrically connected to the drain of the second PMOS transistor.

[0023] In the embodiment of the present application, a resistor and a plurality of capacitors are provided to ensure the stability of the OSC power supply circuit, thereby ensuring that the OSC power supply circuit outputs a stable power supply.

[0024] In a second aspect, an embodiment of the present application provides an integrated OSC circuit, comprising:

[0025] The OSC power supply circuit according to any one of the first aspects, the power supply circuit being configured to output power supply;

[0026] An OSC circuit, wherein an input end of the OSC circuit is electrically connected to an output end of the OSC power supply circuit, and the OSC circuit is used to receive the power supply.

[0027] In a possible implementation, the OSC circuit includes:

[0028] A ring oscillator circuit is configured to receive the power supply and output a first clock signal.

[0029] In a possible implementation, the ring oscillator circuit includes:

[0030] X inverters are sequentially connected in series, an input end of the first inverter is electrically connected to an output end of the last inverter, and X is an odd number greater than or equal to 3.

[0031] In a possible implementation, the ring oscillator circuit further includes:

[0032] M inverters, the M inverters are sequentially connected in series, the input end of the first inverter is electrically connected to the output end of the first inverter among the X inverters, and the output end of the last inverter is electrically connected to the input end of the first inverter among the X inverters, where M is an odd number;

[0033] a third resistor, wherein a first end of the third resistor is electrically connected to an input end of a first inverter among the M inverters;

[0034] A fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the output end of the last inverter among the M inverters, and a second end of the fourth capacitor is electrically connected to the second end of the third resistor and the input end of the first direction device among the N inverters.

[0035] In an embodiment of the present application, a frequency control module is added between the output end of the last inverter among the N inverters and the input end of the first inverter among the N inverters to control the oscillation frequency of the ring oscillation circuit. Specifically, the frequency control module includes M inverters, a third resistor and a fourth capacitor.

[0036] In a possible implementation, the third resistor is an adjustable resistor.

[0037] It can be understood that the frequency of the ring oscillation circuit can be adjusted by adjusting the resistance of the third resistor.

[0038] In a possible implementation, the integrated OSC circuit further includes:

[0039] a level conversion module, wherein a first input end of the level conversion module is electrically connected to the output end of any one of the inverters in the ring oscillation circuit, and a second input end of the level conversion module is electrically connected to the input end of any one of the inverters;

[0040] Y inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the level conversion module, and the output end of the last inverter is used to output a second clock signal, and Y is greater than or equal to 1.

[0041] In an embodiment of the present application, the level of the first clock signal is converted from the level of the power supply to a high level through a level conversion module, and the clock signal after level conversion is input into Y inverters to output a second clock signal.

[0042] In a third aspect, an embodiment of the present application provides an integrated circuit chip, comprising:

[0043] The integrated OSC circuit according to any one of the second aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0045] Figure 1 A schematic diagram of the structure of an OSC power supply circuit in a related technology provided in an embodiment of the present application;

[0046] Figure 2 A schematic diagram of the structure of an OSC power supply circuit provided in an embodiment of the present application;

[0047] Figure 3A schematic structural diagram of another OSC power supply circuit provided in an embodiment of the present application;

[0048] Figure 4 A schematic structural diagram of an integrated OSC circuit provided in an embodiment of the present application;

[0049] Figure 5 A schematic structural diagram of a ring oscillator circuit provided in an embodiment of the present application;

[0050] Figure 6 A schematic structural diagram of an inverter provided in an embodiment of the present application;

[0051] Figure 7 A schematic structural diagram of another ring oscillator circuit provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of the structure of an output circuit provided in an embodiment of the present application;

[0053] Figure 9 A schematic diagram of the structure of a level conversion module provided in an embodiment of the present application;

[0054] Figure 10 This is a schematic structural diagram of another integrated OSC circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0056] It should be clear that the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0057] The terms used in the embodiments of the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise.

[0058] It should be understood that the term "and / or" as used herein simply describes a relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. Furthermore, the character " / " in this document generally indicates an "or" relationship between the associated objects.

[0059] Many electronic circuits require clock signals to function properly. Typically, integrated oscillator (OSC) circuits output clock signals to ensure the proper functioning of other electronic circuits. To ensure the proper functioning of the integrated OSC circuit, a power supply circuit is also required in addition to the main OSC circuit.

[0060] In the related art, there are a large number of NMOS tubes in the power supply circuit. If you want all NMOS tubes to work in the saturation region, you need to input a higher high-level voltage. That is to say, when the power supply circuit in the related art works at low voltage, it cannot output a stable voltage, which in turn affects the power supply to the OSC circuit.

[0061] For ease of understanding, an embodiment of the present application provides a structural schematic diagram of an OSC power supply circuit in related technology.

[0062] See also Figure 1 , is a structural diagram of an OSC power supply circuit in a related technology provided in an embodiment of the present application. Figure 1 As shown, the OSC power supply circuit includes NMOS transistors M1, M3 and M4, a PMOS transistor M2 and a current source Ip, wherein the gate of M1 is electrically connected to the output end of Ip, the drain of M1 is used to connect to a high level (i.e., a power supply voltage), the source of M2 is electrically connected to the source of M1, the gate of M2 is electrically connected to the drain of M2, the gate of M3 is electrically connected to the gate of M2 and the drain of M3 respectively, the source of M3 is grounded, the gate of M4 is electrically connected to the gate of M3, the drain of M4 is electrically connected to the output end of Ip, and the source of M4 is grounded. The node between the source of M1 and the source of M2 is the output end of the OSC power supply circuit, which is used to output power supply. Figure 1It can be seen that for the OSC power supply circuit to operate properly, all MOS transistors in the OSC power supply circuit must operate in the saturation region. In other words, the power supply voltage VDD must be ≥ Vgs(M1) + Vgs(M2) + Vgs(M3). In addition, if M1, M2, and M3 operate in the saturation region, the current source Ip must also operate properly. Because the current source Ip can be regarded as a MOS transistor when operating, the normal operation of the OSC power supply circuit requires a power supply voltage VDD ≥ Vgs(M1) + Vgs(M2) + Vgs(M3) + Vdsat(Mp), where Vdsat(Mp) is the saturation drain-source voltage of Ip. When the threshold of the MOS transistor is high, Vgs ≈ Vth. In other words, the power supply voltage VDD must be at least Vth(M1) + Vth(M2) + Vth(M3) + Vdsat(Mp). Normally, the Vth of a MOS tube is about 0.6V, so the power supply voltage VDD must be at least 1.8V+Vdsat(Mp). When the power supply voltage of the OSC power supply circuit is high (for example, 3.3V), Figure 1 The OSC power supply circuit shown can work normally, but when the power supply voltage of the OSC power supply circuit is low (for example, 1.5V or 1.2V), Figure 1 The OSC power supply circuit shown obviously cannot work properly. That is, when the OSC power supply circuit in the related art works at low voltage, it cannot output a stable voltage, thereby affecting the power supply to the OSC circuit.

[0063] To address the aforementioned issues, embodiments of the present application provide an OSC power supply circuit, an integrated OSC circuit, and an integrated circuit chip. These circuits provide power to the OSC circuit through voltage division by a first PMOS transistor, a first resistor, a second PMOS transistor, and a first NMOS transistor. The power supply voltage is equal to the sum of the voltage drops across the first resistor, the second PMOS transistor, and the first NMOS transistor, and is unaffected by high-level voltages. Furthermore, the voltage required for the MOS transistors in the circuit to operate simultaneously in their saturation regions is relatively low. Even when the OSC power supply circuit operates at a low voltage, the MOS transistors in the circuit can still operate simultaneously in their saturation regions, thereby ensuring the stability of the power supply. This will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] See also Figure 2 , is a structural diagram of an OSC power supply circuit provided in an embodiment of the present application. Figure 2 As shown, the OSC power supply circuit 200 includes a current source module IDC, a first PMOS transistor MP1, a first resistor R1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3. Figure 2As shown, a current source module is used to output a constant current; the source of the first PMOS transistor is used to connect to a high level, and the gate of the first PMOS transistor is electrically connected to the first output terminal of the current source module; the first end of the first resistor is electrically connected to the drain of the first PMOS transistor; the source of the second PMOS transistor is electrically connected to the second end of the first resistor, and the gate of the second PMOS transistor is electrically connected to the drain of the second PMOS transistor; the gate of the first NMOS transistor is electrically connected to the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the drain of the second PMOS transistor, respectively, and the source of the first NMOS transistor is grounded; the drain of the second NMOS transistor is electrically connected to the second output terminal of the current source module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded; the gate of the third NMOS transistor is electrically connected to the drain of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor is grounded; wherein the drain of the first PMOS transistor is used to output power supply. It should be pointed out that in order to more clearly illustrate the circuit structure of the OSC power supply circuit, some related circuits are not shown in the figure.

[0065] Specifically, in the embodiment of the present application, if the OSC power supply circuit is to operate normally, that is, the MOS transistor in the circuit operates in the saturation region, then VDD must be ≥ Vdsat(MP1)+Vgs(MP2)+Vgs(MN1)+Vdsat(IDC). It can be understood that Vdsat(MP1) is much smaller than Vgs(MP1), and in the embodiment of the present application, the width-to-length ratio of the first PMOS transistor is large, and Vdsat is very small (only tens of millivolts). Therefore, even if the power supply voltage VDD is low (for example, 1.5V), the OSC power supply circuit can operate normally, thereby outputting a stable power supply.

[0066] When the OSC power supply circuit operates normally, the first PMOS transistor is turned on, and the current source module provides a constant current I1 to the third NMOS transistor and a constant current I2 to the second NMOS transistor. Because the second NMOS transistor and the first NMOS transistor form a current mirror, the current in the branch where the first NMOS transistor is located is I2. Currents I1 and I2 can be the same or different. For example, I1 and I2 can be provided separately by a single current source module, or I1 can be provided by a first current source module and I2 by a second current source module. Those skilled in the art can adjust the number of current source modules and the magnitudes of currents I1 and I2 based on actual needs.

[0067] When the OSC power supply circuit operates normally, the current provided by the first PMOS transistor is divided into two parts: the current supplied by the power supply and the current supplied by the first resistor, the second PMOS transistor, and the first NMOS transistor. These two parts have the same voltage, so the power supply voltage VDD_OSC is actually: VDD_OSC = I2 × R1 + Vgs(MP2) + Vgs(MN1). When R1 is 0, the power supply voltage VDD_OSC is minimum, i.e., VDD_OSC = Vgs(MP2) + Vgs(MN1). Since the power supply is output by the first PMOS transistor, the upper limit of the power supply voltage is VDD_OSC = VDD - Vdsat(MP1). Vdsat(MP1) is very low, only a few tens of millivolts. That is, in the embodiment of the present application, Vgs(MP2)+Vgs(MN1)≤VDD_OSC<VDD-Vdsat(MP1). Vgs(MP2)+Vgs(MN1) is relatively small, approximately 1.2V, and VDD-Vdsat(MP1) is approximately equal to VDD. Therefore, the voltage range of VDD_OSC is relatively wide. Because the OSC circuit draws current when oscillating, which affects the OSC circuit voltage, a wide VDD_OSC voltage range can suppress the effect of the OSC circuit's current draw on the OSC circuit voltage, thereby ensuring a relatively stable power supply output by the OSC power supply circuit.

[0068] In one possible implementation, the first resistor is an adjustable resistor. As described above, the power supply voltage VDD_OSC is actually: VDD_OSC = I2 × R1 + Vgs(MP2) + Vgs(MN1). The user can control the power supply voltage VDD_OSC by adjusting the resistance of the first resistor R1.

[0069] While the OSC power supply circuit outputs a relatively stable power supply, in some cases, the power supply voltage can fluctuate significantly. For example, when the OSC circuit is first activated, it draws a large current, causing the power supply voltage to drop significantly. In this embodiment, a third NMOS transistor is added to create a negative feedback loop in the OSC power supply circuit.

[0070] Specifically, when the power supply voltage drops significantly, the voltage of the branch containing the first resistor, the second PMOS transistor, and the first NMOS transistor decreases because the power supply voltage is the same as the voltage of the branch containing the first resistor, the second PMOS transistor, and the first NMOS transistor. In other words, the gate voltage of the second NMOS transistor decreases. Because the gate and drain voltages of a MOS transistor change in opposite directions, the drain voltage of the second NMOS transistor (i.e., the gate of the third NMOS transistor) increases, and the drain voltage of the third NMOS transistor (i.e., the gate of the first PMOS transistor) decreases. Because the conduction between the drain and source electrodes increases when the PMOS transistor gate voltage decreases, a higher power supply voltage can be provided, thereby ensuring the stability of the power supply.

[0071] In one possible implementation, the OSC circuit is composed of multiple inverters of the same specifications, each of which is composed of a PMOS transistor and an NMOS transistor. In the embodiment of the present application, the second PMOS transistor in the OSC power supply circuit has the same specifications as the PMOS transistor in the inverter, and the first NMOS transistor has the same specifications as the NMOS transistor in the inverter. It is understandable that when any MOS transistor in the inverter of the OSC circuit is affected by temperature or process, causing the Vth to change, it may cause VDD_OSC to change. However, since the second PMOS transistor and the first NMOS transistor in the OSC power supply circuit have the same specifications as the MOS transistor in the inverter, the Vth change of the second PMOS transistor and the first NMOS transistor is the same as the Vth change of the MOS transistor in the inverter, thereby offsetting the effects of temperature and process on VDD_OSC. For example, when the internal resistance of the inverter in the OSC circuit decreases due to the process corner, the oscillation frequency of the OSC circuit increases. Because the second PMOS transistor and the first NMOS transistor are manufactured using the same process as the MOS transistor in the inverter, their resistance also decreases, thereby reducing the power supply voltage VDD_OSC and, in turn, the oscillation frequency of the OSC circuit. Therefore, the OSC power supply circuit can ensure a stable power supply output under all process, voltage, and temperature (PVT) conditions.

[0072] The above embodiments are all about the OSC power supply circuit portion of the integrated OSC circuit. In the above embodiments, power supply is provided to the OSC circuit through voltage division by the first PMOS transistor, the first resistor, the second PMOS transistor, and the first NMOS transistor. The voltage of the power supply is equal to the sum of the voltage drops across the first resistor, the second PMOS transistor, and the first NMOS transistor, and is not affected by high-level voltages. Moreover, the voltage required for the MOS transistors in the circuit to operate simultaneously in the saturation region is relatively low. Even if the OSC power supply circuit operates at a low voltage, the MOS transistors in the circuit can still be ensured to operate simultaneously in the saturation region, thereby ensuring the stability of the power supply.

[0073] In a possible implementation, in order to ensure the stability of the OSC power supply circuit, a resistor and multiple capacitors are provided in the OSC power supply circuit.

[0074] See also Figure 3 , is a structural diagram of another OSC power supply circuit provided in an embodiment of the present application. Figure 3 As shown, the OSC power supply circuit is Figure 2 The OSC power supply circuit shown in FIG. 1 further includes: a first capacitor C1, a second resistor R2, a second capacitor C2, and a third capacitor C3. A first end of the first capacitor is electrically connected to the gate of the third NMOS transistor; a first end of the second resistor is electrically connected to the second end of the first capacitor, and a second end of the second resistor is electrically connected to the drain of the second NMOS transistor; a first end of the second capacitor is electrically connected to the gate of the first PMOS transistor, and a second end of the second capacitor is electrically connected to the drain of the first PMOS transistor; a first end of the third capacitor is electrically connected to the drain of the first PMOS transistor, and a second end of the third capacitor is electrically connected to the drain of the second PMOS transistor.

[0075] It can be understood that the series connection of the first capacitor and the second resistor can separate the poles of the second NMOS transistor and the third NMOS transistor, and can prevent voltage mutations and absorb overvoltages in the peak state. The second capacitor is the feedforward path of the power supply VDD_OSC. In the time domain, through the charge pump effect, the drain voltage and gate voltage of the first PMOS transistor change in the same direction. For example, when the OSC circuit causes VDD_OSC to drop due to oscillation, the voltage of the second capacitor drops synchronously due to the charge pump effect, thereby causing the gate voltage of the first PMOS transistor to decrease. The first PMOS transistor is quickly turned on, quickly pulling up VDD_OSC, and vice versa. The third capacitor is a zero-point capacitor used to compensate for the phase shift introduced by the feedback circuit.

[0076] The above embodiments are all about the OSC power supply circuit part of the integrated OSC circuit. The integrated OSC circuit includes an OSC circuit in addition to the OSC power supply circuit.

[0077] See also Figure 4 , is a schematic diagram of the structure of an integrated OSC circuit provided in an embodiment of the present application. Figure 4 As shown, the integrated OSC circuit includes an OSC power supply circuit 200 and an OSC circuit 400. The input end of the OSC circuit 400 is electrically connected to the output end of the OSC power supply circuit 200. The OSC power supply circuit 200 is configured to output power, and the OSC circuit 400 is configured to receive power. The OSC power supply circuit 400 includes a ring oscillator circuit 4001, which is configured to receive power and output a first clock signal.

[0078] In one possible implementation, the ring oscillator circuit includes X inverters, which are sequentially connected in series, with the input of the first inverter electrically connected to the output of the last inverter, where X is an odd number greater than or equal to 3. For ease of understanding, the following detailed description is given using X=3 as an example.

[0079] See also Figure 5 , is a schematic diagram of the structure of a ring oscillator circuit provided in an embodiment of the present application. Figure 5 As shown, the ring oscillator circuit 4001 includes: a first inverter MC1, a second inverter MC2 and a third inverter MC3. The first inverter, the second inverter and the third inverter are connected in series, and the input end of the first inverter (the first inverter) is electrically connected to the output end of the last inverter (the third inverter). It can be understood that the three inverters form a closed loop to achieve an alternating oscillation output with a fixed frequency. The input end of the ring oscillator circuit is electrically connected to the output end of the OSC power supply circuit. The power supply VDD_OSC output by the OSC power supply circuit provides power for the three inverters. In the embodiment of the present application, the output end of the third inverter is the output of the ring oscillator circuit. It should be noted that the node between any two of the three inverters can be used as the output end of the ring oscillator circuit.

[0080] For ease of understanding, an embodiment of the present application further provides a structural diagram of an inverter.

[0081] See also Figure 6 , is a schematic diagram of the structure of an inverter provided in an embodiment of the present application. Figure 6 As shown, the inverter MC is composed of a PMOS transistor and an NMOS transistor, and the source of the PMOS transistor is used to connect to a high level, which can be a power supply voltage or a power supply voltage. The gate of the NMOS transistor is electrically connected to the gate of the PMOS transistor, the drain of the NMOS transistor is electrically connected to the drain of the PMOS transistor, and the source of the NMOS transistor is grounded. The node between the gate of the PMOS transistor and the gate of the NMOS transistor is the input end of the inverter, and the node between the drain of the PMOS transistor and the drain of the NMOS transistor is the output end of the inverter.

[0082] In one possible implementation, the ring oscillator circuit also includes a frequency adjustment module, which includes: M inverters (M is an odd number), a resistor, and a capacitor. The M inverters are connected in series, with the input of the first inverter electrically connected to the output of the first inverter among the X inverters, and the output of the last inverter electrically connected to the input of the first inverter among the X inverters, where M is an odd number; the first end of the resistor is electrically connected to the input of the first inverter among the M inverters; the first end of the capacitor is electrically connected to the output of the last inverter among the M inverters, and the second end of the capacitor is electrically connected to the second end of the capacitor. The following describes a ring oscillator circuit with a frequency adjustment module in detail, taking one inverter as an example.

[0083] Specifically, see Figure 7 , is a schematic diagram of the structure of another ring oscillator circuit provided in an embodiment of the present application. Figure 7 As shown, in Figure 5 Based on the ring oscillator circuit shown, Figure 7 The ring oscillator circuit shown further includes: a fourth inverter MC4, a third resistor R3, and a fourth capacitor C4. The input end of the fourth inverter is electrically connected to the output end of the first inverter, the first end of the third resistor is electrically connected to the input end of the fourth inverter, the first end of the fourth capacitor is electrically connected to the output end of the fourth inverter, and the second end of the fourth capacitor is electrically connected to the second end of the third resistor and the input end of the first direction indicator of the N inverters.

[0084] In a possible implementation, the third resistor is an adjustable resistor. It is understandable that the oscillation frequency of the ring oscillation circuit can be adjusted by adjusting the resistance of the third resistor.

[0085] It should be noted that the OSC circuit cannot directly output the first clock signal. Therefore, the integrated OSC circuit in the embodiment of the present application also includes an output circuit, which is used to receive the first clock signal output by the OSC circuit and output the second clock signal or the third clock signal. This is described in detail below with reference to the accompanying drawings and specific embodiments.

[0086] In one possible implementation, the integrated OSC circuit includes a level conversion module and Y inverters. The first input of the level conversion module is electrically connected to the output of any inverter in the ring oscillator circuit, and the second input of the level conversion module is electrically connected to the input of the inverter. The Y inverters are connected in series, with the input of the first inverter electrically connected to the output of the level conversion module, and the output of the last inverter being used to output the second clock signal. Y is greater than or equal to 1. A detailed description is given below using Y being 1 as an example.

[0087] See also Figure 8, is a schematic diagram of the structure of an output circuit provided in an embodiment of the present application. Figure 8 As shown, the integrated OSC circuit further includes a level conversion module 800 and an eighth inverter MC8. A first input terminal of the level conversion module is electrically connected to the output terminal of any inverter in the ring oscillation circuit, a second input terminal of the level conversion module is electrically connected to the input terminal of the inverter, an input terminal of the eighth inverter is electrically connected to the output terminal of the level conversion module, and an output terminal of the eighth inverter is used to output the second clock signal.

[0088] In a possible implementation, the level conversion module includes two NMOS transistors and two PMOS transistors.

[0089] Specifically, see Figure 9 , is a schematic diagram of the structure of a level conversion module provided in an embodiment of the present application. Figure 9 As shown, the level conversion module 800 includes a seventh NMOS transistor MN7 , an eighth NMOS transistor MN8 , a tenth PMOS transistor MP10 , and an eleventh PMOS transistor MP11 . The gate of the seventh NMOS transistor is electrically connected to the output terminal of any inverter in the ring oscillator circuit, and the source of the seventh NMOS transistor is grounded; the gate of the eighth NMOS transistor is electrically connected to the input terminal of any inverter, and the source of the eighth NMOS transistor is grounded; the gate of the tenth PMOS transistor is electrically connected to the drain of the seventh NMOS transistor, the drain of the tenth PMOS transistor is electrically connected to the drain of the seventh NMOS transistor, and the source of the tenth PMOS transistor is connected to a high level; the gate of the eleventh PMOS transistor is electrically connected to the gate of the tenth PMOS transistor, the drain of the eleventh PMOS transistor is electrically connected to the drain of the eighth NMOS transistor, and the source of the eleventh PMOS transistor is connected to a high level; the gate of the seventh NMOS transistor is a first input terminal of the level conversion module, the gate of the eighth NMOS transistor is a second input terminal of the level conversion module, and the node between the drain of the eighth NMOS transistor and the drain of the eleventh PMOS transistor is an output terminal of the level conversion module.

[0090] See also Figure 10 , which is a schematic diagram of the structure of another integrated OSC circuit provided in an embodiment of the present application. The integrated OSC circuit provided in an embodiment of the present application provides power supply for the OSC circuit through voltage division by a first PMOS transistor, a first resistor, a second PMOS transistor, and a first NMOS transistor. The voltage of the power supply is equal to the sum of the voltage drops across the first resistor, the second PMOS transistor, and the first NMOS transistor, and is not affected by high-level voltages. Furthermore, the voltage required for the MOS transistors in the circuit to operate simultaneously in the saturation region is relatively low. Even when the OSC power supply circuit operates at a low voltage, the MOS transistors in the circuit can still operate simultaneously in the saturation region, thereby ensuring the stability of the power supply.

[0091] In the embodiments of the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0092] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments disclosed herein can be implemented using a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0093] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0094] In the several embodiments provided in this application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of this application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store program code.

[0095] In this specification, reference can be made to the same or similar parts between the various embodiments. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. An OSC power supply circuit, characterized in that: include: Current source module, used to output constant current; a first PMOS transistor, wherein a source of the first PMOS transistor is used to connect to a high level, and a gate of the first PMOS transistor is electrically connected to the first output end of the current source module; a first resistor, wherein a first end of the first resistor is electrically connected to the drain of the first PMOS transistor; a second PMOS transistor, wherein a source of the second PMOS transistor is electrically connected to the second end of the first resistor, and a gate of the second PMOS transistor is electrically connected to a drain of the second PMOS transistor; a first NMOS transistor, wherein a gate of the first NMOS transistor is electrically connected to the drain of the first NMOS transistor, the gate of the second PMOS transistor, and the drain of the second PMOS transistor, respectively, and a source of the first NMOS transistor is grounded; a second NMOS transistor, wherein the drain of the second NMOS transistor is electrically connected to the second output end of the current source module, the gate of the second NMOS transistor is electrically connected to the gate of the first NMOS transistor, and the source of the second NMOS transistor is grounded; a third NMOS transistor, wherein the gate of the third NMOS transistor is electrically connected to the drain of the second NMOS transistor, the drain of the third NMOS transistor is electrically connected to the gate of the first PMOS transistor, and the source of the third NMOS transistor is grounded; Wherein, the drain of the first PMOS tube is used to output power supply.

2. The circuit according to claim 1, wherein: The first resistor is an adjustable resistor.

3. The circuit according to claim 1, wherein: The OSC power supply circuit further includes: a first capacitor, wherein a first end of the first capacitor is electrically connected to the gate of the third NMOS transistor; a second resistor, wherein a first end of the second resistor is electrically connected to the second end of the first capacitor, and a second end of the second resistor is electrically connected to the drain of the second NMOS transistor; a second capacitor, wherein a first end of the second capacitor is electrically connected to the gate of the first PMOS transistor, and a second end of the second capacitor is electrically connected to the drain of the first PMOS transistor; A third capacitor, wherein a first end of the third capacitor is electrically connected to the drain of the first PMOS transistor, and a second end of the third capacitor is electrically connected to the drain of the second PMOS transistor.

4. An integrated OSC circuit, characterized in that: include: The OSC power supply circuit according to any one of claims 1 to 3, wherein the power supply circuit is used to output power supply; An OSC circuit, wherein an input end of the OSC circuit is electrically connected to an output end of the OSC power supply circuit, and the OSC circuit is used to receive the power supply.

5. The circuit according to claim 4, characterized in that The OSC circuit comprises: A ring oscillator circuit is configured to receive the power supply and output a first clock signal.

6. The circuit according to claim 5, characterized in that The ring oscillator circuit comprises: X inverters are sequentially connected in series, an input end of the first inverter is electrically connected to an output end of the last inverter, and X is an odd number greater than or equal to 3.

7. The circuit according to claim 6, characterized in that The ring oscillator circuit further includes: M inverters, the M inverters are sequentially connected in series, the input end of the first inverter is electrically connected to the output end of the first inverter among the X inverters, and the output end of the last inverter is electrically connected to the input end of the first inverter among the X inverters, where M is an odd number; a third resistor, wherein a first end of the third resistor is electrically connected to an input end of a first inverter among the M inverters; a fourth capacitor, wherein a first end of the fourth capacitor is electrically connected to the output end of the last inverter among the M inverters, and a second end of the fourth capacitor is electrically connected to the second end of the third resistor and the input end of the first inverter among the N inverters, respectively.

8. The circuit according to claim 7, characterized in that The third resistor is an adjustable resistor.

9. The circuit according to claim 7, characterized in that The integrated OSC circuit further includes: a level conversion module, wherein a first input end of the level conversion module is electrically connected to the output end of any one of the inverters in the ring oscillation circuit, and a second input end of the level conversion module is electrically connected to the input end of any one of the inverters; Y inverters are connected in series in sequence, the input end of the first inverter is electrically connected to the output end of the level conversion module, and the output end of the last inverter is used to output a second clock signal, and Y is greater than or equal to 1.

10. An integrated circuit chip, characterized in that: include: The integrated OSC circuit according to any one of claims 4 to 9.

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