Image sensing device

Abstract

The present application relates to an image sensing device in which the problem of forming a deep trench isolation structure suitable for a light detector having a small pitch is solved by a process in which a grid of trenches is etched from the front side using a high energy plasma and then annealed. The trench is filled with an oxide, and then etching is performed to recess the oxide. The trench groove is filled with a semiconductor to form a latticed semiconductor structure. After FEOL processing, BEOL processing, attachment to the second substrate, and thinning from the backside, the etching removes the oxide of the backside. The etching stops on the latticed semiconductor structure. The trench is then lined and filled from the back side. The front side etch allows the trench to narrow and have highly vertical sidewalls. Lining and filling from the backside to the trench provide good optoelectronic isolation.

Description

Technical Field

[0001] An embodiment of the present invention relates to an image sensing device. Background Art

[0002] Integrated circuits (ICs) containing image sensors are widely used in modern electronic devices such as cameras and mobile phones. Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) have become popular. Compared to charge-coupled devices (CCDs), CISs are increasingly popular due to their low power consumption, small pixel size, fast data processing speed, and low manufacturing cost. As pixel size decreases, manufacturing becomes increasingly difficult, and limiting crosstalk between pixels also becomes increasingly difficult. These are ongoing challenges, and unique solutions can provide improved performance. Utility Model Content

[0003] Some embodiments of the present invention provide an image sensing device, comprising: a semiconductor body having a first side and a second side opposite to the first side; an array of light sensing components located within the semiconductor body; a grid-like trench structure defined by an inner sidewall of the semiconductor body, extending from the second side and located between the light sensing components in the array; a grid-like semiconductor structure located between the light sensing components in the array and between the grid-like trench structure and the first side; a semiconductor island located between the grid-like semiconductor structure and the first side, wherein the semiconductor island is in contact with the semiconductor body; and a dielectric island located between the semiconductor island and the grid-like semiconductor structure.

[0004] In addition, other embodiments of the present invention provide an image sensing device, comprising: a semiconductor body having a first side and a second side opposite to the first side; an array of light sensing components located within the semiconductor body; a deep trench isolation structure extending from the second side to between the light sensing components in the array; a semiconductor structure aligned with a section of the deep trench isolation structure; a dielectric island aligned with the section of the deep trench isolation structure; and a floating diffusion region aligned with the section of the deep trench isolation structure; wherein the semiconductor structure is located between the dielectric island and the section; the dielectric island is located between the semiconductor structure and the floating diffusion region; and the floating diffusion region is arranged in the semiconductor body near the first side. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Various aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. In accordance with standard industry practice, features are not drawn to scale. Furthermore, the dimensions of various features within the various figures may be arbitrarily increased or decreased relative to each other for ease of illustration or to provide emphasis.

[0006] Figure 1 A cross-sectional view of an integrated circuit (IC) device according to some aspects of the present disclosure is shown.

[0007] Figure 2 According to some embodiments Figure 1 A plan view of the IC device.

[0008] Figure 3 Shown Figure 1 Another cross-sectional view of an IC device.

[0009] Figure 4 Shows Figure 1 Circuit diagram of the IC device.

[0010] Figure 5 A circuit diagram of an IC device according to some other embodiments is shown.

[0011] Figure 6 A cross-sectional view of an IC device according to another embodiment is shown.

[0012] Figure 7 A cross-sectional view of an IC device according to another embodiment is shown.

[0013] Figure 8-12 Shown are plan views of IC devices according to various other embodiments.

[0014] Figure 13-35 A series of cross-sectional views illustrating a process according to some embodiments are provided.

[0015] Figures 36-38 A series of cross-sectional views are provided showing Figure 13-35 Variations of the process.

[0016] Figure 39 A flow chart of a process according to some embodiments is provided. DETAILED DESCRIPTION

[0017] The present disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed directly at a junction, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be at a direct junction.

[0018] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature to another component or feature. As shown in the figures. These spatially relative terms are intended to encompass different orientations of the device or apparatus in use or operation in addition to the orientations depicted in the figures. The device or apparatus may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein may be interpreted accordingly. The terms "first," "second," "third," "fourth," and the like are merely general identifiers and, therefore, may be interchangeable in various embodiments. For example, while a component (e.g., an opening) may be referred to as a "first" component in some embodiments, in other embodiments the component may be referred to as a "second" component.

[0019] Some CIS designs are designed for backside illumination (BSI) and include a photodetector array within a semiconductor substrate. The photodetector pixels can be separated by a deep trench isolation (DTI) structure. The DTI structure can be either a backside deep trench isolation (BDTI) structure or a frontside deep trench isolation (FDTI) structure. The trenches of a BDTI structure are formed by etching from the backside of the semiconductor substrate and tend to narrow from the backside to the front side. The trenches of an FDTI structure are formed by etching from the front side and tend to narrow from the front side to the back side. The DTI structure can be in the form of a grid with segments located between adjacent photodetectors. It is preferable to make the grid segments narrower. Narrowing the grid segments increases the area available for light sensing.

[0020] BDTI structures provide good electrical and optical isolation, but their implementation can be costly in terms of front-side area due to challenges associated with landing trenches. For example, if shallow trench isolation (STI) structures are formed in the front side to land the trenches, the front-side area will be occupied by these structures. Additional front-side area is reserved to allow for misalignment between the structures formed on the front side and the trenches etched from the back side. This consumption of front-side area creates an obstacle to reducing pixel pitch.

[0021] According to some aspects of the present disclosure, the problem of forming a DTI structure suitable for photodetectors with a fine pitch is addressed through a process in which a first mask is formed and used to etch a grid of trenches from the front side of a semiconductor body. Etching can be performed at higher energies than from the back side, as substrate damage caused by the etching process can be repaired by annealing before forming the front-side structures, which limits the thermal budget. Using higher etch energies allows trenches with higher aspect ratios, resulting in narrower trenches.

[0022] After etching, the trench is filled with a sacrificial material. In some embodiments, the sacrificial material is an oxide. The sacrificial material is recessed into the trench through the etching process, and the resulting recess is filled with the first semiconductor. In some embodiments, the first semiconductor is polysilicon. In some embodiments, the first semiconductor is epitaxially grown in the trench. The first semiconductor deposited in the trench forms a grid-like semiconductor structure adjacent to the sacrificial material and provides an etch stop for subsequent processes, in which the sacrificial material is removed by etching from the backside.

[0023] In some embodiments, a second mask is formed and used to etch a hole extending through the grid-like semiconductor structure. In some embodiments, the hole is wider than the grid-like semiconductor structure. In some embodiments, the hole is formed at the intersection of the grid-like semiconductor structure. The hole is filled with a dielectric and then etched so that the remaining dielectric forms a dielectric island recessed in the hole. The upper portion of the hole is then filled with a second semiconductor to form a semiconductor island. In some embodiments, the second semiconductor is epitaxially grown in the hole. In some embodiments, the second semiconductor is polysilicon. The semiconductor island may be in direct contact with the semiconductor body. In some embodiments, the semiconductor island provides a floating diffusion region. The dielectric island below the semiconductor island reduces leakage current from the floating diffusion region. Setting the floating diffusion region directly above the trench can effectively utilize the front side area.

[0024] After front-end of line (FEOL) processing (which may include forming photodiodes and transfer gates) and back-end of line (BEOL) processing (including forming metal interconnect structures on the front side), the semiconductor body can be attached to one or more other substrates. The semiconductor body can then be thinned from the back side to at least the depth of the trench.

[0025] The sacrificial material is removed from the trench by etching from the backside and then filling the trench from the backside to form the DTI structure. The inner surfaces (sidewalls) of the semiconductor body defining the trench may have defects (e.g., dangling junctions) caused by the etching. If not mitigated, these defects may trap charge carriers (e.g., electrons) and cause unwanted leakage current to flow between adjacent pixel regions, resulting in dark current and / or white pixel issues. In some embodiments, filling the trench includes forming an epitaxial layer on the trench sidewalls. The epitaxial layer can repair etch damage. In some embodiments, filling the trench includes lining the trench with a high-K dielectric. The high-K dielectric can be formed above the epitaxial layer and also on the backside. The high-K dielectric passivates the defects by forming an electric field that accumulates holes along the sidewalls, thereby passivating the charge carriers (e.g., electrons). The remaining volume of the trench can be filled with one or more other dielectrics, such as an oxide. Filling the trench from the backside provides good electrical and optical isolation, similar to the effects achieved by the BDTI structure.

[0026] Some aspects of the present disclosure relate to integrated circuit devices. The integrated circuit device can be an image sensing device and can be manufactured using the aforementioned method. The image sensing device includes a semiconductor body and an array of light sensing components disposed within the semiconductor body. The semiconductor body has internal sidewalls that define a grid-like trench structure extending laterally from the second side (back side) of the semiconductor body and between the light sensing components. The sidewalls are vertical or angled so that the trench becomes narrower in the direction of the second side. In some embodiments, semiconductor islands adjacent to the first side (front side) of the semiconductor body are directly opposite to segments of the grid-like trench structure and are separated from the grid-like trench structure by corresponding dielectric islands. The semiconductor islands may be laterally surrounded by semiconductors of opposite doping types. In some embodiments, the semiconductor islands provide floating diffusion regions for adjacent light sensing components.

[0027] The grid-shaped semiconductor structure is disposed between the grid-shaped trench structure and the first side. The grid-shaped semiconductor structure separates the dielectric islands from the grid-shaped trench structure. In some embodiments, the grid-shaped semiconductor structure is polycrystalline silicon, etc. In some embodiments, the grid-shaped semiconductor structure is epitaxially grown semiconductor.

[0028] In some embodiments, the dielectric islands are wider than segments of the grid-like trench structure. In some embodiments, the semiconductor islands are wider than segments of the grid-like trench structure. In some embodiments, the semiconductor islands are opposite (directly above) the intersections of the grid-like trench structure. In some embodiments, the semiconductor islands are cross-shaped. In some embodiments, the semiconductor islands are opposite portions of the grid-like trench structure but between the intersections. In some embodiments, the semiconductor islands are rectangular and elongated along corresponding segments of the grid-like trench structure.

[0029] In some embodiments, the grid-like trench structure comprises an epitaxially grown semiconductor. In some embodiments, the grid-like trench structure comprises a high-K dielectric liner. In some embodiments, the high-K dielectric liner extends to the second side. In some embodiments, the grid-like trench structure is filled with a dielectric. In some embodiments, the dielectric filling the trenches is continuous with the dielectric layer on the second side.

[0030] Figure 1 A cross-sectional view of an integrated circuit (IC) device 100, which is an image sensor component, is provided. IC device 100 includes an array of photodiodes 135 within a semiconductor body 113. Semiconductor body 113 has inner sidewalls 133 defining a DTI structure 137. DTI structure 137 is grid-like and has segments extending from backside 119 or semiconductor body 113 to between photodiodes 135.

[0031] Semiconductor islands 157 are arranged adjacent to front side 111 segments of directly opposing semiconductor body 113 segments of DTI structure 137. A grid-like semiconductor structure 149 having substantially the same footprint as DTI structure 137 is disposed between semiconductor islands 157 and DTI structure 137. Dielectric islands 153 are located directly between semiconductor islands 157 and grid-like semiconductor structure 149.

[0032] Epitaxial layer 141 can provide inner sidewalls 133 that define DTI structure 137. In some embodiments, epitaxial layer 141 is indistinguishable from the rest of semiconductor body 113. In some embodiments, epitaxial layer 141 can be distinguished from the rest of semiconductor body 113 by composition or crystal structure. DTI structure 137 includes a high-K dielectric layer 143 lining inner sidewalls 133 and a dielectric core 145. High-K dielectric layer 143 and dielectric core 145 are continuous with layers of these same materials on backside 119.

[0033] DTI structure 137 has a width W1. In some embodiments, width W1 is approximately 100 nm or less. In some embodiments, width W1 is approximately 60 nm or less. In some embodiments, width W1 is in a range from approximately 30 nm to approximately 50 nm. These widths are relevant for DTI structure 137 to be narrow enough to maintain a large full well capacity and wide enough to suppress crosstalk.

[0034] The grid-like semiconductor structure 149 has a width W2. Width W2 is approximately equal to width W1 plus twice the thickness of epitaxial layer 141. In some embodiments, epitaxial layer 141 is not present and width W2 is approximately equal to width W1. In some embodiments, the thickness of epitaxial layer 141 is in a range from about 10 nm to about 100 nm. In some embodiments, the thickness of epitaxial layer 141 is in a range from about 20 nm to about 50 nm.

[0035] Dielectric island 153 has a width W3 that is equal to or greater than width W2. In some embodiments, width W3 is approximately equal to width W2. In some embodiments, width W3 is between 0% and about 100% greater than width W2. In some embodiments, width W3 is between 10% and about 50% greater than width W2. Width W4 can be approximately the same as width W3 or can be slightly greater than the slope of inner sidewalls 151 of semiconductor body 113 surrounding both dielectric island 153 and semiconductor island 157. In some embodiments, width W4 is within about 20% of width W3. In some embodiments, width W4 is within about 10% of width W3.

[0036] A majority of semiconductor body 113 may have p-type doping. Semiconductor island 157 may have n-type doping. N-well 159 may be adjacent to semiconductor island 157. Semiconductor island 157 and N-well 159 together may provide a floating diffusion region 205 capable of retaining charge. Transfer gate 163 may be configured to selectively transfer charge from photodiode 135 to semiconductor island 157. In some embodiments, transfer gate 155 is a vertical transfer gate. Vertical transfer gates facilitate reducing pixel pitch.

[0037] Figure 2 A plan view 200 of the IC device 100 is shown according to some embodiments. The plan view 200 focuses on structures near the front side 111 (see FIG. Figure 1 ). Figure 2 The line A-A' in Figure 1 The cross section of Figure 2 As shown, the grid-like semiconductor structure 149 includes segments 201 that intersect at intersections 203. Semiconductor islands 157 are located at intersections 203 in every other row and column of the grid, such that there is one floating diffusion 205 for every four photodetector pixels 209. The floating diffusion 205 includes the semiconductor islands 157 and the N-well 159. The floating diffusion 205 may also include an n-doped region 207 of the grid-like semiconductor structure 149. The grid-like semiconductor structure 149 is close to the front side 111 except where it is interrupted by the semiconductor islands 157.

[0038] Photodetector pixels 209 have a pitch P1. In some embodiments, pitch P1 ranges from about 0.2 μm to about 0.4 μm. In some embodiments, pitch P1 is about 0.3 μm or less. In some embodiments, pitch P1 is about 0.25 μm or less.

[0039] Figure 3 Shown is the corresponding Figure 2 sectional view of the IC device 100 taken along line BB'. Figure 3As shown, dielectric island 153 provides insulation on the underside of floating diffusion region 205. Charge can be retained in floating diffusion region 205 due to the n-type doping in semiconductor island 157 and n-doped region 207, relative to the p-type doping of mesh-like semiconductor structure 149 in the surrounding area.

[0040] return Figure 1 A metal interconnect structure 109 can be provided on the front side 111. The metal interconnect structure 109 includes metal lines 171 arranged in multiple metallization layers interconnected by vias 175 and surrounded by an interlayer dielectric 173. Contacts 162 couple the metal lines 171 to the transfer gates 163, and contacts 161 couple the metal lines 171 to the semiconductor islands 157. Contacts 170 can also be provided to couple the metal lines 171 to the mesh-like semiconductor structure 149. A ground voltage or other bias voltage can be applied to the mesh-like semiconductor structure 149 through the contacts 170 to improve electrical isolation.

[0041] Semiconductor body 113 and metal interconnect structure 109 constitute first chip 168. First chip 168 can be bonded to second chip 183. Second chip 183 includes semiconductor substrate 105 and metal interconnect structure 107. Metal interconnect structure 107 includes metal lines 187 arranged in multiple metallization layers interconnected by vias 181 and surrounded by interlayer dielectric 185. Bond pads 179 on second chip 183 can be coupled to bond pads 177 on first chip 168 to provide communication between the two chips. Transistor 165 and other integrated circuit devices on second chip 183 can provide intra-pixel circuitry, which is repeated for each photodetector pixel 209 or each floating diffusion region 205. Transistor 165 can include, for example, a select gate, a source follower, and a reset gate. Placing the intra-pixel circuitry on second chip 183 facilitates reducing the pixel pitch on first chip 168.

[0042] Second chip 183 can be bonded to third chip 193. Third chip 193 includes semiconductor body 101 and metal interconnect structure 103. Metal interconnect structure 103 includes metal lines 199 arranged in multiple metallization layers interconnected by vias 197 and surrounded by interlayer dielectric 195. Through-substrate vias (TSVs) 189 can provide connections between metal lines 187 on second chip 183 and metal lines 199 on third chip 193. Transistors 167 and other circuit devices can be integrated on semiconductor body 101. Transistors 167 and other integrated circuit devices on third chip 193 can provide application-specific circuitry connected to the array of photodetector pixels 209.

[0043] Contact pads for connecting to external devices can be implemented in IC device 100 in a variety of ways. One option is to provide contact pads on the back side 119 of the first chip 168. The contact pads can be located in a peripheral area, which is outside the image sensing area shown in the figure. TSVs (not shown) passing through the semiconductor body 113 can provide a connection between the contact pads and the metal lines 171 of the metal interconnect structure 109. Another option is to provide contact pads on the back side of the third chip 193. TSVs (not shown) passing through the semiconductor body 101 can provide a connection between the contact pads on the back side of the third chip 193 and the contact pads on the metal lines 199 of the metal interconnect structure 103.

[0044] Figure 4 Provides the ability to Figure 1 FIG4 is a diagram of a circuit 400 implemented by an IC device 100. In circuit 400, a first chip 168 provides four photodiodes 135 coupled to a floating diffusion region 205. A second chip 183 provides a reset gate RST, a source follower SF, a select gate SEL, and / or other components in a pixel circuit 401. A third chip 193 provides an application specific integrated circuit (ASIC) 403. The floating diffusion region 205 on the first chip 168 is coupled to a structure on the second chip 183, including the source / drain region of the reset gate RST and the gate electrode of the source follower SF.

[0045] Figure 5 A diagram of a circuit 500 according to an alternative embodiment is provided. In this alternative embodiment, the reset gate RST, source follower SF, and select gate SEL are all provided on the first chip 168. Some or all of these transistors can be provided on the mesh-like semiconductor structure 149. The second chip 183 can provide the ASIC 403 and the third chip 193 can be eliminated.

[0046] Figure 6 A cross-sectional view of an IC device 600 is shown. Figure 1 The IC device 100 is different in that the grid-like semiconductor structure 149 is replaced by a grid-like semiconductor structure 649. The grid-like semiconductor structure 149 is made of polycrystalline silicon, etc., while the grid-like semiconductor structure 649 is made of epitaxially grown silicon (Si), etc. Compared to the grid-like semiconductor structure 149 made of polycrystalline silicon, the use of epitaxially grown semiconductor to form the grid-like semiconductor structure 649 makes it more suitable for providing transistor channels or source / drain regions.

[0047] Figure 7 A cross-sectional view of the IC device 700 is shown. Figure 6IC device 600 is shown except that semiconductor islands 157 of polysilicon or the like have been replaced by semiconductor islands 757 of epitaxially grown silicon (Si) or the like. Forming semiconductor islands 757 of epitaxially grown semiconductor makes it easier to uniformly dope them with dopants than semiconductor islands 157.

[0048] Figure 8 A plan view 800 of an IC device according to another embodiment is shown. In plan view 800, floating diffusion region 205 includes semiconductor island 857. Semiconductor island 857 is square, has the same width as segment 201, and is located at intersection 203. Semiconductor island 857 is smaller than semiconductor island 157 (see FIG. Figure 2 ). Smaller semiconductor islands can provide a more compact structure.

[0049] Figure 9 A plan view 900 of an IC device according to another embodiment is shown. In plan view 900, floating diffusion region 205 includes semiconductor island 957. Semiconductor island 957 is rectangular, has the same width as segment 201, and is located at intersection 203. Compared to semiconductor island 857, semiconductor island 957 is elongated (see FIG. Figure 8 ). The elongation allows the semiconductor islands 957 to be larger while remaining within the footprint of the grid-like semiconductor structure 149.

[0050] Figure 10 A plan view 1000 of an IC device according to another embodiment is shown. In plan view 1000, floating diffusion region 205 includes semiconductor island 1057. Semiconductor island 1057 is square, has the same width as segment 201, and is located between intersections 203 along segment 201. In this example, each floating diffusion region 205 serves two photodetector pixels 209 and has two associated transfer gates 155.

[0051] Figure 11 A plan view 1100 of an IC device according to another embodiment is shown. In plan view 1100, floating diffusion region 205 includes semiconductor island 1157. Semiconductor island 1157 is rectangular, has the same width as segment 201, and is located between intersections 203 along segment 201. Semiconductor island 1157 is elongated along corresponding segment 201. The elongation allows semiconductor island 1157 to be larger than semiconductor island 1057 (see FIG. 1 ). Figure 10 ).

[0052] Figure 12A plan view 1200 of an IC device according to another embodiment is shown. In plan view 1200, floating diffusion region 205 includes semiconductor island 1257. Semiconductor island 1257 is rectangular, wider than segment 201, and located between intersections 203 along segment 201. Making semiconductor island 1257 wider than segment 201 helps reduce variations in threshold voltage between transfer gates 163.

[0053] Figure 13-35 A series of cross-sectional views 1300-3500 are provided showing an integrated circuit device according to the present disclosure at various stages of fabrication according to a process according to the present disclosure. Figure 13-35 The present invention is described with respect to a series of actions, but it should be understood that in some cases, the order of the actions may be changed and that the series of actions may be applied to structures other than those shown. In some embodiments, some of the actions are omitted in whole or in part. In addition, Figure 13-35 It is described in terms of a series of actions. It should be understood that Figure 13-35 The structure shown in is not limited to the manufacturing method but can be independent as a structure separate from the method.

[0054] like Figure 13 As shown in the cross-sectional view 1300 of FIG, the method can begin by forming a mask 1301 on the front side 111 of the semiconductor body 113 and etching a grid of trenches 1303 using the mask 1301. The mask 1301 and other masks used throughout the process can be patterned by lithography, ion beam lithography, or any other suitable method. The mask 1301 can include a photoresist mask and a hard mask patterned using a photoresist mask. The semiconductor body 113 can be cut from a single crystal and can be any type of semiconductor, such as silicon (Si), a III-V group, some other binary semiconductor, a tertiary semiconductor (e.g., AlGaAs), a high-order semiconductor, or the like. In some embodiments, the semiconductor body 113 is or includes silicon (Si), etc.

[0055] The process of etching trench 1303 may include dry etching such as plasma etching. The plasma may include high-energy ions 1305, causing trench 1303 to be formed with substantially vertical sidewalls. In some embodiments, trench 1303 has an aspect ratio of 20:1 or greater. In some embodiments, trench 1303 has an aspect ratio of 25:1 or greater. In some embodiments, trench 1303 has an aspect ratio of 30:1 or greater. In some embodiments, mask 1301 is substantially removed by the etching process. Trench 1303 is etched to a depth D1 below front side 111. In some embodiments, depth D1 is in a range of about 7 μm to about 3 μm. In some embodiments, depth D1 is in a range of about 1 μm to about 3 μm. Depth D1 may be selected to be greater than the thickness that semiconductor body 113 will have after a subsequent chip thinning process.

[0056] like Figure 14 As shown in cross-sectional view 1400 of , the process can continue by filling trench 1303 with sacrificial material 1401. Sacrificial material 1401 is etch-sensitive compared to semiconductor body 113. In some embodiments, sacrificial material 1401 is one or more dielectric layers. In some embodiments, sacrificial material 1401 comprises an oxide. In some embodiments, the oxide is silicon dioxide (SiO2). Sacrificial material 1401 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable process. In some embodiments, the base layer of sacrificial material 1401 is formed by a thermal oxidation process. The thermal oxidation process can be used to remove damaged layers of semiconductor body 113 bordering trench 1303.

[0057] like Figure 15As shown in cross-sectional view 1500 in FIG, excess sacrificial material 1401 is removed from front side 111 and etched to recess sacrificial material 1401 below front side 111, leaving a grid of trenches 1501 above sacrificial material 1401. Removal of sacrificial material 1401 from front side 111 can be performed through a planarization process or through an etching process. The planarization process can be, for example, chemical mechanical polishing (CMP). Alternatively or additionally, removal of sacrificial material 1401 from front side 111 can be performed through an etching process. The etching process can be the same as the etching process used to recess sacrificial material 1401 below front side 111, or it can be a different etching process. The etching process can include wet etching, dry etching, or any other suitable process. Sacrificial material 1401 is etched to a depth D2 below front side 111. In some embodiments, depth D2 is in a range from approximately 20 nm to approximately 100 nm. In some embodiments, depth D2 is in a range from approximately 100 nm to approximately 800 nm. Depth D2 is much smaller than depth D1. In some embodiments, depth D2 is about 1 / 4 or less of depth D1.

[0058] like Figure 16 As shown in cross-sectional view 1600 , the process can continue by filling the grid of trenches 1501 with semiconductor 1601. In some embodiments, semiconductor 1601 is polysilicon or the like. Semiconductor 1601 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any other suitable process. In some embodiments, semiconductor 1601 has a p-type doping. The p-type doping in semiconductor 1601 can improve isolation between photodiode pixels.

[0059] like Figure 17 As shown in cross-sectional view 1700 in FIG. 1 , excess semiconductor 1601 is removed from front side 111. The remaining semiconductor 1601 forms a grid-like semiconductor structure 149. In some embodiments, the removal process is an etching process. In some embodiments, the removal process is a planarization process. The planarization process can be, for example, CMP.

[0060] like Figure 18As shown in cross-sectional view 1800 of FIG, a mask 1801 is formed and used to etch holes 1803 in front side 111. Holes 1803 are formed directly above mesh-like semiconductor structure 149. In some embodiments, holes 1803 are wider than mesh-like semiconductor structure 149. The etching process can be a dry etching method such as plasma etching, or any other suitable etching process. Holes 1803 are etched to a depth D3 below front side 111. In some embodiments, depth D3 is in a range from about 10 nm to about 60 nm. In some embodiments, depth D3 is in a range from about 60 nm to about 500 nm. Depth D3 is less than depth D2. In some embodiments, depth D3 is about 75% or less of depth D2. Depth D3 is selected relative to depth D2 so that a thickness D4 of mesh-like semiconductor structure 149 remaining between holes 1803 and sacrificial material 1401 is sufficient to provide an etch stop layer for subsequent processes that etch away sacrificial material 1401. In some embodiments, thickness D4 is in a range from about 10 nm to about 60 nm. In some embodiments, thickness D4 is in a range from about 60 nm to about 300 nm.

[0061] like Figure 19 As shown in cross-sectional view 1900 of FIG. 1 , dielectric 1901 is deposited to fill hole 1803. In some embodiments, dielectric 1901 is an oxide, etc. In some embodiments, dielectric 1901 is silicon dioxide (SiO2), etc. Dielectric 1901 can be deposited by PVD, CVD, ALD, etc., or any other suitable process.

[0062] like Figure 20 As shown in cross-sectional view 2000 of FIG. , a planarization process may be performed. The planarization process may be CMP, for example. In some embodiments, the planarization process stops on mask 1801. In some embodiments, the planarization process stops on front side 111. The remaining dielectric 1901 within hole 1803 forms dielectric islands 153. The planarization process improves the uniformity of the recess process in subsequent steps.

[0063] like Figure 21As shown in the cross-sectional view 2100 of , the dielectric island 153 is etched so that the dielectric island 153 is recessed below the front side 111 and the hole 2101 is formed directly above the dielectric island 153. The etching process can be wet etching, dry etching, etc. The hole 2101 is as wide as or slightly wider than the dielectric island 153. The etching process can thin or remove the mask 1801. The hole 2102 is etched to a depth D5 below the front side 111, leaving the dielectric island 153 with a thickness D5. In some embodiments, the depth D5 is in the range of about 1 nm to about 20 nm. In some embodiments, the depth D5 is in the range of about 20 nm to about 200 nm. In some embodiments, the depth D5 is about half of the depth D2 or less. The depth D5 can be selected based on the desired thickness of the semiconductor that will subsequently fill the hole 2102, which in turn can be related to factors such as the desired capacitance of the floating diffusion area 205 (see Figure 1 and Figure 2 In some embodiments, thickness D6 is in a range of about 10 nm to about 60 nm. In some embodiments, depth D6 is in a range of about 60 nm to about 300 nm. Thickness D5 is selected so that dielectric island 153 has sufficient thickness to limit leakage current between floating diffusion region 205 and mesh semiconductor structure 149.

[0064] like Figure 22 As shown in cross-sectional view 2200 of FIG1 , the process can continue by filling hole 2101 with semiconductor 2201. In some embodiments, semiconductor 2201 is polysilicon, etc. Semiconductor 2201 can be deposited by PVD, CVD, ALD, etc., or any other suitable process. In some embodiments, semiconductor 1601 is formed by epitaxial growth. In some embodiments, semiconductor 2201 has n-type doping. The n-type doping in semiconductor 2201 can provide PN junction isolation between semiconductor 2201 and adjacent semiconductors (e.g., semiconductor body 113 and mesh-like semiconductor structure 149).

[0065] like Figure 23 As shown in cross-sectional view 2300 in FIG, excess semiconductor 2201 has been removed from front side 111. Remaining semiconductor 2201 forms semiconductor island 157. In some embodiments, the removal process is an etching process. In some embodiments, the removal process is a planarization process. The planarization process can be, for example, CMP. The etching or CMP process can stop on mask 1801. In some embodiments, the etching or CMP process removes mask 1801. In some embodiments, the etching or CMP process stops on front side 111.

[0066] like Figure 24As shown in the cross-sectional view 2400 of FIG. 1 , ion doping may be performed to form the photodiode 135. The ion doping may include, for example, deep N-well doping, shallow p-well doping, etc. Some of these ion doping processes may be performed using a mask. In some embodiments, these ion doping processes form a p-well having a depth greater than or equal to depth D2. The p-well of this depth provides junction isolation for the mesh-like semiconductor structure 149.

[0067] like Figure 25 As shown in the cross-sectional view 2500 of FIG, a mask 2501 can be formed and used to etch holes 2503. Figure 26 As shown in cross-sectional view 2600 of FIG, mask 2501 can be stripped and gate stack 2605 can then be formed. Gate stack 2605 can include a gate dielectric layer 2601 and a gate electrode layer 2603. Gate stack 2605 fills hole 2503. Gate dielectric layer 2601 can be an oxide, or some other suitable material for a gate dielectric layer. Gate electrode layer 2603 can be polysilicon, or some other suitable material. These layers can be deposited by PVD, CVD, ALD, or any other suitable process.

[0068] like Figure 27 As shown in cross-sectional view 2700 of FIG. 2 , a mask 2701 may be formed and used to pattern transfer gates 163 including transfer gates 155 from gate stack 2605. Other transistors may also be defined from gate stack 2605 through this patterning process.

[0069] like Figure 28 As shown in cross-sectional view 2800 of FIG, spacers 2801 can be formed around transfer gate 163. Spacers 2801 can be formed by depositing a spacer material and then performing anisotropic etching. The spacer material can include one or more layers of any suitable dielectric. The spacer material can be or include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), a high-K dielectric material, etc. The spacer material can be deposited by ALD, CVD, PVD, etc., or any other suitable process.

[0070] like Figure 29 As shown in the cross-sectional view 2900 in FIG. 2 , a mask 2901 is formed and ions 2903 are doped to form an N-well 159. The N-well 159 may be aligned with the spacer 2801. In some embodiments, the ion doping process also imparts n-type doping to the semiconductor island 157. The ion doping process may also produce an n-doped region 207 (see FIG. 2 ) in the portion of the mesh-like semiconductor structure 149 adjacent to the semiconductor island 157. Figure 2 and Figure 3 ).

[0071] like Figure 30As shown in the cross-sectional view 3000 of FIG, the process can continue to form the metal interconnect structure 109 on the front side 111. In some embodiments, the metal interconnect structure 109 is formed using a damascene or dual damascene process. The metal line 171 and the via 175 may include one or more layers of copper (Cu), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), conductive carbides, oxides, alloys of these metals, etc., or any other suitable conductive material. One of these layers can be a diffusion barrier layer, such as titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), etc. The bonding pad 177 can be one of these compositions or different compositions. Similarly, the contacts 161, contacts 162 and contacts 170 can be one of these compositions or different compositions. In some embodiments, contacts 161 , 162 , and 170 are made of tungsten (W), cobalt (Co), cobalt silicide (CoSi 2 ), nickel (Ni), nickel silicide (NiSi), or alloys thereof. These materials can be deposited by electroplating, electroless plating, ALD, CVD, PVD, or any other suitable process.

[0072] The interlayer dielectric 173 may include one or more layers of silicon dioxide (SiO2), a low-K interlayer dielectric, or an ultra-low-K dielectric. A low-K dielectric refers to a material with a lower dielectric constant than silicon dioxide (SiO2). The dielectric constant of SiO2 is approximately 3.9. Examples of low-K dielectrics include organosilicate glass (OSG), such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica glass (FSG)), organic polymer low-K dielectrics, and porous silicate glass. An ultra-low-K dielectric is a material with a dielectric constant of approximately 2.1 or less. An ultra-low-K dielectric material is typically a low-K dielectric material that forms a porous structure. The porosity reduces the effective dielectric constant. The low-K interlayer dielectric 173 can be deposited by ALD, CVD, PVD, or any other suitable process. The semiconductor body 113 and the metal interconnect structure 109 constitute the first chip 168.

[0073] like Figure 31 As shown in cross-sectional view 3100 of FIG. 1 , first chip 168 may be flipped over and bonded to second chip 183. The bonding process may be oxide-to-oxide bonding, metal bonding, a combination thereof, or any other suitable bonding process. Second chip 183 may be bonded to third chip 193 before or after bonding to first chip 168.

[0074] like Figure 32As shown in cross-sectional view 3200 of FIG, after bonding, semiconductor body 113 can be thinner than backside 119. Thinning semiconductor body 113 allows light to more easily pass to photodiode 135. Thinning semiconductor body 113 can be performed by etching, mechanical grinding, CMP, or any other suitable process. In some embodiments, semiconductor body 113 is thinned to a thickness in a range from about 7 μm to about 3 μm. In some embodiments, semiconductor body 113 is thinned to a thickness in a range from about 1 μm to about 3 μm. The thinning process is performed at least to a point where sacrificial material 1401 is exposed on backside 119.

[0075] like Figure 33 As shown in the cross-sectional view 3300 of , an etching process is performed to remove the sacrificial material 1401, leaving trenches 3301. According to some embodiments, the etching process stops on the mesh-like semiconductor structure 149. The etching process can be dry etching, wet etching, etc. or any other suitable etching process.

[0076] like Figure 34 As shown in cross-sectional view 3400 of FIG301 , epitaxial layer 141 comprising a semiconductor can be grown on the sidewalls of trench 3301. Backside 119 can be masked or epitaxial layer 141 can be allowed to grow on backside 119. Epitaxial layer 141 increases inner sidewall 133, narrows trench 3301, and can passivate defects on inner sidewall 133. In some embodiments, epitaxial layer 141 has a p-type doping.

[0077] like Figure 35 As shown in the cross-sectional view 3500 of FIG. 3 , the trench 3301 may be lined with a high-K dielectric layer 143, which is then filled to provide a dielectric core 145. The high-K dielectric layer 143 may be, for example, hafnium oxide (H f O2), europium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), hafnium oxide aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), tantalum oxide aluminum oxide (HfO2-Al2O3), zirconium oxide (ZrO2), hafnium oxide (Ta2O5), aluminum oxide (Al2O3), yttrium oxide (Y2O3), lanthanum oxide (La2O3), titanium oxide (SrT i O3) and may have a thickness in the range of, for example, 5 to 50 angstroms. The high-k dielectric layer 143 may be deposited by ALD, CVD, PVD, or the like, or any suitable process. The dielectric core 145 may be an oxide, such as silicon oxide (SiO2), tantalum oxide (Ta2O5), or the like, and may be deposited by ALD, CVD, PVD, or the like, or any suitable process. Additional processing may be performed to provide a backside metal grid 125, color filters 123, and microlenses 121, thereby providing, for example, Figure 1 The structure of the IC device 100 is shown in FIG.

[0078] Figures 36-38 A variation of the aforementioned process is shown. Figure 36 As shown in the cross-sectional view 3600, it can be Figure 14 1400, in this variation, the mask 1301 remains in place while the trench 1303 is filled with sacrificial material 1401. Figure 37 As shown in cross-sectional view 3700 of , at least one layer of mask 1301 may remain in place after the process that causes the sacrificial material 1401 to be recessed below the front side 111. Figure 38 As shown in cross-sectional view 3800 of FIG. 1 , trenches 1501 are filled with semiconductor via an epitaxial growth process, thereby forming a grid-like semiconductor structure 649. In some embodiments, the grid-like semiconductor structure 649 is made of the same semiconductor type as the semiconductor body 113. In some embodiments, the grid-like semiconductor structure 649 is made of silicon (Si), for example. In some embodiments, the grid-like semiconductor structure 649 has p-type doping. The p-type doping in the grid-like semiconductor structure 649 can improve isolation between photodiode pixels.

[0079] Figure 39 A flow chart of a process 3900 for forming an image sensing device according to some embodiments is provided. Although process 3900 is shown and described below as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or concurrently with other actions or events than those shown and / or described herein. In addition, not all of the actions shown are required to implement one or more aspects or embodiments described herein. Furthermore, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0080] Process 3900 may begin with act 3901 by etching a deep trench in the front side of a semiconductor body. Figure 13 An example is provided in the cross-sectional view 1300 of FIG. The trenches exhibit a grid pattern defined by a hard mask. Etching can be performed using high energy plasma, making the trenches narrow and having steep sidewalls.

[0081] Action 3903 is annealing. This annealing process repairs the etching damage caused by the trench formation process. The annealing process can be performed at this stage of processing, or at a later stage before action 3927, which performs doping to form the photodiode.

[0082] Act 3905 fills the trench with oxide or other sacrificial material. Figure 14 Sectional view 1400 and Figure 36The 3600 provides an example.

[0083] Action 3909 is an etching process that causes the oxide or other sacrificial material used to fill the trench to become recessed into the trench. Figure 15 Sectional view 1500 and Figure 37 The 3700 provides an example.

[0084] Action 3911 is a deposition process that causes the grooves created by the etch back of action 3909 to be filled, thereby creating a grid-like semiconductor structure. Figure 16 Sectional view 1600 and Figure 38 The 3800 provides an example.

[0085] Action 3913 is an etch-back and / or planarization process that removes excess semiconductor material from the front side surface. Figure 17 An example is provided in cross-sectional view 1700. Any remaining portions of the hard mask used in the deep trench etch of act 3901 may be removed at this stage of processing.

[0086] Act 3915 is forming a second mask and etching holes through the mask. The holes are located directly above the grid-like semiconductor structure, such that the holes penetrate the grid-like semiconductor structure. In some embodiments, the holes are formed at intersections of the grid-like semiconductor structure. In some embodiments, the holes are wider than the segments of the grid-like semiconductor structure. Figure 18 The cross-sectional view 1800 provides an example.

[0087] Act 3917 is filling the hole with a dielectric (eg, oxide). Figure 19 The cross-sectional view 1900 provides an example.

[0088] Action 3919 is a planarization process that removes excess dielectric from previous deposition steps. Figure 20 The cross-sectional view 2000 provides an example.

[0089] Act 3921 is a dielectric etch back process that etches the dielectric deposited in act 3917 to create a recess corresponding to the upper portion of the hole etched in the process of act 3915 . Figure 21 An example is provided in cross-sectional view 2100 .

[0090] Action 3923 is to fill the groove with a semiconductor. In some embodiments, the semiconductor is polysilicon or some other semiconductor that can be deposited by PVD or CVD. In some embodiments, the semiconductor is epitaxially grown in the groove. Figure 22 An example is provided in cross-sectional view 2200 .

[0091] Action 3925 is an etch-back and / or planarization process that removes excess semiconductor material from the front side surface. The remaining semiconductor deposited in the previous step forms semiconductor islands. Figure 23 An example is provided in cross-sectional view 2300 .

[0092] Action 3927 includes one or more ion doping processes to form PN diodes separated laterally by the grid-like isolation structure formed in the previous step. The ion doping processes include at least one deep N-well doping process. In some embodiments, the ion doping process includes a shallow P-well doping process. Figure 24 An example is provided in cross-sectional view 2400 .

[0093] Action 3929 is etching trenches for the vertical transfer gates. Figure 25 An example is provided in cross-sectional view 2500 .

[0094] Action 3931 is to deposit and pattern a gate stack. The gate stack is deposited in the trench formed in the previous step. Figure 26 Cross-sectional view 2600 is provided to illustrate an example of the formation of a gate stack. Figure 27 Cross-sectional view 2700 of FIG. 2 is provided to illustrate an example of patterning of a gate stack.

[0095] Action 3933 is to form sidewall spacers around the gate. Figure 28 An example is provided in cross-sectional view 2800 .

[0096] Action 3935 is doping the source / drain region around the gate. Optionally, this doping provides n-type doping to the semiconductor island. Optionally, this doping extends to a portion of the mesh-like semiconductor structure bordering the semiconductor island. Figure 29 An example is provided in cross-sectional view 2900 .

[0097] Action 3939 is a BEOL process that forms a metal interconnect structure on the front side. The metal interconnect structure has contacts, semiconductor islands, and gate electrodes from action 3931. In some embodiments, the metal interconnect structure has contacts with a mesh-like semiconductor structure, where the contacts can be used to provide a ground voltage or bias voltage. Figure 30 The cross-sectional view 3000 provides an example.

[0098] Act 3941 is bonding one or more second substrates. Figure 31 An example is provided in cross-sectional view 3100 of FIG. 3943 . Thinning the semiconductor body from the backside exposes the oxide or other sacrificial material deposited in action 3905 . Figure 32 An example is provided in cross-sectional view 3200 .

[0099] Action 3945 is etching to remove oxide or other sacrificial material from the trenches. The etching process stops the grid-like semiconductor structure formed by action 3911. Figure 33 An example is provided in cross-sectional view 3300 .

[0100] Action 3947 is an optional step of epitaxially growing a semiconductor layer on the sidewalls of the trench. The epitaxial growth process can repair defects and narrow the trench. In some embodiments, the epitaxially grown semiconductor has p-type doping. Figure 34 An example is provided in cross-sectional view 3400 .

[0101] Act 3949 is to line the trench with a high-K dielectric layer. Act 3951 is to fill the trench with a dielectric material (such as oxide). Figure 35 The cross-sectional view 3500 provides an example.

[0102] Action 3953 is to form a backside metal grid. The backside metal grid may have segments corresponding to the trench isolation structures formed in the previous step. Action 3955 is to form color filters and microlenses. Figure 1 The IC device 100 provides an example of the final structure.

[0103] Some aspects of the present disclosure relate to an image sensing device comprising an array of light sensing elements within a semiconductor body having a first side and a second side. An inner sidewall of the semiconductor body defines a grid-like trench structure extending from the second side and positioned between the light sensing elements in the array. A grid-like semiconductor structure is positioned between the light sensing elements in the array. The grid-like semiconductor structure is also positioned between the grid-like trench structure and the first side. A semiconductor island is positioned between the grid-like semiconductor structure and the first side. The semiconductor island is in direct contact with the semiconductor body. A dielectric island is positioned between the semiconductor island and the grid-like semiconductor structure.

[0104] In some embodiments of the present invention, the grid-shaped semiconductor structure comprises polysilicon.

[0105] In some embodiments of the present invention, the semiconductor island comprises polysilicon.

[0106] In some embodiments of the present invention, the image sensing device further includes a transfer gate, wherein the light sensing component includes a photodiode and the transfer gate selectively couples one of the photodiodes to the semiconductor island.

[0107] In some embodiments of the present invention, the dielectric island has a first width, a section of the grid-shaped trench structure below the dielectric island has a second width, and the first width is greater than the second width.

[0108] In some embodiments of the present invention, the semiconductor islands are located at intersections of the grid-shaped trench structures.

[0109] In some embodiments of the present invention, the semiconductor island is in a cross shape.

[0110] In some embodiments of the present invention, the semiconductor island has a width and a length, and the length is greater than the width.

[0111] In some embodiments of the present invention, the semiconductor body includes a bulk semiconductor and an epitaxial layer grown on the bulk semiconductor, and the epitaxial layer provides the inner sidewall.

[0112] Some aspects of the present disclosure relate to an image sensing device comprising an array of light sensing elements within a semiconductor body having a first side and a second side. A deep trench isolation structure extends from the second side between the light sensing elements in the array. A floating diffusion region is disposed within the semiconductor body proximate the first side and directly opposite the deep trench isolation structure. A semiconductor structure is directly between the deep trench isolation structure and the floating diffusion region. A dielectric island within the semiconductor body is directly between the semiconductor structure and the floating diffusion region.

[0113] In some embodiments of the present invention, the floating diffusion region is adjacent to the semiconductor structure.

[0114] In some embodiments of the present invention, the deep trench isolation structure has a width that is substantially constant or decreases as approaching the second side.

[0115] Some aspects of the present disclosure relate to a method for fabricating an integrated circuit device. The method includes etching a grid of trenches on a first side of a semiconductor body and depositing a sacrificial material in the trenches. The sacrificial material is etched to create a first trench recess, which is then filled with a first semiconductor material to form a first semiconductor structure. The semiconductor body is then thinned, and the sacrificial material is etched from a second side to form a second trench recess. The trenches are then aligned and filled with a dielectric from the second side.

[0116] In some embodiments of the present invention, the method further includes: etching a hole from the first side, wherein the hole extends partially through the first semiconductor structure and has a second depth; depositing a first dielectric in the hole; etching from the first side so as to recess the first dielectric in the hole and form a hole groove having a third depth; and depositing a second semiconductor material in the hole groove.

[0117] In some embodiments of the present invention, depositing the second semiconductor material in the hole recess includes epitaxially growing the second semiconductor material in the hole recess.

[0118] In some embodiments of the present invention, the second semiconductor material is polysilicon and the third depth is half of the first depth or less.

[0119] In some embodiments of the present invention, the method further includes doping to form an array of photodiodes laterally spaced apart from the trenches, wherein doping to form the array of photodiodes includes forming a P-well having a depth greater than or equal to the first depth.

[0120] In some embodiments of the present invention, forming the first semiconductor structure includes growing the first semiconductor material inside and outside the first trench recess.

[0121] In some embodiments of the present invention, the first semiconductor material is polysilicon, and the first depth is one quarter or less of a depth of the trench.

[0122] In some embodiments of the present invention, the method further includes epitaxially growing a semiconductor in the second trench recess.

[0123] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. An image sensing device, characterized in that: include: a semiconductor body having a first side and a second side opposite the first side; A light sensing component array is located in the semiconductor body; a grid-like trench structure defined by the inner sidewalls of the semiconductor body, extending from the second side and positioned between the light sensing elements in the array; a grid-shaped semiconductor structure located between the light sensing elements in the array and between the grid-shaped trench structure and the first side; a semiconductor island located between the grid-like semiconductor structure and the first side, wherein the semiconductor island is in contact with the semiconductor body; and The dielectric island is located between the semiconductor island and the grid-shaped semiconductor structure.

2. The image sensing device according to claim 1, wherein: The grid-shaped semiconductor structure includes polysilicon.

3. The image sensing device according to claim 1, wherein: Further included is a transfer gate, wherein the light sensing element includes a photodiode and the transfer gate selectively couples one of the photodiodes to the semiconductor island.

4. The image sensing device according to claim 1, wherein: The dielectric island has a first width, a section of the grid-shaped trench structure below the dielectric island has a second width, and the first width is greater than the second width.

5. The image sensing device according to claim 1, wherein: The semiconductor islands are located at intersections of the grid-shaped trench structures.

6. The image sensing device according to claim 1, wherein: The semiconductor island has a width and a length, and the length is greater than the width.

7. The image sensing device according to claim 1, wherein: The semiconductor body includes a bulk semiconductor and an epitaxial layer grown on the bulk semiconductor, and the epitaxial layer provides the inner sidewall.

8. An image sensing device, characterized in that: include: a semiconductor body having a first side and a second side opposite the first side; a light sensing component array, located in the semiconductor body; a deep trench isolation structure extending from the second side to between the light sensing elements in the array; a semiconductor structure aligned with a section of the deep trench isolation structure; a dielectric island aligned with the segment of the deep trench isolation structure; and a floating diffusion region aligned with the segment of the deep trench isolation structure; wherein the semiconductor structure is located between the dielectric island and the segment; The dielectric island is located between the semiconductor structure and the floating diffusion region; and The floating diffusion region is disposed in the semiconductor body near the first side.

9. The image sensing device according to claim 8, wherein: The floating diffusion region is adjacent to the semiconductor structure.

10. The image sensing device according to claim 8, wherein: The deep trench isolation structure has a width that is substantially constant or decreases as approaching the second side.

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