Chip testing equipment

Abstract

The utility model provides chip testing equipment, and relates to the technical field of chip testing. According to the utility model, the wafer feeding mechanism is arranged along the front-back direction, the wafer discharging mechanism and the wafer feeding mechanism are arranged side by side, the testing mechanism is located behind the wafer feeding mechanism and the wafer discharging mechanism, the testing mechanism is provided with a plurality of testing stations arranged along the left-right direction, and the testing stations are used for carrying out functional testing on a tested chip. The carrying mechanism is used for carrying the tested chip to the test stations of the test mechanism, carrying the tested chip among the plurality of test stations, and moving the tested chip out of the test mechanism after the test is completed. According to the technical scheme, the wafer feeding mechanism and the wafer discharging mechanism are arranged side by side, and the testing mechanism is arranged behind the wafer feeding mechanism and the wafer discharging mechanism, so that the overall length of the chip testing equipment is prevented from being too long, and the chip testing equipment is more compact in structure.

Description

Technical Field

[0001] The utility model relates to the technical field of chip testing, in particular to a chip testing device. Background Art

[0002] With the rapid development of semiconductor technology, the performance and reliability requirements of electronic components are constantly increasing. Therefore, multiple electrical performance tests are required for chips. Generally speaking, common test items include: UIS (Unclamped Inductive Switching) failure, DC test (DC test) and AC test (AC test).

[0003] Existing testing equipment mainly includes chip loading equipment, chip testing equipment and chip unloading equipment, thereby realizing automated testing of chips. After the chip under test enters the chip loading equipment, the chip under test needs to be transported from the chip loading equipment to the chip testing equipment to perform performance testing on the chip under test. Therefore, it is necessary to set up a transport device on the chip loading equipment and the chip unloading equipment respectively to realize the transport of the chip under test. In the prior art, the above-mentioned loading equipment, chip testing equipment and chip unloading equipment are arranged in sequence in the horizontal direction, which results in a longer length of the entire machine and is inconvenient to set up more detection stations. Therefore, there is an urgent need to design a testing equipment with a more compact structure. Utility Model Content

[0004] One purpose of the present invention is to provide a chip testing device to solve the technical problem of the non-compact structure of the chip testing device in the prior art.

[0005] A further object of the present invention is to increase the number of test stations and improve the accuracy of chip detection.

[0006] In particular, the present invention provides a chip testing device, comprising:

[0007] Wafer loading mechanism, arranged in the front-to-back direction, used to load the chip under test;

[0008] A wafer unloading mechanism, arranged side by side with the wafer loading mechanism, for unloading the tested chips after completion of testing;

[0009] A testing mechanism, located behind the wafer loading mechanism and the wafer unloading mechanism, comprising a plurality of testing stations arranged in a left-right direction, the testing stations being used to perform functional testing on the chip under test;

[0010] A transport mechanism is used to transport the chip under test between the wafer loading mechanism, multiple test stations and the wafer unloading mechanism.

[0011] Optionally, it also includes:

[0012] a first alignment mechanism, which is disposed between the wafer loading mechanism and the testing mechanism and is used to perform position correction on the chip under test transported from the wafer loading mechanism;

[0013] A second alignment mechanism is provided between the wafer unloading mechanism and the testing mechanism, and is used for performing position correction on the chip under test transported from the testing mechanism.

[0014] Optionally, the transport mechanism includes:

[0015] A first transport mechanism is provided on top of the wafer loading mechanism and is configured to be movable along the front-rear direction so as to transport the chip under test on the wafer loading mechanism to the first alignment mechanism.

[0016] Optionally, the transport mechanism further includes:

[0017] A second conveying mechanism is provided at the testing mechanism and is configured to be movable along the left-right direction so as to convey the chip under test on the first alignment mechanism to the testing station, convey the chip under test between the plurality of testing stations, and convey the chip under test after the test is completed to the second alignment mechanism.

[0018] Optionally, it also includes:

[0019] The detection mechanism is arranged between the wafer unloading mechanism and the testing mechanism, and is used to perform visual detection on the tested chip after the test is completed and the position correction is performed.

[0020] Optionally, the transport mechanism further includes:

[0021] The third conveying mechanism is arranged on the top of the wafer unloading mechanism and is configured to be movable along the front-to-back direction to convey the chip under test on the second alignment mechanism to the inspection mechanism, and to convey the chip under test after completing visual inspection to the wafer unloading mechanism.

[0022] Optionally, it further includes a waffle box loading mechanism and a waffle box unloading mechanism;

[0023] The first transport mechanism is further configured to transport the chip to be tested on the waffle box loading mechanism to the first alignment mechanism;

[0024] The third transport mechanism is further configured to transport the chip to be tested on the detection mechanism to the waffle box unloading mechanism.

[0025] Optionally, both the first alignment mechanism and the second alignment mechanism include:

[0026] XY adjustment module;

[0027] A mounting platform, the mounting platform is spaced apart from the XY adjustment module and has at least one first mounting position on the top for placing the chip under test;

[0028] An adjustment plate, one end of which is connected to the XY adjustment module and has at least one clamping portion for clamping the chip under test. The adjustment plate is configured to move under the drive of the XY adjustment module so that the clamping portion is clamped with the chip under test, so that the chip under test moves with the adjustment plate, thereby adjusting the position of the chip under test.

[0029] Optionally, each of the test stations includes:

[0030] A test fixture, comprising a lower test cover and an upper test cover;

[0031] a mold closing station, on which the lower test cover is placed and which is configured to be movable in a vertical direction so as to lift the lower test cover so as to press the lower test cover against the upper test cover;

[0032] The test station is used to perform functional testing on the chip under test in the test fixture.

[0033] Optionally, the second transport mechanism further includes a plurality of first slide rails, each of the first slide rails corresponds to one of the test stations, the upper test cover is slidably connected to the corresponding first slide rail, and the first slide rail is used to transport the pressed test fixture from the mold clamping station to the test station.

[0034] In the present invention, the wafer loading mechanism is arranged in the front-to-back direction, the wafer unloading mechanism is arranged side by side with the wafer loading mechanism, the testing mechanism is located behind the wafer loading mechanism and the wafer unloading mechanism, the testing mechanism has multiple testing stations arranged in the left-right direction, the testing stations are used to perform functional tests on the chips under test, and the transport mechanism is used to transport the chips under test between the wafer loading mechanism, the multiple testing stations, and the wafer unloading mechanism. The above technical solution arranges the wafer loading mechanism and the wafer unloading mechanism side by side, and sets the testing mechanism behind the wafer loading mechanism and the wafer unloading mechanism, thereby avoiding the chip testing equipment from being too long and making the chip testing equipment structure more compact.

[0035] Furthermore, the chip testing apparatus of the present invention also includes a first alignment mechanism, disposed between the wafer loading mechanism and the testing mechanism, for correcting the position of the chip under test delivered from the wafer loading mechanism. By providing the first alignment mechanism, the above technical solution allows for position correction of the chip under test before testing, thereby improving the accuracy of chip testing.

[0036] Based on the following detailed description of specific embodiments of the present invention in conjunction with the accompanying drawings, those skilled in the art will become more aware of the above and other objects, advantages and features of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Hereinafter, some specific embodiments of the present invention will be described in detail in an exemplary and non-limiting manner with reference to the accompanying drawings. The same reference numerals in the accompanying drawings indicate the same or similar components or parts. It should be understood by those skilled in the art that these drawings are not necessarily drawn to scale. In the accompanying drawings:

[0038] Figure 1 is a schematic structural diagram of a chip testing device according to an embodiment of the present utility model;

[0039] Figure 2 is a schematic structural diagram of a first alignment mechanism according to an embodiment of the present utility model;

[0040] Figure 3 is a schematic enlarged view of a clamping portion of an adjustment plate according to an embodiment of the present utility model;

[0041] Figure 4 is a schematic structural diagram of a first transport mechanism according to an embodiment of the present utility model;

[0042] Figure 5 yes Figure 1 A schematic structural diagram of a test mechanism of the chip test equipment shown;

[0043] Figure 6 is a schematic structural diagram of a second alignment mechanism and a detection mechanism according to an embodiment of the present utility model;

[0044] Figure 7 It is a schematic structural diagram of a wafer loading mechanism according to an embodiment of the present utility model.

[0045] Reference numerals:

[0046] 100- chip testing equipment, 200- chip under test, 10- wafer loading mechanism, 20- wafer unloading mechanism, 30- testing mechanism, 40- transport mechanism, 50- first alignment mechanism, 60- second alignment mechanism, 70- detection mechanism, 80- waffle box loading mechanism, 90- waffle box unloading mechanism, 41- first transport mechanism, 42- second transport mechanism, 43- third transport mechanism, 31- mold clamping station, 32- test fixture, 321- lower test cover, 322- upper test cover, 33- test station, 423- first slide rail, 422- first adsorption component, 4 25-suction nozzle, 421-eighth slide rail, 424-ninth slide rail, 426-mounting plate, 411-third slide rail, 412-second adsorption component, 413-visual detection component, 414-a pair of second slide rails, 51-XY adjustment module, 511-fourth slide rail, 512-fifth slide rail, 53-adjustment plate, 531-clamping part, 532-hook, 52-mounting table, 61-lens, 62-placing platform, 621-detection position, 11-sliding platform, 12-a pair of sixth slide rails, 13-material box, 14-manipulator, 15-seventh slide rail, 91-testing machine. DETAILED DESCRIPTION

[0047] The following describes in detail embodiments of the present invention, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present invention, and should not be construed as limiting the present invention.

[0048] In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "back", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0049] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features, that is, include one or more of the features. In the description of the present utility model, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined. When a feature "includes or contains" one or more of the features it covers, unless otherwise specifically described, this indicates that other features are not excluded and may further include other features.

[0050] Unless otherwise specified or limited, the terms "connection" and "installation" should be interpreted broadly. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection; direct connection, or indirect connection through an intermediate medium; internal communication between two components, or interaction between two components, unless otherwise specified. A person of ordinary skill in the art should be able to understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0051] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the description of this embodiment have the same meaning as commonly understood by ordinary technicians in the technical field to which this application belongs.

[0052] Figure 1 FIG is a schematic structural diagram of a chip testing device 100 according to an embodiment of the present invention. Figure 1 As shown, the chip testing equipment 100 includes a wafer loading mechanism 10, a wafer unloading mechanism 20, a testing mechanism 30, and a transport mechanism 40. The wafer loading mechanism 10 is arranged in the front-to-back direction and is used to load the chip under test 200. The wafer unloading mechanism 20 is arranged side by side with the wafer loading mechanism 10 and is used to unload the chip under test 200 after the test is completed. The testing mechanism 30 is located behind the wafer loading mechanism 10 and the wafer unloading mechanism 20. The testing mechanism 30 has multiple test stations arranged in the left-right direction. The test stations are used to perform functional tests on the chip under test 200. The transport mechanism 40 is used to transport the chip under test 200 between the wafer loading mechanism 10, multiple test stations, and the wafer unloading mechanism 20.

[0053] In this embodiment, the wafer loading mechanism 10 and the wafer unloading mechanism 20 are arranged side by side, and the testing mechanism 30 is set behind the wafer loading mechanism 10 and the wafer unloading mechanism 20, so as to avoid the chip testing equipment 100 from being too long and make the chip testing equipment 100 more compact.

[0054] Compared with the "I"-shaped layout in the prior art, this embodiment arranges the wafer loading mechanism 10 and the wafer unloading mechanism 20 at the front end, and arranges the test station 33 at the rear end, so that the entire chip testing equipment 100 forms a "U"-shaped structure. The layout is relatively compact and occupies a smaller area, so that more test stations can be arranged.

[0055] Figure 2 FIG is a schematic structural diagram of the first alignment mechanism 50 according to an embodiment of the present invention. Figure 2 As shown, and see Figure 1In some embodiments, the chip testing apparatus 100 further includes a first alignment mechanism 50 and a second alignment mechanism 60. The first alignment mechanism 50 is disposed between the wafer loading mechanism 10 and the testing mechanism 30 and is used to correct the position of the chip under test 200 conveyed from the wafer loading mechanism 10. The second alignment mechanism 60 is disposed between the wafer unloading mechanism 20 and the testing mechanism 30 and is used to correct the position of the chip under test 200 conveyed from the testing mechanism 30.

[0056] This embodiment provides a first alignment mechanism 50 to calibrate the position of the chip under test 200 before testing, thereby improving the accuracy of testing the chip under test 200. Furthermore, after testing the chip under test 200, the second alignment mechanism 60 can be used to calibrate the position of the chip under test 200 again, thereby ensuring the accuracy of the position of the chip under test 200 when it is transferred to the wafer unloading mechanism 20.

[0057] In some embodiments, the first alignment mechanism 50 and the second alignment mechanism 60 each include an XY adjustment module 51, a mounting platform 52, and an adjustment plate 53. The mounting platform 52 is spaced apart from the XY adjustment module 51 and has at least one first mounting position on its top for placing the chip under test 200. One end of the adjustment plate 53 is connected to the XY adjustment module 51 and has at least one engaging portion 531 for engaging the chip under test 200. The adjustment plate 53 is configured to move under the drive of the XY adjustment module 51 so that the engaging portion 531 engages with the chip under test 200, allowing the chip under test 200 to follow the movement of the adjustment plate 53, thereby adjusting the position of the chip under test 200.

[0058] Figure 3 FIG. 5 is a schematic enlarged view of the clamping portion 531 of the adjustment plate 53 according to an embodiment of the present invention. Figure 3 As shown, the engaging portion 531 includes four hooks 532 arranged in a square and defining a space for engaging the chip under test 200. The adjustment plate 53 moves with the XY adjustment module 51 until the four hooks 532 of the engaging portion 531 engage with the four side surfaces of the corresponding chip under test 200. The XY adjustment module 51 then drives the adjustment plate 53 to move again, thereby causing the adjustment plate 53 to move the chip under test 200 to adjust the position of the chip under test 200. Here, one end of the adjustment plate 53 is connected to the XY adjustment module 51, while the other end is essentially suspended, allowing it to move with the XY adjustment module 51 above the mounting platform 52.

[0059] In some embodiments, the XY adjustment module 51 includes a fourth slide rail 511 and a fifth slide rail 512. The fourth slide rail 511 is arranged along the X direction, and the fifth slide rail 512 is arranged along the Y direction. In other words, the XY adjustment module 51 can drive the adjustment plate 53 to move in both the X and Y directions. Here, the X direction is the left-right direction of the chip testing device 100, and the Y direction is the front-back direction of the chip testing device 100.

[0060] In some embodiments, the adjustment plate 53 is provided with two clamping portions 531, and the mounting platform 52 is provided with two first mounting positions, each of which corresponds to a clamping portion 531, so that the positions of two chips under test 200 can be adjusted simultaneously. In other embodiments, the number of clamping portions 531 and first mounting positions can be selected according to specific design requirements.

[0061] Figure 4 FIG. 4 is a schematic structural diagram of the first transport mechanism 41 according to an embodiment of the present invention. Figure 4 As shown, and see Figure 1 In some embodiments, the conveying mechanism 40 includes a first conveying mechanism 41, which is arranged on the top of the wafer loading mechanism 10 and is arranged to be movable along the front-to-back direction to convey the chip under test 200 on the wafer loading mechanism 10 to the first alignment mechanism 50.

[0062] In some embodiments, the first transport mechanism 41 includes a pair of second rails 414, a third rail 411, at least one second adsorption component 412, and a visual detection component 413. The pair of second rails 414 are arranged along the Y direction, and the third rail 411 is arranged along the X direction and is slidably connected to the pair of second rails 414. The second adsorption component 412 and the visual detection component 413 are respectively slidably mounted on the third rail 411 and can slide along the X direction and follow the third rail 411 to slide along the Y direction. In other words, the second adsorption component 412 and the visual detection component 413 can both move in both the X and Y directions. The second adsorption component 412 is used to adsorb and transport the chip under test 200 on the wafer loading mechanism 10 to the first alignment mechanism 50. The visual detection component 413 is used to detect the actual position of the chip under test 200 on the first alignment mechanism 50, so that the first alignment mechanism 50 can adjust the chip under test 200 according to the actual position of the chip under test 200. Here, there are two second adsorption components 412 , which can simultaneously adsorb two chips under test 200 . The number of the second adsorption components 412 is the same as the number of the clamping portions 531 of the adjustment plate 53 .

[0063] Figure 5 yes Figure 1 FIG. 1 is a schematic structural diagram of the test mechanism 30 of the chip test device 100. Figure 5As shown, in some embodiments, the transport mechanism 40 further includes a second transport mechanism 42, which is disposed at the testing mechanism 30 and is configured to be movable in the left-right direction to transport the chip under test 200 on the first alignment mechanism 50 to a testing station, transport the chip under test 200 between multiple testing stations, and transport the chip under test 200 after testing to the second alignment mechanism 60. It can be understood that the second transport mechanism 42 has three functions: one is to transport the chip under test 200 from the first alignment mechanism 50 to a testing station, one is to transport the chip under test 200 between multiple testing stations, and another is to transport the chip under test 200 from a testing station to the second alignment mechanism 60.

[0064] In some embodiments, the second transport mechanism 42 includes a mounting plate 426, an eighth slide rail 421, multiple ninth slide rails 424, and multiple first suction assemblies 422. The eighth slide rail 421 extends in the X-direction. The mounting plate 426 is mounted on the eighth slide rail 421 and can slide along the eighth slide rail 421. Multiple ninth slide rails 424 are installed on the mounting plate 426 at intervals along the X-direction. The ninth slide rails 424 extend in the Y-direction, and each ninth slide rail 424 is mounted with a first suction assembly 422. Each first suction assembly 422 is equipped with a suction nozzle 425. The ninth slide rail 424 can move the corresponding first suction assembly 422 in the Y-direction, and the multiple first suction assemblies 422 can move along with the mounting plate 426 in the X-direction. Here, the number of first suction assemblies 422 exceeds the number of test stations by one. It can be understood that if there are four test stations, then there are five first suction assemblies 422, with one first suction assembly 422 corresponding to each test station, and the remaining first suction assembly 422 corresponding to the first alignment mechanism 50. The suction nozzle 425 of the first suction assembly 422 corresponding to the first alignment mechanism 50 suctions the chip under test 200 from the first alignment mechanism 50. The eighth slide rail 421 then drives the mounting plate 426 to move along the X-axis, causing the first suction assembly 422 to move rightward, placing the chip under test 200 on the corresponding test station. The other first suction assemblies 422 also move rightward synchronously, moving the corresponding chip under test 200 to the next test station for the next functional test.

[0065] This embodiment can sequentially transport the chip under test 200 to multiple testing stations by providing the eighth slide rail 421 , thereby implementing multiple different functional tests on the chip under test 200 , and has a wide range of applications.

[0066] In some embodiments, each test station includes a test fixture 32, a mold clamping station 31 and a test station 33, and the test fixture 32 includes a lower test cover 321 and an upper test cover 322. The lower test cover 321 is placed on the mold clamping station 31, and is configured to be movable vertically to lift the lower test cover 321 so that the lower test cover 321 is pressed against the upper test cover 322. The test station 33 is used to perform functional testing on the chip 200 under test in the test fixture 32. It can be understood that one test station 33 corresponds to one mold clamping station 31. The test station 33 is located behind the corresponding mold clamping station 31. The number of test stations can be set to 1 to 6, and more test stations can achieve the specificity of the test, thereby improving the test accuracy of the chip test.

[0067] See also Figure 1 In some embodiments, the chip testing equipment 100 further includes a testing machine 91 , which is located behind the testing stations and connected to each testing station.

[0068] The second transport mechanism 42 also includes multiple first rails 423, each corresponding to a testing station. The upper test cover 322 is slidably connected to the corresponding first rail 423. The first rails 423 are used to transport the pressed test jig 32 from the mold clamping station 31 to the testing station 33. Here, the first rails 423 are located above the mold clamping station 31 and the testing station 33 and arranged along the Y direction. The upper test cover 322 is mounted at the bottom of the first rails 423. When the lower test cover 321 is lifted and pressed against the upper test cover 322, it slides along the first rails 423, moving the lower test cover 321 from the mold clamping station 31 to the rear testing station 33. After the lower test cover 321 is pressed against the upper test cover 322, it can be connected to the upper test cover 322 through suction, and then the mold clamping station 31 is lowered and reset. Here, the mold closing station 31 can move up and down following the vertically arranged slide rail to achieve the pressing and separation of the lower test cover 321 and the upper test cover 322.

[0069] After the chip under test 200 completes the test at the test station 33, the first slide rail 423 moves along the Y direction, driving the test fixture 32 to move from the test station 33 to the top of the front mold clamping station 31, and then the mold clamping station 31 moves upward, driving the lower test cover 321 to move downward, so that the lower sealing cover is separated from the upper sealing cover, and then the corresponding first adsorption component 422 adsorbs the chip under test 200, and the mounting plate 426 moves to the right along the eighth slide rail 421, so that the first adsorption component 422 drives the chip under test 200 to the lower test cover 321 of the next mold clamping station 31, and repeats the above test steps.

[0070] Figure 6FIG is a schematic structural diagram of the second alignment mechanism 60 and the detection mechanism 70 according to an embodiment of the present invention. Figure 6 As shown, in some embodiments, the chip testing equipment 100 further includes an inspection mechanism 70, which is disposed between the wafer unloading mechanism 20 and the testing mechanism 30 and is used to perform visual inspection on the chip under test 200 after testing and position correction. Here, the inspection mechanism 70 is located next to the second alignment mechanism 60, and the structure of the second alignment mechanism 60 is consistent with that of the first alignment mechanism 50. After the chip under test 200 is aligned in the second alignment mechanism 60, it is transported to the inspection mechanism 70 for inspection.

[0071] In some embodiments, the detection mechanism 70 includes a lens 61 and a placement platform 62. The placement platform 62 is provided with a detection position 621. The chip under test 200 is placed at the detection position 621 for detection. After the test is completed, it can be observed whether the chip under test 200 is damaged.

[0072] In one embodiment, the transport mechanism 40 further includes a third transport mechanism 43, which is disposed on top of the wafer unloading mechanism 20 and is configured to be movable in the front-to-back direction to transport the chip under test 200 on the second alignment mechanism 60 to the inspection mechanism 70, and to transport the chip under test 200 after visual inspection to the wafer unloading mechanism 20. Here, the structure of the third transport mechanism 43 is consistent with that of the first transport mechanism 41. The first adsorption assembly 422 transports the chip under test 200 after testing from the testing mechanism 30 to the second alignment mechanism 60. After the chip under test 200 is aligned, the third transport mechanism 43 transports the chip under test 200 on the second alignment mechanism 60 to the inspection position 621 of the inspection mechanism 70 for visual inspection. After the visual inspection is completed, the third transport mechanism 43 transports the chip under test 200 to the wafer unloading mechanism 20.

[0073] See also Figure 1 In some embodiments, the chip testing equipment 100 further includes a waffle box loading mechanism 80 and a waffle box unloading mechanism 90. The first transport mechanism 41 is further configured to transport the chip under test 200 on the waffle box loading mechanism 80 to the first alignment mechanism 50. The third transport mechanism 43 is further configured to transport the chip under test 200 on the detection mechanism 70 to the waffle box unloading mechanism 90. It can be understood that the chip testing equipment 100 can meet two loading methods: one is waffle box loading, and the other is wafer loading, which is highly practical.

[0074] Figure 7 FIG is a schematic structural diagram of a wafer loading mechanism 10 according to an embodiment of the present invention. Figure 7As shown, the wafer loading mechanism 10 includes a material box 13, a manipulator 14, a pair of sixth slide rails 12, a seventh slide rail 15 and a sliding platform 11. The pair of sixth slide rails 12 are arranged along the Y direction, and the seventh slide rail 15 is also arranged along the Y direction. The sliding platform 11 is slidably connected to the pair of sixth slide rails 12 and can move along the Y direction. The manipulator 14 is slidably connected to the seventh slide rail 15 and can move along the Y direction. The material box 13 is located at the front end, and a plurality of wafers are placed in the material box 13. The manipulator 14 clamps the steel ring of the corresponding wafer and moves along the Y direction to take the corresponding wafer out of the material box 13 and move it to the sliding platform 11. Then the sliding platform 11 moves along the Y direction to transport the wafer to the rear. Afterwards, the second adsorption component 412 adsorbs the chip under test 200 on the wafer and moves the chip under test 200 to the first alignment mechanism 50.

[0075] In some embodiments, the wafer unloading mechanism 20 has the same structure as the wafer loading mechanism 10. The second suction component 412 of the wafer unloading mechanism 20 first suctions and transfers the chip under test 200 on the second alignment mechanism 60 to the detection mechanism 70. After the chip under test 200 completes the detection, the second suction component 412 of the wafer unloading mechanism 20 transfers the chip under test 200 from the detection mechanism 70 to the wafer. The sliding platform 11 of the wafer unloading mechanism then slides along the Y direction to approach the magazine 13. The robot arm 14 then grips the steel ring of the wafer and slides along the Y direction to transfer the wafer into the magazine 13, completing the unloading of the chip under test 100.

[0076] In some embodiments, the waffle box loading mechanism 80 is mounted on the sliding platform 11 of the wafer loading mechanism 10, and the waffle box unloading mechanism 90 is mounted on the sliding platform 11 of the wafer unloading mechanism 10. In other embodiments, the positions of the waffle box loading mechanism 80 and the waffle box unloading mechanism 90 can also be selected according to specific circumstances.

[0077] At this point, those skilled in the art should recognize that, although multiple exemplary embodiments of the present invention have been shown and described in detail herein, many other variations or modifications consistent with the principles of the present invention can be directly determined or deduced from the contents disclosed herein without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be understood and deemed to cover all such other variations or modifications.

Claims

1. A chip testing device, characterized in that: include: Wafer loading mechanism, arranged in the front-to-back direction, used to load the chip under test; A wafer unloading mechanism, arranged side by side with the wafer loading mechanism, for unloading the tested chips after completion of testing; A testing mechanism, located behind the wafer loading mechanism and the wafer unloading mechanism, comprising a plurality of testing stations arranged in a left-right direction, the testing stations being used to perform functional testing on the chip under test; A transport mechanism is used to transport the chip under test between the wafer loading mechanism, the multiple test stations and the wafer unloading mechanism.

2. The chip testing device according to claim 1, characterized in that: Also includes: a first alignment mechanism, which is disposed between the wafer loading mechanism and the testing mechanism and is used to perform position correction on the chip under test transported from the wafer loading mechanism; A second alignment mechanism is provided between the wafer unloading mechanism and the testing mechanism, and is used for performing position correction on the chip under test transported from the testing mechanism.

3. The chip testing device according to claim 2, characterized in that: The transport mechanism comprises: A first transport mechanism is provided on top of the wafer loading mechanism and is configured to be movable along the front-rear direction so as to transport the chip under test on the wafer loading mechanism to the first alignment mechanism.

4. The chip testing device according to claim 3, characterized in that: The transport mechanism further comprises: A second conveying mechanism is provided at the testing mechanism and is configured to be movable along the left-right direction so as to convey the chip under test on the first alignment mechanism to the testing station, convey the chip under test between the plurality of testing stations, and convey the chip under test after the test is completed to the second alignment mechanism.

5. The chip testing device according to claim 4, characterized in that: Also includes: The detection mechanism is arranged between the wafer unloading mechanism and the testing mechanism, and is used to perform visual detection on the tested chip after the test is completed and the position correction is performed.

6. The chip testing device according to claim 5, characterized in that: The transport mechanism further comprises: The third conveying mechanism is arranged on the top of the wafer unloading mechanism and is configured to be movable along the front-to-back direction to convey the chip under test on the second alignment mechanism to the inspection mechanism, and to convey the chip under test after completing visual inspection to the wafer unloading mechanism.

7. The chip testing device according to claim 6, characterized in that: It also includes a waffle box loading mechanism and a waffle box unloading mechanism; The first transport mechanism is further configured to transport the chip to be tested on the waffle box loading mechanism to the first alignment mechanism; The third transport mechanism is further configured to transport the chip to be tested on the detection mechanism to the waffle box unloading mechanism.

8. The chip testing device according to any one of claims 2 to 7, characterized in that: The first alignment mechanism and the second alignment mechanism both include: XY adjustment module; A mounting platform, the mounting platform is spaced apart from the XY adjustment module and has at least one first mounting position on the top for placing the chip under test; An adjustment plate, one end of which is connected to the XY adjustment module and has at least one clamping portion for clamping the chip under test. The adjustment plate is configured to move under the drive of the XY adjustment module so that the clamping portion is clamped with the chip under test, so that the chip under test moves with the adjustment plate, thereby adjusting the position of the chip under test.

9. The chip testing device according to any one of claims 4 to 7, characterized in that: Each of the test stations comprises: A test fixture, comprising a lower test cover and an upper test cover; a mold closing station, on which the lower test cover is placed and which is configured to be movable in a vertical direction so as to lift the lower test cover so as to press the lower test cover against the upper test cover; The test station is used to perform functional testing on the chip under test in the test fixture.

10. The chip testing device according to claim 9, characterized in that: The second transport mechanism also includes a plurality of first slide rails, each of which corresponds to one of the test stations. The upper test cover is slidably connected to the corresponding first slide rail, and the first slide rail is used to transport the pressed test fixture from the mold clamping station to the test station.

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