Insulated gate bipolar transistor wafer

Abstract

The utility model discloses an insulated gate bipolar transistor wafer, a chip area and a test area are formed on the wafer, the chip area is provided with an insulated gate bipolar transistor with a groove type gate structure, the test area is provided with a process structure to be tested, and the process structure to be tested is a groove type test structure. According to the technical scheme provided by the embodiment of the invention, the performance test can be accurately carried out on the IGBT with the groove type gate structure.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to an insulated gate bipolar transistor wafer. Background Art

[0002] In electronic circuits, insulated gate bipolar transistors (IGBTs) offer superior electrical properties compared to MOS transistors, thyristors, and bipolar junction transistors (BJTs), such as higher input resistance, more effective gate oxide voltage control, and higher saturation current density. Among IGBTs, those with a trench gate structure, such as the trench field stop (Trench FS) IGBT, are currently the most widely used.

[0003] For the manufacturing process of IGBT wafers, it is usually necessary to perform a wafer acceptance test (WAT) after the wafer manufacturing is completed. The WAT can reflect the performance of the IGBT manufactured on the wafer, and the wafer can only be shipped after passing the WAT. The WAT test structure required for the above-mentioned WAT is usually set at a specific position on the wafer. In the process of realizing the present invention, the inventor found that the WAT test structure set at a specific position of the wafer in the related art is usually a planar test structure, which cannot accurately perform performance testing on IGBTs with trench gate structures. Summary of the Invention

[0004] An embodiment of the present application provides an insulated bipolar transistor wafer that can accurately perform performance testing on an IGBT that adopts a trench gate structure.

[0005] The present application provides an insulated gate bipolar transistor wafer, on which a chip area and a test area are formed. The chip area is provided with an insulated gate bipolar transistor with a trench gate structure, and the test area is provided with a process structure to be tested, which is a trench test structure.

[0006] In some embodiments, the process performance test structure to be tested is a wafer acceptability test structure.

[0007] In some embodiments, the test region is disposed in a scribe line region of the IGBT wafer.

[0008] In some embodiments, the process structure to be tested includes at least one of a polysilicon test structure, a gate test structure, a first-type MOS transistor test structure, and a second-type MOS transistor test structure.

[0009] In some embodiments, at least one of the polysilicon test structure, the gate test structure, the first type MOS transistor test structure, and the second type MOS transistor test structure is fabricated in the same fabrication process as a portion of the insulated gate bipolar transistor structure.

[0010] In some embodiments, an insulated gate bipolar transistor with a trench gate structure includes a first conductivity type substrate, a first conductivity type epitaxial layer, and a first trench structure. The first conductivity type epitaxial layer is formed on a first surface of the first conductivity type substrate, a first trench structure is formed within the first conductivity type epitaxial layer and extends to the first conductivity type substrate, and a first insulating layer and a first polysilicon layer are sequentially formed within the first trench structure.

[0011] In some embodiments, a polysilicon test structure includes a first conductive type substrate, a second trench structure, a first dielectric layer, and a first metal electrode. The second trench structure is formed in the first conductive type substrate, a second insulating layer and a second polysilicon layer are sequentially formed in the second trench structure, the second insulating layer and the first insulating layer are prepared in the same fabrication process, and the second polysilicon layer and the first polysilicon layer are prepared in the same fabrication process. The first dielectric layer is formed on a first surface of the first conductive type substrate, two first openings are formed in the first dielectric layer, the two first openings are respectively used to expose the second polysilicon layer at both ends of the second trench structure, and the first metal electrode covers the first openings.

[0012] In some embodiments, two planar polysilicon structures are formed on the first surface of the first conductive type substrate, the two planar polysilicon structures are respectively arranged at both ends of the second trench structure, and are electrically connected to the second polysilicon layer in the second trench structure, and the first opening exposes the two planar polysilicon structures.

[0013] In some embodiments, the number of the first openings disposed at each end of the second trench structure is at least two.

[0014] In some embodiments, an insulated gate bipolar transistor includes a first conductivity type substrate, a first conductivity type epitaxial layer, a first trench structure, a second dielectric layer, and a second metal electrode. The first conductivity type epitaxial layer is formed on a first surface of the first conductivity type substrate, a first trench structure is formed in the first conductivity type epitaxial layer and extends to the first conductivity type substrate, a first insulating layer and a first polysilicon layer are sequentially formed in the first trench structure, a second dielectric layer covers the first polysilicon layer, a second opening is provided in the second dielectric layer, the second opening is used to expose the first polysilicon layer, and a second metal electrode is formed on a side of the second dielectric layer away from the first conductivity type substrate, the second metal electrode covers the second opening.

[0015] In some embodiments, the gate test structure includes a first conductive type substrate, a third trench structure, a third dielectric layer, and a third metal electrode. The third trench structure is formed in the first conductive type substrate, a third insulating layer and a third polysilicon layer are sequentially formed in the third trench structure, the third insulating layer and the first insulating layer are prepared in the same preparation process, the third polysilicon layer and the first polysilicon layer are prepared in the same preparation process, the third dielectric layer is formed on the first surface of the first conductive type substrate, a third opening is formed in the third dielectric layer, the third opening is used to expose the third polysilicon layer in the third trench structure, the third opening and the second opening are prepared in the same preparation process, the third metal electrode covers the third opening, and the third metal electrode and the second metal electrode are prepared in the same preparation process.

[0016] In some embodiments, the insulated gate bipolar transistor includes a first conductive type substrate, a first conductive type epitaxial layer, a first trench structure, a second conductive type region, a second conductive type heavily doped region, a first conductive type heavily doped region, a second dielectric layer, a first metal layer, a collector region, and a collector. A first conductive type epitaxial layer is formed on a first surface of a first conductive type substrate, a first trench structure is formed in the first conductive type epitaxial layer and extends to the first conductive type substrate, a first insulating layer and a first polysilicon layer are sequentially formed in the first trench structure, a second conductive type region is formed in the first conductive type epitaxial layer, a second conductive type heavily doped region is formed in the second conductive type region, the first conductive type heavily doped region is formed in the second conductive type region and connects the first trench structure and the second conductive type heavily doped region, a second dielectric layer covers the second conductive type region, a second opening and a fourth opening are provided on the second dielectric layer, the second opening is used to expose the first polysilicon layer, and the fourth opening is used to expose the second conductive type heavily doped region, a first metal layer is formed on a side of the second dielectric layer away from the first conductive type substrate, the first metal layer includes a second metal electrode covering the second opening, and a fourth metal electrode covering the fourth opening, a collector region is formed on the second surface of the first conductive type substrate, the second surface is arranged opposite to the first surface, and the collector is formed on a side of the collector region away from the second surface.

[0017] In some embodiments, the first-type MOS transistor test structure includes a first-conductivity-type substrate, a fourth trench structure, a fourth dielectric layer, and a second metal layer. The fourth trench structure is formed in the first-conductivity-type substrate, and a fourth insulating layer and a fourth polysilicon layer are sequentially formed in the fourth trench structure. The fourth insulating layer and the first insulating layer are prepared in the same manufacturing process, and the fourth polysilicon layer and the first polysilicon layer are prepared in the same manufacturing process. The second-conductivity-type region is formed on one side of the fourth trench structure, and the second-conductivity-type region on one side of the fourth trench structure is prepared in the same manufacturing process as the second-conductivity-type region of the insulated gate bipolar transistor. The first-conductivity-type heavily doped region is formed in the second-conductivity-type region and is connected to the fourth insulating layer. The first-conductivity-type heavily doped region connected to the fourth trench structure is prepared in the same manufacturing process as the first-conductivity-type heavily doped region of the insulated gate bipolar transistor. A fourth dielectric layer is formed on the second conductivity type region and the first conductivity type substrate. A fifth opening and a sixth opening are formed in the fourth dielectric layer. The fifth opening is used to expose the fourth polysilicon layer at one end of the fourth trench structure, and the sixth opening is used to expose the first conductivity type heavily doped region. The fifth and sixth openings are fabricated in the same fabrication process as the second and fourth openings. A second metal layer is formed on a side of the fourth dielectric layer away from the first conductivity type substrate. The second metal layer includes a fifth metal electrode covering the fifth opening and a sixth metal electrode covering the sixth opening. The second metal layer and the first metal layer are fabricated in the same fabrication process.

[0018] In some embodiments, a second-type MOS transistor test structure includes a first-conductivity-type substrate, a second-conductivity-type region, a fifth trench structure, a fifth dielectric layer, and a third metal layer. The second-conductivity-type region is formed on a first surface of the first-conductivity-type substrate, and the second-conductivity-type region on the first surface is fabricated in the same fabrication process as the second-conductivity-type region of the insulated gate bipolar transistor. A fifth trench structure is formed within the second-conductivity-type region and extends into the first-conductivity-type substrate. A fifth insulating layer and a fifth polysilicon layer are sequentially formed within the fifth trench structure. The fifth insulating layer and the first insulating layer are fabricated in the same fabrication process, and the fifth polysilicon layer and the first polysilicon layer are fabricated in the same fabrication process. A fifth dielectric layer is formed on the surface of the second-conductivity-type region. A seventh opening, an eighth opening, and a ninth opening are formed within the fifth dielectric layer. The seventh opening is configured to expose the fifth polysilicon layer at one end of the fifth trench structure. The eighth opening and the ninth opening are configured to expose the second-conductivity-type region on either side of the fifth trench structure, respectively. The seventh opening, the eighth opening, and the ninth opening are fabricated in the same fabrication process as the second opening and the fourth opening. A third metal layer is formed on a side of the fifth dielectric layer away from the first conductive type substrate. The third metal layer includes a seventh metal electrode covering the seventh opening, an eighth metal electrode covering the eighth opening, and a ninth metal electrode covering the ninth opening. The third metal layer and the first metal layer are prepared in the same preparation process.

[0019] In some embodiments, at least one of the first opening, the second opening, the third opening, the fourth opening, the fifth opening, the sixth opening, the seventh opening, the eighth opening, and the ninth opening comprises a bowl-shaped opening structure.

[0020] In some embodiments, the test area is further provided with at least one test electrode, which is electrically connected to at least one of the second metal electrode, the third metal electrode, the fourth metal electrode, the fifth metal electrode, the sixth metal electrode, the seventh metal electrode, the eighth metal electrode and the ninth metal electrode.

[0021] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

[0022] The insulated gate bipolar transistor wafer provided in the embodiment of the present application has an IGBT with a trench gate structure in the chip area on the wafer, and a process structure to be tested is provided in the test area, and the process structure to be tested is a trench test structure. The trench test structure provided in the test area can more accurately reflect the electrical performance of each part of the IGBT with a trench gate structure, thereby realizing more accurate detection of the film layer structure process of the IGBT, thereby improving the preparation yield of the insulated gate bipolar transistor wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 A schematic structural diagram of the insulated bipolar transistor wafer provided in this application;

[0025] Figure 2 A schematic structural diagram of an insulated gate bipolar transistor with a trench gate structure provided in this application;

[0026] Figure 3 A schematic diagram of the structure of the polysilicon test structure provided in this application;

[0027] Figure 4 A top view of the polysilicon test structure provided in this application;

[0028] Figure 5 A schematic diagram of the gate test structure provided in this application;

[0029] Figure 6 A top view of the gate test structure provided in this application;

[0030] Figure 7 A schematic diagram of the structure of the first type of MOS tube test structure provided in this application;

[0031] Figure 8 A top view of the first type of MOS tube test structure provided in this application;

[0032] Figure 9 A schematic diagram of the structure of the second type of MOS tube test structure provided in this application;

[0033] Figure 10 This is a top view of the second type of MOS tube test structure provided in this application. DETAILED DESCRIPTION

[0034] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0035] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0036] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0037] Reference is made herein to the figures as idealized exemplary embodiments and, thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.

[0038] Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present application and are not to be construed as limiting the present application. The optical path of the present application is described in detail below, and the description of the optical path is shown in the accompanying drawings, where the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0039] The present application provides an insulated bipolar transistor wafer, Figure 1 This is a schematic diagram of the structure of the insulated bipolar transistor wafer provided in this application, as shown in FIG. Figure 1 As shown, a chip region 2 and a test region 5 are formed on the insulated bipolar transistor wafer 1. The test region 5 can be arranged around the chip region 2. At least one IGBT 4 with a trench gate structure is arranged on the chip region 2. The test region 5 is provided with a process structure to be tested 6, which is a trench test structure.

[0040] The insulated gate bipolar transistor wafer 1 provided in the embodiment of the present application has an IGBT 4 with a trench gate structure provided in the chip area 2 on the wafer, and a process structure to be tested 6 is provided in the test area 5, and the process structure to be tested 6 is a trench test structure. The trench test structure provided on the test area 5 can more accurately reflect the electrical performance of each part of the trench gate structure IGBT 4, thereby realizing more accurate detection of each film layer structure process of the IGBT 4, thereby improving the preparation yield of the insulated gate bipolar transistor wafer 1.

[0041] In some embodiments, the insulated bipolar transistor wafer 1 includes a chip area 2 and a cutting path area 3 surrounding the chip area 2. The cutting path area 3 is a thin line on the wafer used to separate the individual chips arranged on the chip area 2. It mainly provides a guide line when the wafer is diced to ensure that the chip can be accurately cut. The test area 5 is set in the cutting path area 3 of the insulated gate bipolar transistor wafer 1. While realizing the performance detection of each film layer structure of the insulated bipolar transistor wafer 1, it will not affect the normal use of each chip in the chip area 2 and subsequent chip cutting.

[0042] In some embodiments, the process structure to be tested 6 is a wafer acceptability test (WAT) structure. WAT is a very critical test link in the semiconductor manufacturing process. It is usually performed after the wafer tape-out is completed and before the quality inspection. The purpose is to detect the process conditions of the wafer by measuring the electrical parameters of a specific test structure on the wafer. WAT can evaluate the quality and stability of the semiconductor manufacturing process and determine whether the wafer meets the electrical specification requirements of the process technology platform. In some embodiments, the process structure to be tested 6 can be designed according to the film structure of the IGBT4 and the specific performance of the IGBT4 that needs to be tested for the film structure. For example, the above-mentioned process structure to be tested 6 can include at least one of a polysilicon test structure 61, a gate test structure 62, a first type MOS tube test structure 63 and a second type MOS tube test structure 64, and each of the above-mentioned test structures is a trench type. The trench-type polysilicon test structure 61, the gate test structure 62, the first-type MOS transistor test structure 63, and the second-type MOS transistor test structure 64 can accurately measure the performance of each film layer structure of the IGBT 4 with a trench-type gate structure, and whether the preparation process of each film layer structure meets the preparation requirements.

[0043] In some embodiments, in order to make the process structure to be tested 6 closer to the film structure and process of the IGBT 4, at least one of the above-mentioned polysilicon test structure 61, gate test structure 62, first-type MOS transistor test structure 63, and second-type MOS transistor test structure 64 can be prepared in the same preparation process as part of the structure of the IGBT 4. In this case, the two will be closer in terms of both film structure and preparation process, so that the process structure to be tested 6 can more accurately reflect the specific conditions of the IGBT 4. For an IGBT 4 with a trench gate structure, a polysilicon layer will be filled in the trench structure. The square resistance of the polysilicon layer can reflect the gate resistance of the entire IGBT 4 and is therefore a parameter of particular interest. In the embodiments of the present application, by setting the above-mentioned polysilicon test structure 61, the square resistance of the polysilicon layer can be measured. In some cases, the leakage current and withstand voltage capability of the trench gate of the IGBT 4 are also parameters of particular interest. In the embodiments of the present application, the gate test structure 62 can be set to test them. In addition, due to the design principle of the IGBT, there may be conductive channels in two directions in the film structure of the IGBT4. The voltage withstand capability of these conductive channels is also a parameter of concern. In the embodiment of the present application, a corresponding MOS tube can be designed for each conductive channel, that is, the above-mentioned first-type MOS tube test structure 63 and second-type MOS tube test structure 64 respectively test the voltage withstand capability of the corresponding conductive channel.

[0044] In the following embodiments, the specific film layer structures of the polysilicon test structure 61, the gate test structure 62, the first type MOS transistor test structure 63 and the second type MOS transistor test structure 64 are described by taking the specific structure of an insulated gate bipolar transistor with a trench gate structure as an example. Figure 2 The schematic diagram of the structure of the insulated gate bipolar transistor with a trench gate structure provided in this application is shown in FIG. Figure 2 The specific film layer structure in the embodiment shown is only an example. For different types of IGBT4, part or all of the film layer structure may change, but for each specific structure, a corresponding test process structure can be set to test the performance of the film layer structure.

[0045] like Figure 2As shown, the insulated gate bipolar transistor 4 with a trench gate structure may include a first conductivity type substrate 41, a first trench structure 42, a first conductivity type epitaxial layer 43, a second conductivity type region 431, a second conductivity type heavily doped region 432, and a first conductivity type heavily doped region 433. The first conductivity type substrate 41 includes a first surface 411 and a second surface 412 disposed opposite each other. The first conductivity type epitaxial layer 43 is formed on the first surface 411 of the first conductivity type substrate 41. The first trench structure 42 is formed in the first conductivity type epitaxial layer 43 and extends to the first conductivity type substrate 41. A gate is formed in the first trench structure 42. The gate includes a first insulating layer 421 and a first polysilicon layer 422 formed in sequence. The second conductivity type region 431 is formed in the first conductivity type epitaxial layer 43. The second conductivity type heavily doped region 432 is formed in the second conductivity type region 431. The first conductivity type heavily doped region 433 is formed in the second conductivity type region 431 and connects the first trench structure 42 and the second conductivity type heavily doped region 432.

[0046] Continue to see Figure 2 The trench-gate insulated gate bipolar transistor 4 further includes a second dielectric layer 44, a first metal layer 45, a protective layer 46, a collector region 47, and a collector electrode 48. The second dielectric layer 44 covers the second conductivity type region 431 and is provided with a second opening 441 and a fourth opening 442. The second opening 441 is used to expose the first polysilicon layer 422, and the fourth opening 442 is used to expose the second conductivity type heavily doped region 432. The first metal layer 45 is formed on a side of the second dielectric layer 44 away from the first conductivity type substrate 41. The first metal layer 45 includes a second metal electrode 451 covering the second opening 441 and a fourth metal electrode 452 covering the fourth opening 442. The protective layer 46 is formed on a side of the first metal layer 45 away from the first conductivity type substrate 41. The collector region 47 is formed on the second surface 412 of the first conductivity type substrate 41. The ions implanted into the collector region 47 are also of the second conductivity type. The collector electrode 48 is formed on a side of the collector region 47 away from the second surface 412 .

[0047] Exemplarily, the trench-gate insulated gate bipolar transistor 4 further includes a CS region 434. The CS region 434 is typically located between the emitter and collector of the IGBT and may be located at the junction of the first conductivity type substrate 41 and the first conductivity type epitaxial layer 43. The conductivity type of the CS region 434 may be the second conductivity type, which helps reduce the on-state voltage drop and switching loss of the IGBT while maintaining a low turn-off time, thereby optimizing device performance.

[0048] In some embodiments, the first conductivity type mentioned above is N-type and the second conductivity type is P-type; or in other cases, the first conductivity type mentioned above is P-type and the second conductivity type is N-type. Both cases are applicable to the technical solutions protected by the embodiments of the present application.

[0049] For ease of description, in the embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type. The process of forming the trench gate structure IGBT4 on the chip area 2 of the insulated bipolar transistor wafer 1 may include the following steps:

[0050] Step 1: providing a substrate 41 of a first conductivity type, wherein the doping resistivity of the substrate 41 may be less than 30 Ω.cm, and the substrate 41 includes a first surface 411 and a second surface 412 opposite to each other;

[0051] Step 2: forming a first conductive type epitaxial layer 43 on the first surface of the first conductive type substrate 41 by deposition or other processes;

[0052] Step 3: On the first conductive type epitaxial layer 43, an insulating oxide layer is grown by thermal oxidation, and the chip region 2 is etched out. Then, the CS implantation region is defined by a mask, and N-type impurities such as P31 or As75 are ion-implanted and activated and diffused through a high-temperature furnace to form a CS region 434. The doping dose can be 1×10 10 / cm 2 ~1×10 15 / cm 2 , the diffusion temperature can be 900℃~1300℃, and the diffusion time can be 100min~300min;

[0053] Step 4: Etching the first conductive type epitaxial layer 43 to form a first trench structure 42. The etching process may be dry etching, and the etching depth may be 3 μm to 10 μm.

[0054] Step 5: Deposit a first insulating layer 421 in the trench. The thickness of the first insulating layer 421 is generally 0.05um to 0.3um. Then, grow a layer of polysilicon (POLY) as a first polysilicon layer 422 by chemical vapor deposition. The thickness of the polysilicon is generally 0.3um to 3um. Then, define the gate by photolithography and etching.

[0055] Step 6: Ion implantation is performed on the first conductive type epitaxial layer 43 by designing different masks to implant the second conductive type region 431, the second conductive type heavily doped region 432 and the first conductive type heavily doped region 433. The ion implantation dose of the second conductive type region 431 is 1×10 12 / cm 2 ~1×10 15 / cm 2 The ion implantation dose of the second conductive type heavily doped region 432 is 1×10 13 / cm 2 ~1×10 16 / cm 2 The ion implantation dose of the first conductive type heavily doped region 433 is 1×10 13 / cm 2 ~1×10 16 / cm 2 , and then pass through a high temperature furnace tube for annealing and repair of injection damage;

[0056] Step 7: A second dielectric layer 44 is deposited by chemical vapor deposition, and a second opening 441 and a fourth opening 442 are etched through a mask. Metal is sputtered into the second opening 441 and the fourth opening 442 to form a first metal layer 45, wherein the first metal layer 45 includes a second metal electrode 451 and a fourth metal electrode 452, the second metal electrode 451 covers the second opening 441, and the fourth metal electrode 452 covers the fourth opening 442. The material of the first metal layer 45 can be one or more of aluminum (Al), gold (Au), titanium (Ti), nickel (Ni), and silver (Ag), and the thickness can be 0.5um to 5um.

[0057] Step 8: Forming a protective layer 46 on the side of the first metal layer 45 away from the first conductive type substrate 41 by deposition or other processes. The deposited material may be polyimide or silicon nitride. The thickness of the protective layer 46 may be 3 μm to 10 μm.

[0058] Step 9: The back side of the wafer, i.e., the second surface 412 of the first conductive type substrate 41, is ground and thinned. After thinning, a second type of ion implantation is performed on the second surface 412 to form a collector region 47. For example, the implanted ions may be boron, and the implantation dose may be 1×10 10 / cm 2 ~1×10 15 / cm 2 , then activate the implanted ions and repair the implanted damage through high temperature annealing, rapid annealing, laser annealing, etc.;

[0059] Step 10: Perform metal evaporation on the second surface 412 to form the collector electrode 48. The metal material can be Ti, Ni, Ag or Ni, Ag or Al, Ti, Ni, Ag, etc. The metal thickness can be 0.5um to 3um.

[0060] The polysilicon test structure 61 , the gate test structure 62 , the first type MOS transistor test structure 63 , and the second type MOS transistor test structure 64 in the embodiment of the present application are described below respectively.

[0061] As described in the above embodiment, the polysilicon test structure 61 in the embodiment of the present application is mainly for Figure 2 In the embodiment shown, the IGBT 4 includes a first conductive type substrate 41, and a first conductive type epitaxial layer 43 formed on a first surface 411 of the first conductive type substrate 41, and then a first trench structure 42 is formed in the first conductive type epitaxial layer 43, and a first insulating layer 421 and a first polysilicon layer 422 are formed in the first trench structure 42. When it is necessary to measure the square resistance of the first polysilicon layer 422 and further calculate its gate resistance, a polysilicon test structure 61 can be formed on the first conductive type substrate 41 in the saw road area 3. The structural schematic diagram of the polysilicon test structure 61 and its preparation process can be referred to. Figure 3 and Figure 4 ,in Figure 3 This is a schematic diagram of the polysilicon test structure provided in this application. Figure 4 A top view of the polysilicon test structure provided in this application.

[0062] like Figure 3 As shown, the polysilicon test structure 61 includes a first conductive type substrate 41, a second trench structure 611, a second insulating layer 612, a second polysilicon layer 613, a first dielectric layer 614, and a first metal electrode 615. The second trench structure 611 is formed in the first conductive type substrate 41. The second insulating layer 612 and the second polysilicon layer 613 are sequentially formed in the second trench structure 611. The first dielectric layer 614 is formed on the first surface 411 of the first conductive type substrate 41. Two first openings 616 are formed in the first dielectric layer 614. The two first openings 616 are respectively used to expose the second polysilicon layer 613 at both ends of the second trench structure 611. The first metal electrode 615 covers the first openings 616.

[0063] In some embodiments, as Figure 3 As shown, the first metal electrode 615 in the polysilicon test structure 61 is connected to the first test electrode 71 through an external lead, so as to facilitate electrical testing of the polysilicon test structure 61 .

[0064] In some embodiments, see Figure 3 and Figure 4Two planar polysilicon structures 617 are formed on the first surface 411 of the first conductive type substrate 41. The two planar polysilicon structures 617 are respectively disposed at opposite ends of the second trench structure 611 and are electrically connected to the second polysilicon layer 613 within the second trench structure 611. In other words, the two planar polysilicon structures 617 are disposed at opposite ends of the second polysilicon layer 613. The first opening 616 exposes the two planar polysilicon structures 617. The two planar polysilicon structures 617 primarily function as conductive wires. In some embodiments, the two planar polysilicon structures 617 can be replaced with conductive metal. The advantage of using planar polysilicon structures 617 is that they can be produced in the same process step as the polysilicon in the trench structure.

[0065] Exemplarily, the process of forming the polysilicon test structure 61 may include the following steps:

[0066] Step S1: According to the chip manufacturing process, a test area 5 of the cutting path area 3 is etched through a mask. Figure 3 The etching depth of the second trench region 611 is 2 μm to 10 μm;

[0067] Step S2: Deposit a second insulating layer 612 in the second trench. Figure 2 The first insulating layer 421 is prepared in the same preparation process, and then a layer of polysilicon (POLY) is grown by chemical vapor deposition as the second polysilicon layer 613. The second polysilicon layer 613 is formed with Figure 2 The first polysilicon layer 422 is prepared in the same preparation process, and then the polysilicon outside the second trench is etched cleanly through exposure, development, etching and other processes. In this step, the two planar polysilicon structures 617 can also be formed at the same time.

[0068] Step S3: Form a first dielectric layer 614 by chemical vapor deposition (CVD), and refer to Figure 4 After designing the mask, two first openings 616 are etched on the first dielectric layer 614;

[0069] Step S4: forming a first metal electrode 615 on the wafer surface by physical vapor deposition (PVD) sputtering;

[0070] Step S5: Reference Figure 3 and Figure 4 , metal lines connected to the two first test electrodes 71 are etched through mask design, so that the two first metal electrodes 615 are electrically connected to the two first test electrodes 71 respectively.

[0071] In some embodiments, see Figure 3 and Figure 4The number of first openings 616 provided at each end of the second trench structure 611 is at least two. At least two first openings 616 can effectively reduce contact resistance and make the test results more accurate.

[0072] See also Figure 3 and Figure 4 The specific steps of performing electrical testing on the polysilicon test structure 61 are as follows:

[0073] The two probes of the WAT test machine are electrically connected to the two first test electrodes 71 respectively. A high level 1 is applied to one end and a low level 0 is applied to the other end. The current loop at this time is: the first test electrode 71 at one end measures the current in the loop, then passes through the planar polysilicon structure 617, passes through the POLY in the second polysilicon layer 613 in the middle second trench structure 611, and reaches the first test electrode 71 at the other end. After measuring the current, the loop resistivity ρ is obtained based on the applied voltage, and finally the sheet resistance is calculated according to the formula R s =ρ×L / S, the square resistance R of the polysilicon in the polysilicon test structure 61 can be measured. S_POLY , the value of the square resistance can reflect Figure 2 The gate resistance of IGBT4 is shown as follows. When the measured R S_POLY When the parameter fluctuation is large, it indicates that the gate oscillation of the IGBT 4 may become larger and affect the power loss and switching speed of the IGBT 4. Therefore, the electrical test of the polysilicon test structure 61 helps to monitor whether the power consumption and reliability of the entire IGBT 4 are normal.

[0074] As described in the above embodiment, the gate test structure 62 in the embodiment of the present application is mainly for Figure 2 In the illustrated embodiment, the IGBT 4 includes a first conductive type substrate 41, and a first conductive type epitaxial layer 43 formed on a first surface 411 of the first conductive type substrate 41, a first trench structure 42 is formed in the first conductive type epitaxial layer 43, and a first insulating layer 421 and a first polysilicon layer 422 are formed in the first trench structure 42, and a second dielectric layer 44 covering the first polysilicon layer 422 is provided. A second opening 441 exposing the first polysilicon layer 422 is provided on the second dielectric layer 44, and a second metal electrode 451 covering the second opening 441 is formed on a side of the second dielectric layer 44 away from the first conductive type substrate 41. When it is necessary to test the leakage current and breakdown voltage of the gate passing through the above-mentioned first trench structure 42, a gate test structure 62 can be formed on the first conductive type substrate 41 in the cutting street area 3. The structural schematic diagram of the gate test structure 62 and its preparation process can be referred to. Figure 5 and Figure 6 ,in Figure 5 This is a schematic diagram of the gate test structure provided in this application. Figure 6 This is a top view of the gate test structure provided in this application.

[0075] like Figure 5 As shown, the gate test structure 62 includes a first conductive type substrate 41, a third trench structure 621, a third dielectric layer 624, and a third metal electrode 625. The third trench structure 621 is formed in the first conductive type substrate 41. A third insulating layer 622 and a third polysilicon layer 623 are sequentially formed in the third trench structure 621. The third dielectric layer 624 is formed on the first surface 411 of the first conductive type substrate 41. A third opening 626 is formed in the third dielectric layer 624. The third opening 626 is used to expose the third polysilicon layer 623 in the third trench structure 621. The third metal electrode 625 covers the third opening 626.

[0076] In some embodiments, as Figure 5 As shown, the third metal layer 625 in the gate test structure 62 is connected to the second test electrode 72 through an external lead, and the first conductive type substrate 41 in the gate test structure 62 is electrically connected to the test base 8 to facilitate electrical testing of the gate test structure 62.

[0077] Exemplarily, the process of forming the gate test structure 62 may include the following steps:

[0078] Step S1: According to the chip manufacturing process, a test area 5 of the cutting path area 3 is etched through a mask. Figure 5 The third trench structure 621 is etched to a depth of 2 μm to 10 μm.

[0079] Step S2: depositing a third insulating layer 622 in the third trench. Figure 2 The first insulating layer 421 in the first embodiment is prepared in the same preparation process, and then a layer of polysilicon (POLY) is grown by chemical vapor deposition as a third polysilicon layer 623. Figure 2 The first polysilicon layer 422 is prepared in the same preparation process, and then the polysilicon outside the third trench structure 621 is etched cleanly through processes such as exposure, development, and etching;

[0080] Step S3: Form a third dielectric layer 624 by chemical vapor deposition (CVD), and refer to Figure 6 After designing the mask, a third opening 626 is etched on the third dielectric layer 624. The third opening 624 is Figure 2 The second opening 441 in is prepared in the same preparation process;

[0081] Step S4: forming a third metal electrode 625 on the surface of the wafer by physical vapor deposition (PVD) sputtering. Figure 2 The second metal electrode 451 is prepared in the same preparation process;

[0082] Step S5: Reference Figure 5 , a metal connection is etched out through a mask design to electrically connect the third metal electrode 625 with the second test electrode 72 , and the first conductive type substrate 41 with the test base 8 .

[0083] See also Figure 5 and Figure 6 , the specific steps of performing electrical testing on the gate test structure 62 are:

[0084] The probe of the WAT test machine is electrically connected to the second test electrode 72, and the current is transmitted to the gate structure formed in the third trench structure 621 through the third polysilicon layer 623. The test base 8 supplies power by contacting the back of the gate test structure 62 to be tested. The test base 8 applies a continuously increasing high level, and the probe applies a low level 0. By testing the leakage current I through the gate film layer r Obtain the leakage current I of the trench gate of IGBT4 r By testing the voltage applied by the base 8 during breakdown, the breakdown voltage V BD_GATE , thereby testing the quality of the gate in the first trench structure 42 that actually works when the IGBT 4 is working, which is helpful for subsequent failure analysis and process control of the IGBT 4.

[0085] As described in the above embodiment, the first type MOS transistor test structure 63 and the second type MOS transistor test structure 64 in the embodiment of the present application are mainly for Figure 2In the illustrated embodiment, the IGBT 4 includes a first conductive type substrate 41, a first conductive type epitaxial layer 43, a first trench structure 42, a first insulating layer 421 and a first polysilicon layer 422, a second conductive type region 431, a second conductive type heavily doped region 432, a first conductive type heavily doped region 433, a second dielectric layer 44, a second opening 441 and a fourth opening 442, a first metal layer 45, a second metal electrode 451 and a fourth metal electrode 452, a collector region 47 and a collector electrode 48. When a forward voltage is applied to the IGBT 4, I There are two conductive channels inside GBT4. The first one is the current flowing from the gate in the first trench structure 42 through the first conductive type heavily doped region 433, the second conductive type region 431, the first conductive type substrate 41 and the collector region 47 to the collector 48. This conductive channel can be called a vertical conductive channel. The second one is the current flowing through the second conductive type region 431 on the left, the first conductive type substrate 41 and the second conductive type region 431 on the right in sequence, that is, the current flows around the semicircular channel at the bottom of the first trench 42. This conductive channel can be called a semicircular conductive channel. When it is necessary to test the parameters of the voltage withstand capability of the conductive channels in the above two directions that may exist in the film structure of IGBT4, in the embodiment of the present application, a first type MOS tube test structure 63 and a second type MOS tube test structure 64 are formed on the first conductive type substrate 41 in the cutting area 3 for testing. The structural schematic and preparation process of the first type MOS tube test structure 63 can be referred to. Figure 7 and Figure 8 ,in Figure 7 This is a schematic diagram of the structure of the first type of MOS tube test structure provided in this application. Figure 8 This is a top view of the first type of MOS tube test structure provided in this application.

[0086] like Figure 7As shown, the first-type MOS transistor test structure 63 includes a first-conductivity-type substrate 41, a fourth trench structure 631, a fourth insulating layer 632 and a fourth polysilicon layer 633, a second-conductivity-type region 634, a first-conductivity-type heavily doped region 635, a fourth dielectric layer 636, a fifth opening 638 and a sixth opening 639, a second metal layer 637, a fifth metal electrode 637a, and a sixth metal electrode 637b. The fourth trench structure 631 is formed in the first-conductivity-type substrate 41, a fourth insulating layer 632 and a fourth polysilicon layer 633 are sequentially formed in the fourth trench structure 631, the second-conductivity-type region 634 is formed on one side of the fourth trench structure 631, a first-conductivity-type heavily doped region 635 is formed in the second-conductivity-type region 634, the first-conductivity-type heavily doped region 635 is connected to the fourth insulating layer 632, and a fourth dielectric layer 636 is formed between the second-conductivity-type region 635 and the first-conductivity-type heavily doped region 635. On the type substrate 41, a fifth opening 638 and a sixth opening 639 are formed in the fourth dielectric layer 636, the fifth opening 638 is used to expose the fourth polysilicon layer 633 at one end of the fourth trench structure 631, and the sixth opening 639 is used to expose the first conductive type heavily doped region 635, and the second metal layer 637 includes a fifth metal electrode 637a and a sixth metal electrode 637b, wherein the fifth metal layer 637a covers the fifth opening 638, and the sixth metal layer 637b covers the sixth opening 639.

[0087] In some embodiments, as Figure 7 As shown, the fifth metal layer 637a and the sixth metal layer 637b in the first-type MOS transistor test structure 63 are respectively connected to the third test electrode 73 and the fourth test electrode 74 through external leads, and the first conductive type substrate 41 in the first-type MOS transistor test structure 63 is electrically connected to the test base 8 to facilitate electrical testing of the first-type MOS transistor test structure 63.

[0088] Exemplarily, the process of forming the first-type MOS transistor test structure 63 may include the following steps:

[0089] Step S1: According to the chip manufacturing process, a test area 5 of the cutting path area 3 is etched through a mask. Figure 7 The fourth trench structure 631 shown has an etching depth of 2um to 10um;

[0090] Step S2: depositing a fourth insulating layer 632 in the fourth trench. Figure 2 The first insulating layer 421 is prepared in the same preparation process, and then a layer of polysilicon (POLY) is grown by chemical vapor deposition as the fourth polysilicon layer 633. Figure 2The first polysilicon layer 422 is prepared in the same preparation process, and then the polysilicon outside the fourth trench structure 631 is etched cleanly through processes such as exposure, development, and etching;

[0091] Step S3: See Figure 7 and Figure 8 The first conductive type substrate 41 is designed by different masks to define the second conductive type region 634 and the first conductive type heavily doped region 635, and then the second conductive type region 634 and the first conductive type heavily doped region 635 are formed by ion implantation, wherein the second conductive type region 634 and the first conductive type heavily doped region 635 are Figure 2 The second conductive type region 431 of the IGBT4 is prepared in the same preparation process, and the first conductive type heavily doped region 635 is prepared in the same preparation process. Figure 2 The first conductivity type heavily doped region 433 of the IGBT 4 is prepared in the same preparation process;

[0092] Step S4: forming a fourth dielectric layer 636 by CVD, and referring to Figure 8 After designing the mask, a fifth opening 638 and a sixth opening 639 are etched on the fourth dielectric layer 636. The fifth opening 638 and the sixth opening 639 are Figure 2 The second opening 441 and the fourth opening 442 are prepared in the same preparation process;

[0093] Step S5: forming a second metal layer 637 on the wafer surface by PVD sputtering. The second metal layer 637 and the first metal layer 45 are prepared in the same preparation process. The second metal layer 637 includes a fifth metal electrode 637a and a sixth metal electrode 637b. The fifth metal electrode 637a covers the fifth opening 638, and the sixth metal electrode 637b covers the sixth opening 639.

[0094] Step S6: Reference Figure 7 Metal wiring is etched through mask design to electrically connect the fifth metal electrode 637 a and the sixth metal electrode 637 b to the third test electrode 73 and the fourth test electrode 74 , respectively, and the first conductive type substrate 41 to the test base 8 .

[0095] See also Figure 7 and Figure 8 The specific steps of performing electrical testing on the first type MOS transistor test structure 63 are as follows:

[0096] The two probes of the WAT test machine are electrically connected to the third test electrode 73 and the fourth test electrode 74 respectively. A high level is applied to the third test electrode 73, that is, a high level is applied to the gate structure in the fourth trench structure 631. The first type MOS conductive channel in the vertical direction is opened. By applying a certain voltage to the test base 8 and a low level 0 to the fourth test electrode 74, a current is caused to flow from the third test electrode 73 through the first conductive type heavily doped region 635, the second conductive type region 634 and the first conductive type substrate 41 to the test base 8. The saturation current I of the first type MOS transistor can be measured. SAT When the voltage at the third test electrode 73 is increased in a certain step, the threshold voltage of the first type MOS tube can be tested by judging the current between the fourth test electrode 74 and the test base 8.

[0097] From the above analysis, it can be understood that in the electrical test of the first type MOS transistor test structure 63, the current flows through the vertical channel. Figure 2 The vertical conductive channel of the IGBT4 is the same, so the results of the electrical test of the first type MOS tube test structure 63 can be analyzed to determine whether Figure 2 In some embodiments, the structure diagram of the second type MOS tube test structure 64 and its preparation process can be referred to. Figure 9 and Figure 10 ,in Figure 9 This is a schematic diagram of the structure of the second type of MOS tube test structure provided in this application. Figure 10 This is a top view of the second type of MOS tube test structure provided in this application.

[0098] like Figure 9As shown, the second-type MOS transistor test structure 64 includes a first conductive type substrate 41, a fifth trench structure 641, a fifth insulating layer 642 and a fifth polysilicon layer 643, a second conductive type region 644, a fifth dielectric layer 645, and a third metal layer 647. The second conductive type region 644 is formed on the first surface 411 of the first conductive type substrate 41, the fifth trench structure 641 is formed in the second conductive type region 644 and extends to the first conductive type substrate 41, a fifth insulating layer 642 and a fifth polysilicon layer 643 are sequentially formed in the fifth trench structure 641, a fifth dielectric layer 645 is formed on the surface of the second conductive type region 644, and a seventh opening 646a, an eighth opening 646b, and a ninth opening 646c are formed in the fifth dielectric layer 645. The seventh opening 646a is used for The fifth polysilicon layer 643 is exposed at one end of the fifth trench structure 641, the eighth opening 646b and the ninth opening 646c are respectively used to expose the second conductive type region 644 on both sides of the fifth trench structure 641, and the third metal layer 647 is formed on the side of the fifth dielectric layer 645 away from the first conductive type substrate 41. The third metal layer 647 includes a seventh metal electrode 647a, an eighth metal electrode 647b and a ninth metal electrode 647c, which respectively cover the seventh opening 646a, the eighth opening 646b and the ninth opening 646c.

[0099] In some embodiments, as Figure 9 As shown, the seventh metal electrode 647a, the eighth metal electrode 647b and the ninth metal electrode 647c in the second type MOS transistor test structure 64 are electrically connected to the fifth test electrode 75, the sixth test electrode 76 and the seventh test electrode 77 through external leads, respectively, to facilitate electrical testing of the second type MOS transistor test structure 64.

[0100] Exemplarily, the process of forming the second-type MOS transistor test structure 64 may include the following steps:

[0101] Step S1: According to the chip manufacturing process, a test area 5 of the cutting path area 3 is etched through a mask. Figure 7 The fifth trench structure 641 shown has an etching depth of 2 μm to 10 μm;

[0102] Step S2: depositing a fifth insulating layer 642 in the fifth trench. Figure 2 The first insulating layer 421 in the first embodiment is prepared in the same preparation process, and then a layer of polysilicon (POLY) is grown by chemical vapor deposition as the fifth polysilicon layer 643. Figure 2 The first polysilicon layer 422 is prepared in the same preparation process, and then the polysilicon outside the fourth trench structure 641 is etched cleanly through processes such as exposure, development, and etching;

[0103] Step S3: See Figure 9 and Figure 10 , ion implantation is performed on the first conductive type substrate 41 to form a second conductive type region 644, and the second conductive type region 644 is connected to the first conductive type substrate 41. Figure 2 The second conductivity type region 431 of the insulated gate bipolar transistor 4 is prepared in the same preparation process;

[0104] Step S4: forming a fifth dielectric layer 645 by CVD, and referring to Figure 10 After designing the mask, a seventh opening 646a, an eighth opening 646b, and a ninth opening 646c are etched on the fifth dielectric layer 645. The seventh opening 646a exposes the fifth polysilicon layer 643 at one end of the fifth trench structure 641. The eighth opening 646b and the ninth opening 646c are used to expose the second conductive type regions 644 on both sides of the fifth trench structure 641, respectively. The seventh opening 646a, the eighth opening 646b, and the ninth opening 646c are used to expose the second conductive type regions 644 on both sides of the fifth trench structure 641. Figure 2 The second opening 441 and the fourth opening 442 are prepared in the same preparation process;

[0105] Step S5: forming a third metal layer 647 on the surface of the wafer by PVD sputtering, wherein the third metal layer 647 comprises a seventh metal electrode 647a, an eighth metal electrode 647b and a ninth metal electrode 647c, which respectively cover the seventh opening 646a, the eighth opening 646b and the ninth opening 646c. Figure 2 The first metal layer 45 is prepared in the same preparation process;

[0106] Step S6: Reference Figure 9 , metal wiring is etched out through mask design, so that the seventh metal electrode 647a, the eighth metal electrode 647b and the ninth metal electrode 647c are electrically connected to the fifth test electrode 75, the sixth test electrode 76 and the seventh test electrode 77 respectively.

[0107] See also Figure 9 and Figure 10 The specific steps of performing electrical testing on the second type MOS transistor test structure 64 are as follows:

[0108] The two probes of the WAT test machine are electrically connected to the fifth test electrode 75 and the sixth test electrode 76 or the seventh test electrode 77, respectively. A high voltage is applied to the fifth test electrode 75 to open the annular conductive channel horizontally surrounding the bottom of the fifth groove. Corresponding voltages are then applied to the sixth test electrode 76 and the seventh test electrode 77 to create a voltage difference between the sixth test electrode 76 and the seventh test electrode 77. This allows the saturation current of the second type MOS transistor to be measured. When a voltage is applied to the fifth test electrode 75 in a step-by-step manner, the threshold voltage of the second type MOS transistor can be measured by determining the current between the fifth test electrode 75 and the sixth test electrode 76 or the seventh test electrode 77.

[0109] From the above analysis, it can be understood that in the electrical test of the second type MOS transistor test structure 64, the current flows through the semicircular conductive channel at the bottom of the fifth trench 641. Figure 2 The semicircular conductive channel of the IGBT4 in the embodiment is the same, so the results of the electrical test of the second type MOS tube test structure 64 can be analyzed to determine whether the Figure 2 Whether the conductive performance of the semicircular conductive channel of IGBT4 meets the requirements.

[0110] The first type MOS transistor test structure 63 and the second type MOS transistor test structure 64 provided in the embodiment of the present application obtain electrical parameters of saturation current, saturation current and threshold voltage by conducting electrical tests on their respective conductive channels, thereby Figure 2 The ion doping concentrations of the first conductivity type heavily doped region 433 and the second conductivity type region 431 of the corresponding IGBT 4 are tested. The morphology of the first trench structure 42 can also be tested. For example, if the morphology of the first trench structure 42 is abnormal, the bottom chamfer of the first trench structure 42 will be too sharp, causing the electric field to concentrate at the sharp point, causing high impact ionization, thereby affecting the withstand voltage performance of the entire trench gate IGBT 4. Therefore, the abnormality of the first trench structure 42 is reflected by electrical parameters such as saturation current, saturation current and threshold voltage.

[0111] In the above embodiments of the present application, when the first conductivity type is N-type and the second conductivity type is P-type, the first type MOS transistor is an NMOS transistor and the second type MOS transistor is a PMOS transistor; or in other cases, when the first conductivity type is P-type and the second conductivity type is N-type, the first type MOS transistor is an NMOS transistor and the second type MOS transistor is a PMOS transistor.

[0112] In some embodiments, at least one of the first opening 441, the second opening 442, the third opening 616, the fourth opening 626, the fifth opening 638, the sixth opening 639, the seventh opening 646a, the eighth opening 646b, and the ninth opening 646c comprises a bowl-shaped opening structure. This bowl-shaped opening structure facilitates metallization and filling of openings with a small critical dimension (CD). Furthermore, the smooth etching morphology of the openings reduces the risk of metal cracks during subsequent metal etching, routing, and wire binding, thereby improving the success rate of wire binding.

[0113] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An insulated gate bipolar transistor wafer, characterized in that: A chip area and a test area are formed on the wafer. The chip area is provided with an insulated gate bipolar transistor with a trench gate structure. The test area is provided with a process structure to be tested, and the process structure to be tested is a trench test structure.

2. The wafer according to claim 1, wherein: The process structure to be tested is a wafer acceptability test structure.

3. The wafer according to claim 1, wherein: The test area is arranged in a dicing street area of the insulated gate bipolar transistor wafer.

4. The wafer according to any one of claims 1 to 3, wherein: The process structure to be tested includes at least one of a polysilicon test structure, a gate test structure, a first type MOS transistor test structure, and a second type MOS transistor test structure.

5. The wafer according to claim 4, wherein: At least one of the polysilicon test structure, the gate test structure, the first type MOS transistor test structure and the second type MOS transistor test structure is manufactured in the same manufacturing process as a part of the structure of the insulated gate bipolar transistor.

6. The wafer according to claim 5, characterized in that The insulated gate bipolar transistor comprises: A first conductive type substrate, and a first conductive type epitaxial layer formed on a first surface of the first conductive type substrate; A first trench structure is formed in the first conductive type epitaxial layer and extends to the first conductive type substrate, wherein a first insulating layer and a first polysilicon layer are sequentially formed in the first trench structure.

7. The wafer according to claim 6, wherein: The polysilicon test structure comprises: a first conductive type substrate; a second trench structure formed in the first conductive type substrate, wherein a second insulating layer and a second polysilicon layer are sequentially formed in the second trench structure, the second insulating layer and the first insulating layer being prepared in the same preparation process, and the second polysilicon layer and the first polysilicon layer being prepared in the same preparation process; and a first dielectric layer formed on a first surface of the first conductive type substrate, wherein two first openings are formed in the first dielectric layer, the two first openings being respectively used to expose the second polysilicon layer at both ends of the second trench structure; A first metal electrode covers the first opening.

8. The wafer according to claim 7, wherein: Two planar polysilicon structures are formed on the first surface of the first conductive type substrate, and the two planar polysilicon structures are respectively arranged at two ends of the second trench structure and electrically connected to the second polysilicon layer in the second trench structure; The first opening exposes the two planar polysilicon structures.

9. The wafer according to claim 8, characterized in that The number of the first openings disposed at each end of the second trench structure is at least two.

10. The wafer according to claim 5, wherein: The insulated gate bipolar transistor comprises: A first conductive type substrate, and a first conductive type epitaxial layer on a first surface of the first conductive type substrate; a first trench structure formed in the first conductive type epitaxial layer and extending to the first conductive type substrate, wherein a first insulating layer and a first polysilicon layer are sequentially formed in the first trench structure; a second dielectric layer covering the first polysilicon layer, wherein the second dielectric layer is provided with a second opening, and the second opening is used to expose the first polysilicon layer; A second metal electrode is formed on a side of the second dielectric layer away from the first conductive type substrate, and the second metal electrode covers the second opening.

11. The wafer according to claim 10, wherein: The gate test structure includes: the first conductive type substrate; a third trench structure formed in the first conductive type substrate, wherein a third insulating layer and a third polysilicon layer are sequentially formed in the third trench structure, the third insulating layer and the first insulating layer are prepared in the same preparation process, and the third polysilicon layer and the first polysilicon layer are prepared in the same preparation process; a third dielectric layer formed on the first surface of the first conductive type substrate, wherein a third opening is formed in the third dielectric layer, the third opening being used to expose the third polysilicon layer in the third trench structure, and the third opening and the second opening are prepared in the same preparation process; A third metal electrode covering the third opening is prepared in the same preparation process as the second metal electrode.

12. The wafer according to claim 5, wherein: The insulated gate bipolar transistor comprises: A first conductive type substrate, and a first conductive type epitaxial layer on a first surface of the first conductive type substrate; a first trench structure formed in the first conductive type epitaxial layer and extending to the first conductive type substrate, wherein a first insulating layer and a first polysilicon layer are sequentially formed in the first trench structure; a second conductivity type region formed in the first conductivity type epitaxial layer; forming a heavily doped region of the second conductivity type in the region of the second conductivity type; a first conductivity type heavily doped region formed in the second conductivity type region and connecting the first trench structure and the second conductivity type heavily doped region; a second dielectric layer covering the second conductive type region, wherein the second dielectric layer is provided with a second opening and a fourth opening, the second opening being used to expose the first polysilicon layer, and the fourth opening being used to expose the second conductive type heavily doped region; a first metal layer formed on a side of the second dielectric layer away from the first conductive type substrate, the first metal layer comprising a second metal electrode covering the second opening and a fourth metal electrode covering the fourth opening; a collector region formed on a second surface of the first conductive type substrate, the second surface being arranged opposite to the first surface; A collector is formed in the collector region away from the second surface.

13. The wafer according to claim 12, wherein: The first type MOS transistor test structure includes: a first conductive type substrate; a fourth trench structure formed in the first conductive type substrate, wherein a fourth insulating layer and a fourth polysilicon layer are sequentially formed in the fourth trench structure, the fourth insulating layer and the first insulating layer are prepared in the same preparation process, and the fourth polysilicon layer and the first polysilicon layer are prepared in the same preparation process; a second conductivity type region formed on one side of the fourth trench structure, wherein the second conductivity type region on one side of the fourth trench structure and the second conductivity type region of the insulated gate bipolar transistor are prepared in the same preparation process; a first conductivity type heavily doped region formed in the second conductivity type region, the first conductivity type heavily doped region being connected to the fourth trench structure, the first conductivity type heavily doped region connected to the fourth trench structure and the first conductivity type heavily doped region of the insulated gate bipolar transistor being prepared in the same preparation process; a fourth dielectric layer formed on the second conductivity type region and the first conductivity type substrate, wherein a fifth opening and a sixth opening are formed in the fourth dielectric layer, the fifth opening being used to expose the fourth polysilicon layer at one end of the fourth trench structure, and the sixth opening being used to expose the first conductivity type heavily doped region, and the fifth opening and the sixth opening being prepared in the same preparation process as the second opening and the fourth opening; A second metal layer is formed on a side of the fourth dielectric layer away from the first conductive type substrate, the second metal layer includes a fifth metal electrode covering the fifth opening, and a sixth metal electrode covering the sixth opening, and the second metal layer and the first metal layer are prepared in the same preparation process.

14. The wafer according to claim 12, wherein: The second type MOS tube test structure includes: a first conductive type substrate; A second conductivity type region is formed on the first surface of the first conductivity type substrate, wherein the second conductivity type region of the first surface and the second conductivity type region of the insulated gate bipolar transistor are prepared in the same preparation process; a fifth trench structure formed in the second conductivity type region and extending to the first conductivity type substrate, wherein a fifth insulating layer and a fifth polysilicon layer are sequentially formed in the fifth trench structure, the fifth insulating layer and the first insulating layer being prepared in the same preparation process, and the fifth polysilicon layer and the first polysilicon layer being prepared in the same preparation process; a fifth dielectric layer formed on a surface of the second conductivity type region, wherein a seventh opening, an eighth opening, and a ninth opening are formed in the fifth dielectric layer, the seventh opening being used to expose the fifth polysilicon layer at one end of the fifth trench structure, the eighth opening and the ninth opening being used to expose the second conductivity type regions on both sides of the fifth trench structure, respectively, and the seventh opening, the eighth opening, and the ninth opening being fabricated in the same fabrication process as the second opening and the fourth opening; A third metal layer is formed on a side of the fifth dielectric layer away from the first conductive type substrate, the third metal layer including a seventh metal electrode covering the seventh opening, an eighth metal electrode covering the eighth opening, and a ninth metal electrode covering the ninth opening, and the third metal layer and the first metal layer are prepared in the same preparation process.

15. The wafer according to any one of claims 7, 10, 11, 12, 13 and 14, characterized in that: At least one of the first opening, the second opening, the third opening, the fourth opening, the fifth opening, the sixth opening, the seventh opening, the eighth opening and the ninth opening includes a bowl-shaped opening structure.

16. The wafer according to any one of claims 7, 10, 11, 12, 13 and 14, characterized in that The test area is further provided with at least one test electrode, which is electrically connected to at least one of the second metal electrode, the third metal electrode, the fourth metal electrode, the fifth metal electrode, the sixth metal electrode, the seventh metal electrode, the eighth metal electrode and the ninth metal electrode.

17. The wafer according to any one of claims 12 to 14, characterized in that: The first conductivity type is N-type, and the second conductivity type is P-type; or, the first conductivity type is P-type, and the second conductivity type is N-type.

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