Controller data downloading link device, resource board card and test machine

By using a tree-like switch module in the controller data download link, the problem of data transmission reliability and low burning efficiency in daisy chain design is solved, and independent data transmission paths and efficient program burning is realized.

CN223217860UActive Publication Date: 2025-08-12HANGZHOU CHANGCHUAN TECH CO LTD
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Patent Information

Application Number
CN202422593883.3
Authority / Receiving Office
CN · China
Patent Type
Utility models(China)
Current Assignee / Owner
Filing Date
2024-10-25
Publication Date
2025-08-12
Estimated Expiration
2034-10-25

AI Technical Summary

Technical Problem

In the prior art, the controller data download link in the daisy chain design mode causes the daisy chain to break when a certain control chip works abnormally, resulting in low data transmission reliability and low burn-in efficiency.

Method used

A tree-like structure is used to build a switch module, and the control signal output from the signal output module is used to adjust the on-off of the switch, ensuring that the data accessed by the data interface is sent to the corresponding controller through the switch, realizing an independent data transmission path.

Benefits of technology

Improves the reliability and burning efficiency of data transmission, avoids the impact of daisy chain break on other controllers, shortens traces and simplifies the program selection process.

✦ Generated by Eureka AI based on patent content.

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Abstract

The utility model relates to a controller data downloading link device, a resource board card and a testing machine, a change-over switch module in the controller data downloading link device is constructed by utilizing a plurality of change-over switches and adopting a tree structure, and the on-off of the change-over switches is adjusted according to a control signal output by a signal output module, so that data accessed by a data interface are transmitted to a server through a data transmission module, and the data are transmitted to the server through a data transmission module. And the information is transmitted to the corresponding controller through the change-over switch. When a certain controller works abnormally, data downloading of other controllers is not affected, and the data transmission reliability is improved.
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Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a controller data download link device, a resource board, and a tester. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to inspect various parameters of devices under test (DUTs) and eliminate defective products to control the quality of semiconductors before they leave the factory. In a tester, if multiple identical control chips are required, a daisy chain design is often used to design the program download link to save costs and circuit board space. The control chips are connected through a daisy chain design, and program burning of multiple control chips is achieved through a single download port. If a control chip in the daisy chain malfunctions, the daisy chain will break, making program burning impossible, resulting in low data transmission reliability. Utility Model Content

[0003] Based on this, it is necessary to provide a controller data download link device, resource board and test machine that can improve data transmission reliability in order to address the above problems.

[0004] A first aspect of the present application provides a controller data download link device, comprising:

[0005] A signal output module outputs a control signal to the switch module;

[0006] The switching switch module is constructed using a tree structure using multiple switching switches. The switching switch module connects the data interface, the signal output module and multiple controllers, and adjusts the on and off of the switching switch according to the control signal output by the signal output module, so that the data accessed by the data interface is transmitted to the corresponding controller through the switching switch.

[0007] In one embodiment, the signal output module includes a switch unit and a power supply unit, the power supply unit is connected to a power supply terminal and the switch unit, and the switch unit is connected to the switch module.

[0008] In one embodiment, the switching switch module includes several levels of switching switches, and the switching switches at each level are connected to the switch unit, the switching switches at the first level are connected to the data interface, and the switching switches at at least the last level are connected to the link interface of the corresponding controller.

[0009] In one embodiment, the switch unit includes a multi-stage dip switch, and the power supply unit includes a plurality of voltage divider components; each of the voltage divider components is connected to a power supply terminal and a corresponding dip switch, and each dip switch is connected to a switching switch of a corresponding stage.

[0010] In one embodiment, in the switching switch module, the control end of each switching switch is connected to the corresponding dip switch, the static contact of each switching switch is connected to the moving contact of the previous level switching switch or the data interface, and the moving contact of each switching switch is connected to the static contact of the next level switching switch or the link interface of the corresponding controller.

[0011] In one embodiment, the control ends of the switches at the same level are connected to the same DIP switch.

[0012] In one embodiment, the data interface and the link interface are JTAG protocol interfaces.

[0013] In one embodiment, the switches at the first stage include a switch SPDT11 , a switch SPDT12 , a switch SPDT13 , and a switch SPDT14 ;

[0014] The control end of the switching switch SPDT11 is connected to the first-level dial switch, the static contact of the switching switch SPDT11 is connected to the TCK pin of the data interface, and the moving contact of the switching switch SPDT11 is connected to the static contact of the next-level switching switch;

[0015] The control end of the switching switch SPDT12 is connected to the first-level dial switch, the static contact of the switching switch SPDT12 is connected to the TMS pin of the data interface, and the moving contact of the switching switch SPDT12 is connected to the static contact of the next-level switching switch;

[0016] The control end of the switching switch SPDT13 is connected to the first-level dial switch, the static contact of the switching switch SPDT13 is connected to the TDI pin of the data interface, and the moving contact of the switching switch SPDT13 is connected to the static contact of the next-level switching switch;

[0017] The control end of the switching switch SPDT14 is connected to the first-stage dial switch, the static contact of the switching switch SPDT14 is connected to the TDO pin of the data interface, and the moving contact of the switching switch SPDT14 is connected to the static contact of the next-stage switching switch.

[0018] A second aspect of the present application provides a resource board, comprising a data interface, a controller and the above-mentioned controller data download link device.

[0019] In one embodiment, the controller is a PFGA.

[0020] A third aspect of the present application provides a testing machine, comprising the above-mentioned resource board.

[0021] In the controller data download link device, resource board, and tester, the switch module in the controller data download link device utilizes multiple switches in a tree-like structure. The switches are turned on and off according to control signals output by the signal output module, so that data received by the data interface is transmitted to the corresponding controller via the switches. This improves data transmission reliability by allowing a controller to malfunction without affecting data downloads from other controllers. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A structural block diagram of a controller data download link device in one embodiment;

[0023] Figure 2 A schematic diagram of the structure of a controller data download link device in one embodiment;

[0024] Figure 3 It is a structural principle diagram of a controller data download link device in another embodiment. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0027] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if there is transmission of electrical signals or data between the connected circuits, modules, units, etc.

[0028] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, operations, components, parts, or combinations thereof.

[0029] In the circuit board of the current test machine, if it is necessary to use multiple control chips of the same type, the daisy chain design mode is often used for link design, which will result in too long wiring and realize the program burning of multiple control chips through one download port. When a control chip in the daisy chain works abnormally due to power supply or chip problems, it will cause the daisy chain to break, which will lead to the inability to perform program burning; and when using the daisy chain structure, in the software burning selection, it is also necessary to synchronously build the same daisy chain structure (select the corresponding number of programs) to select a specific control chip for program burning, which has certain inconveniences in the use scenario and low burning efficiency. Based on this, the present application provides a controller data download link device, the switching switch module is built with a tree structure using multiple switching switches, and the on-off of the switching switch is adjusted according to the control signal output by the signal output module, so that the data accessed by the data interface is delivered to the corresponding controller through the switching switch. When a certain controller has a working abnormality, it does not affect the data download of other controllers, improves data transmission reliability, can also shorten the wiring, and does not need to select multiple programs at the same time when burning, improves burning efficiency.

[0030] In one embodiment, a controller data download link device is provided, which is suitable for programming multiple controllers of the same type. Figure 1 As shown, the controller data download link device includes a signal output module 110 and a switching switch module 120. The signal output module 110 outputs a control signal to the switching switch module 120. The switching switch module 120 is constructed using a tree structure using multiple switching switches. The switching switch module 120 connects the data interface 210, the signal output module 110 and multiple controllers 220. The switching switch is adjusted to be on or off according to the control signal output by the signal output module 110, so that the data accessed by the data interface 210 is transmitted to the corresponding controller 220 through the switching switch.

[0031] The type and number of controllers 220 are not unique. The controller 220 can be a chip such as an FPGA, CPU, or MCU, and the number of controllers 220 can be two or more. The switch module 120 is constructed using multiple switches in a tree structure, with the data interface 210 as the root. The switches split the signal into two or four signals, respectively, to establish a link from one data interface 210 to multiple controllers 220. The switches can be single-pole, double-throw analog switches.

[0032] The specific type of the signal output module 110 is not unique, and the control signal may be sent in the form of a switch, or may be sent through other structures such as a control chip. Figure 2As shown, the signal output module 110 may include a switch unit 112 and a power supply unit 114. The power supply unit 114 is connected to the power supply terminal and the switch unit 112, and the switch unit 112 is connected to the switching module 120. The power supply unit 114 supplies power to the switch unit 112 according to the power supply connected to the power supply terminal, and adjusts the switch state in the switch unit 112 to send a control signal (level 0 or 1) to the corresponding switch in the switching module 120, thereby changing the link state.

[0033] Furthermore, the switching module 120 includes several levels of switching switches, and the switching switches at each level are connected to the switch unit 112, the switching switches at the first level are connected to the data interface 210, and the switching switches at at least the last level are connected to the link interface of the corresponding controller 220. Among them, the switching switches can be divided into two or more levels, and the number of levels of switching switches and the number of switching switches in each level need to be set according to the number of controllers 220 and the type of link interface. In this embodiment, the data interface 210 and the link interface are JTAG (Joint Test Action Group) protocol interfaces. The JTAG protocol includes four signal lines: TCK (clock line), TMS (mode select line), TDI (data input line) and TDO (data output line). By controlling the on-off of the switching switches in the switching module 120, the JTAG link between the data interface 210 and each controller 220 is switched, thereby programming the corresponding controller 220.

[0034] In one embodiment, the switch unit 112 includes a multi-stage DIP switch, and the power supply unit 114 includes a plurality of voltage divider components 1142; each voltage divider component 1142 is connected to a power supply terminal and a corresponding DIP switch, and each DIP switch is connected to a corresponding level of switching switch. The number of DIP switches in the switch unit 112 corresponds to the number of levels of switching switches, and the number of voltage divider components 1142 corresponds to the number of DIP switches. The voltage divider components 1142 divide the input power supply so that the divided voltage meets the drive level of the switching switch. Specifically, the resistors in the voltage divider components 1142 must be selected to ensure that the drive current meets the requirements of the switching switch. By toggling the DIP switch, switching between levels 0 and 1 can be achieved, thereby allowing the multi-stage DIP switches to be combined into different combination modes.

[0035] Specifically, in the switch module 120, the control end of each switch is connected to the corresponding dial switch, the static contact of each switch is connected to the dynamic contact of the previous switch or the data interface 210, and the dynamic contact of each switch is connected to the static contact of the next switch or the link interface of the corresponding controller 220. Figure 2As shown, the switches at the first stage include switch SPDT11 , switch SPDT12 , switch SPDT13 and switch SPDT14 , and the control ends of the switches at the first stage are all connected to the same DIP switch. The control end of the switching switch SPDT11 is connected to the first-level dial switch, the static contact of the switching switch SPDT11 is connected to the TCK pin of the data interface 210, and the moving contact of the switching switch SPDT11 is connected to the static contact of the next-level switching switch; the control end of the switching switch SPDT12 is connected to the first-level dial switch, the static contact of the switching switch SPDT12 is connected to the TMS pin of the data interface 210, and the moving contact of the switching switch SPDT12 is connected to the static contact of the next-level switching switch; the control end of the switching switch SPDT13 is connected to the first-level dial switch, the static contact of the switching switch SPDT13 is connected to the TDI pin of the data interface 210, and the moving contact of the switching switch SPDT13 is connected to the static contact of the next-level switching switch; the control end of the switching switch SPDT14 is connected to the first-level dial switch, the static contact of the switching switch SPDT14 is connected to the TDO pin of the data interface 210, and the moving contact of the switching switch SPDT14 is connected to the static contact of the next-level switching switch.

[0036] Continue to refer to Figure 2 , using two DIP switches to program four FPGAs as an example. The four FPGAs are numbered A, B, C, and D. Setting up a JTAG link requires a total of 12 switches. Switches SPDT11, SPDT12, SPDT13, and SPDT14 serve as first-stage switches, while switches SPDT21, SPDT22, SPDT23, SPDT24, SPDT25, SPDT26, SPDT27, and SPDT28 serve as second-stage switches. Switch unit 112 includes two DIP switches, namely, first-stage and second-stage DIP switches. Resistors R1 and R2 form a voltage divider component 1142, and resistors R3 and R4 form another voltage divider component 1142. After resistors R1 and R2 are connected in series, their common end is connected to the first end of the second-stage DIP switch. The second end of the second-stage DIP switch is connected to the control end of each second-stage switch through port ctrl1, and a control signal is output to each second-stage switch. The other end of resistor R1 is connected to the power supply, and the other end of resistor R2 is grounded. After resistors R3 and R4 are connected in series, their common end is connected to the first end of the first-stage DIP switch. The second end of the first-stage DIP switch is connected to the control end of each first-stage switch through port ctrl0, and a control signal is output to each first-stage switch. The other end of resistor R4 is connected to the power supply, and the other end of resistor R3 is grounded.

[0037] Specifically, the first moving contact of switching switch SPDT11 is connected to the static contact of switching switch SPDT21, the second moving contact of switching switch SPDT11 is connected to the static contact of switching switch SPDT22, the first moving contact of switching switch SPDT12 is connected to the static contact of switching switch SPDT23, the second moving contact of switching switch SPDT12 is connected to the static contact of switching switch SPDT24, the first moving contact of switching switch SPDT13 is connected to the static contact of switching switch SPDT25, the second moving contact of switching switch SPDT13 is connected to the static contact of switching switch SPDT26, the first moving contact of switching switch SPDT14 is connected to the static contact of switching switch SPDT27, and the second moving contact of switching switch SPDT14 is connected to the static contact of switching switch SPDT28.

[0038] Switches SPDT21 and SPDT22 each have two moving contacts, for a total of four moving contacts, connected to the TCK pins of four FPGAs. Switches SPDT23 and SPDT24 each have two moving contacts, for a total of four moving contacts, connected to the TMS pins of four FPGAs. Switches SPDT25 and SPDT26 each have two moving contacts, for a total of four moving contacts, connected to the TDI pins of four FPGAs. Switches SPDT27 and SPDT28 each have two moving contacts, for a total of four moving contacts, connected to the TDO pins of four FPGAs.

[0039] By toggling the DIP switch, the levels 0 and 1 can be switched, resulting in four combinations: 00, 01, 10, and 11, which are used to switch the switch. The truth table for the four FPGAs is shown in Table 1, which shows the order of the four FPGAs connected according to the four DIP switch combinations: 00, 01, 10, and 11.

[0040] Table 1

[0041] Ctrl 0 Ctrl 1 FPGA connection serial number 0 0 A 0 1 B 1 0 C 1 1 D

[0042] When the dip switch is switched to mode 00, the JTAG link path of FPGA A can be realized; when the dip switch is switched to mode 01, the JTAG link path of FPGA B can be realized; when the dip switch is switched to mode 10, the JTAG link path of FPGA C can be realized; when the dip switch is switched to mode 11, the JTAG link path of FPGA A can be realized.

[0043] It is understandable that when more FPGAs need to be programmed, the number of levels of switches can be further expanded. Figure 3The figure shows a tree topology of five FPGAs. By adding switches, the topology is modified to achieve the establishment of a JTAG link for the five FPGAs. Figure 3 The tree topology in Figure 2 The difference lies in the addition of a third level of switches: switch SPDT31, switch SPDT32, switch SPDT33, and switch SPDT34. Switch unit 112 is equipped with three levels of dip switches, and power supply unit 114 is equipped with three voltage divider components 1142 to supply power to the corresponding dip switches. The three levels of dip switches are connected to the control terminals of the switches in the first, second, and third levels via ports ctrl0, ctrl1, and ctrl2, respectively. The static contact of the third-level switch is connected to a moving contact of the corresponding switch in the second level. The two moving contacts of the third-level switch are connected to corresponding pins of FPGA A and FPGA B, respectively. The remaining moving contacts of the second-level switch are connected to corresponding pins of FPGA C, FPGA D, and FPGA E, respectively.

[0044] The truth table of the switching of the five FPGAs is shown in Table 2. The link switching of the five FPGAs is achieved by combining the three control signals.

[0045] Table 2

[0046] Ctrl0 Ctrl1 Ctrl2 FPGA connection serial number 0 0 0 A 0 0 1 B 0 1 / C 1 0 / D 1 1 / E

[0047] In the controller data download link device provided by this application, each FPGA's JTAG link is an independent link, and the rectification link will not be affected by the failure of other FPGAs. When downloading a program, there is no need to repeatedly select multiple programs in the software, which can better save time and cost and greatly reduce the complexity of the operation. In addition, since analog switches are used for link switching, each JTAG link is relatively independent and has a short routing, so the driving capability can be guaranteed, without the need to add additional link buffers to enhance the driving capability.

[0048] In one embodiment, a resource board is provided, comprising a data interface, a controller, and the controller data download link device. The controller may be a chip such as PFGA, CPU, or MCU.

[0049] In one embodiment, a test machine is provided, comprising the aforementioned resource board. The test machine may further include a host computer connected to a data interface, which transmits data to the data interface to program each controller. The host computer may be, but is not limited to, various personal computers, laptops, smartphones, tablet computers, and portable wearable devices. The portable wearable devices may include smart watches, smart bracelets, head-mounted devices, and the like.

[0050] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0051] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A controller data download link device, characterized in that: include: A signal output module outputs a control signal to the switch module; The switching switch module is constructed using a tree structure using multiple switching switches. The switching switch module connects the data interface, the signal output module and multiple controllers, and adjusts the on and off of the switching switch according to the control signal output by the signal output module, so that the data accessed by the data interface is transmitted to the corresponding controller through the switching switch.

2. The device according to claim 1, characterized in that The signal output module includes a switch unit and a power supply unit. The power supply unit is connected to a power supply terminal and the switch unit. The switch unit is connected to the switch module.

3. The device according to claim 2, characterized in that The switching switch module includes several levels of switching switches, and the switching switches at each level are connected to the switch unit, the switching switches at the first level are connected to the data interface, and the switching switches at at least the last level are connected to the link interface of the corresponding controller.

4. The device according to claim 3, characterized in that The switch unit includes a multi-stage dial switch, and the power supply unit includes a plurality of voltage dividing components; each voltage dividing component is connected to a power supply terminal and a corresponding dial switch, and each dial switch is connected to a switching switch of a corresponding stage.

5. The device according to claim 4, characterized in that In the switching switch module, the control end of each switching switch is connected to the corresponding dial switch, the static contact of each switching switch is connected to the moving contact of the previous level switching switch or the data interface, and the moving contact of each switching switch is connected to the static contact of the next level switching switch or the link interface of the corresponding controller.

6. The device according to claim 5, characterized in that The control ends of the switches at the same level are connected to the same DIP switch.

7. The device according to claim 6, characterized in that The data interface and the link interface are JTAG protocol interfaces.

8. The device according to claim 7, characterized in that The switches at the first stage include a switch SPDT11, a switch SPDT12, a switch SPDT13, and a switch SPDT14; The control end of the switching switch SPDT11 is connected to the first-level dial switch, the static contact of the switching switch SPDT11 is connected to the TCK pin of the data interface, and the moving contact of the switching switch SPDT11 is connected to the static contact of the next-level switching switch; The control end of the switching switch SPDT12 is connected to the first-level dial switch, the static contact of the switching switch SPDT12 is connected to the TMS pin of the data interface, and the moving contact of the switching switch SPDT12 is connected to the static contact of the next-level switching switch; The control end of the switching switch SPDT13 is connected to the first-level dial switch, the static contact of the switching switch SPDT13 is connected to the TDI pin of the data interface, and the moving contact of the switching switch SPDT13 is connected to the static contact of the next-level switching switch; The control end of the switching switch SPDT14 is connected to the first-stage dial switch, the static contact of the switching switch SPDT14 is connected to the TDO pin of the data interface, and the moving contact of the switching switch SPDT14 is connected to the static contact of the next-stage switching switch.

9. A resource board, characterized in that: It comprises a data interface, a controller and the controller data download link device according to any one of claims 1 to 8.

10. A testing machine, characterized in that: Including the resource board as claimed in claim 9.