Memory device

Abstract

A memory device comprises a plurality of first decoding lines. A plurality of first decoding lines are disposed in the first metallization layer and extend in a first direction. Each of the plurality of first decoding lines includes at least a first segment and a second segment respectively coupled to the plurality of first memory cells and the plurality of second memory cells. A first segment and a second segment of each of the plurality of first decoding lines are arranged side by side along a first direction.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and more particularly to a memory device having multiple decode lines that can be coupled to multiple memory cells. Background Art

[0002] The semiconductor industry has experienced rapid growth due to a series of improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). The improvement in integration density comes primarily from the continuous reduction in the size of the minimum feature, which allows more components to be integrated into a given area. Utility Model Content

[0003] This disclosure provides a memory device comprising a plurality of first decode lines. The plurality of first decode lines are disposed in a first metallization layer and extend in a first direction. Each of the plurality of first decode lines comprises at least a first segment and a second segment, each coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and the second segment of each of the plurality of first decode lines are arranged side by side along the first direction.

[0004] This disclosure provides a memory device comprising a memory array, a memory controller, and a plurality of first decoding lines. The memory array comprises a plurality of first memory cells and a plurality of second memory cells. The memory controller is physically adjacent to the plurality of first memory cells, and the plurality of second memory cells are physically opposite the plurality of first memory cells along a first direction with the memory controller as the center. The memory controller is configured to provide a plurality of decoding signals to the memory array. The plurality of first decoding lines are disposed in a first metallization layer and extend in a first direction. Each of the plurality of first decoding lines comprises at least a first segment and a second segment, each coupled to the plurality of first memory cells and the plurality of second memory cells.

[0005] This disclosure provides a memory device comprising a substrate, a memory array, a decoder, and a plurality of decoder lines. The memory array is formed in a first region of the substrate and includes a first portion and a second portion. Circuitry for the decoder is formed in a second region of the substrate. A plurality of decoder lines are formed in a first of a plurality of metallization layers on the substrate, each of the plurality of decoder lines including a first segment and a second segment separated from each other along a first lateral direction. The first segment and the second segment of each of the plurality of decoder lines are respectively coupled to the first portion and the second portion of the memory array. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the embodiments of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 depicts a block diagram of a memory device according to various embodiments;

[0008] Figure 2 Schematic diagrams of example word line (WL) decoders of memory devices according to various embodiments are shown;

[0009] Figure 3 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0010] Figure 4 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0011] Figure 5 depicts a schematic diagram of an example WL decoder and an example memory controller according to various embodiments;

[0012] Figure 6 illustrates an example set of signals provided by a memory controller according to various embodiments;

[0013] Figure 7 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0014] Figure 8 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0015] Figure 9 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0016] Figure 10 depicts a schematic diagram of an example WL decoder according to various embodiments;

[0017] Figure 11 depicts a flowchart of an example method for operating a WL decoder according to some embodiments; and

[0018] Figure 12 A flowchart illustrating an example method for forming a memory device according to some embodiments is shown.

[0019]

Explanation of symbols

[0020] 105:Memory Controller

[0021] 107:Signal

[0022] 112: Input / Output (I / O) Circuit

[0023] 114: Word Line (WL) Decoder

[0024] 120:Memory array

[0025] 200:WL decoder

[0026] 201F: Far side

[0027] 201N: Near side

[0028] 205:Decoding signal

[0029] 210, 210F, 210N: M1 track

[0030] 220, 220F, 220N: M2 track

[0031] 240:M4 track

[0032] 251: first through-hole structure

[0033] 252: Second through-hole structure

[0034] 253: third through-hole structure

[0035] 270:WLPY Circuit

[0036] 300A,300B:WL decoder

[0037] 302A, 302B: Width

[0038] 304A, 304B: Width

[0039] 310A: First Distance

[0040] 310B: Second distance

[0041] 410:M2 fragment

[0042] 420: first two columns

[0043] 500:WL decoder

[0044] 505:Memory controller

[0045] 510F:DEC_X0F <7>

[0046] 510N:DEC_X0N <7>

[0047] 605:WLDRV4

[0048] 610:DEC_X2

[0049] 615:DEC_X1

[0050] 620:DEC_X0

[0051] 620F:DEC_X0<7:4>

[0052] 620N:DEC_X0<3:0>

[0053] 700:WL decoder

[0054] 710F: Second part of the signal / second signal

[0055] 710N: First part of the signal / first signal

[0056] 800:WL decoder

[0057] 810-1~810-9: Bimetallic Track

[0058] 900:WL decoder

[0059] 901F: Far side

[0060] 901N: Near side

[0061] 910F,910N:M1 track

[0062] 920F,920N:M2 track

[0063] 1000:WL decoder

[0064] 1010F, 1010N: M1 track

[0065] 1020F, 1020N: M2 track

[0066] 1100: Method

[0067] 1110, 1120, 1130: Operation

[0068] 1200: Method

[0069] 1210, 1220, 1230: Operation DETAILED DESCRIPTION

[0070] The following disclosure provides many different embodiments or examples to implement the different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the embodiments of this disclosure may repeat element symbols and / or letters in each example. This repetition is for simplicity and clarity purposes and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0071] Furthermore, for ease of description, spatially relative terms (such as "below," "beneath," "lower," "above," "upper," and the like) may be used herein to describe the relationship of one element or feature to another element (or elements) or feature (or features) illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted similarly.

[0072] As integrated circuit technology advances, IC features have been reduced, allowing for more circuitry to be implemented within an IC. Implementing memory devices within an IC can present various challenges. For example, in a word line (WL) decoder that utilizes a large number of metal conductors, the metal tracks (e.g., decoder lines) can occupy a significant amount of space and / or create excessive parasitic resistance and capacitance (RC) values. This can result in delays in providing WL decode signals, increasing access and setup times.

[0073] This disclosure provides various embodiments of memory devices and word line decoders. The techniques disclosed herein provide a solution for reducing RC values in word line decoders, thereby reducing RC delay when providing WL decoded signals and improving access and setup times. The techniques disclosed herein include utilizing both M4 and M2 rails (e.g., parallel M2 and M4 rails) for signal connections, with the M4 rails positioned perpendicularly above the M2 rails. This reduces parasitic resistance while also allowing for shared space (e.g., reducing the back-end area for metal wiring by 50%). The configuration of M2 and M4 rails and controlled dimensions (e.g., width) provides design flexibility that can be tailored to various scenarios (e.g., resistance-dominated, back-end capacitance-dominated, front-end capacitance-dominated, etc.). The techniques disclosed herein can be applied to various memory technologies, including SRAM, RRAM, MRAM, phase change memory, NVM, NOR memory, NAND memory, e-fuse memory, OTP memory, BEOL memory, and others.

[0074] Figure 1 FIG. 1 shows a block diagram of a memory device 100 according to various embodiments. The memory device 100 includes a memory array 120, a memory controller 105, an input / output (I / O) circuit 112, and a word line (WL) decoder 114. Figure 1 Although not explicitly shown, the memory device 100 may include other components (eg, a bit line controller, etc.). Figure 1 Although not explicitly shown, the components in the memory device 100 may be operatively coupled to each other and to the memory controller 105. For example, in some embodiments, a heater may be included in the memory device 100 and thermally coupled to at least the memory array 120, while the memory controller 105, I / O circuit 112, WL decoder 114, and other components may be electrically coupled to the memory array 120. Figure 1 In the example shown, for clarity of illustration, the elements are depicted as separate blocks, but in some other embodiments, Figure 1 Some or all of the components shown in FIG. 1 may be integrated together. For example, the memory array 120 may include the I / O circuit 112 embedded therein.

[0075] The memory array 120 is implemented as a semiconductor memory device. The memory array 120 includes a plurality of storage circuits or memory cells. The memory array 120 includes word lines WL0, WL1, ..., WLJ (not shown) and bit lines BL0, BL1, ..., BLK (not shown), each word line extending in a vertical direction (e.g., the Y direction) and each bit line extending in a horizontal direction (e.g., the X direction). The word lines WL and the bit lines BL can be conductive metals or conductive rails. In one configuration, each memory cell is coupled to a corresponding word line WL and a corresponding bit line BL, and can operate according to a voltage or current flowing through the corresponding word line and the corresponding bit line. In some embodiments, each bit line includes a bit line BL, which is coupled to one or more memory cells in a group of memory cells arranged along a horizontal direction (e.g., the X direction). The bit line BL can receive and / or provide a differential signal. Each memory unit may include volatile memory, non-volatile memory, or a combination thereof. In some embodiments, each memory unit is implemented as a static random access memory (SRAM) unit or other types of memory units.

[0076] The WL decoder 114 is a hardware component that can receive a signal 107 from the memory controller 105. The signal 107 can include a WL address of the memory array 120 and can identify a conductive structure (e.g., a word line) at the column address. Although not depicted in the figures, the memory device 100 can include a bit line (BL) decoder and a hardware component that can receive a row address of the memory array 120 and identify one or more conductive structures (e.g., a bit line, a source line) at the row address.

[0077] I / O circuit 112 is a hardware component that can access (e.g., read, program) each memory cell in memory array 120 identified by WL decoder 114 and BL decoder. For example, a plurality of switch / select transistors may form I / O circuit 112. In some embodiments, memory array 120 may be formed in a first region of a substrate, while I / O circuit 112 may be formed in a second region of the substrate. The second region may be configured as a closed ring or an open ring surrounding the first region.

[0078] The memory controller 105 is a hardware component that controls the operation of the memory array 120. Figure 1As shown, the memory controller 105 may be physically adjacent to the WL decoder 114. The memory controller 105 includes and / or controls the BL decoder, I / O circuitry 112, the WL decoder 114, and the like. In some examples, the BL decoder, I / O circuitry 112, the WL decoder 114, and the like may be implemented as logic circuits, analog circuits, or a combination thereof. In one configuration, the WL decoder 114 is a circuit that provides a voltage or current flowing through one or more WLs in the memory array 120, and the BL decoder (not shown) is a circuit that provides or senses a voltage or current flowing through one or more BLs in the memory array 120. The WL decoder 114 may include a plurality of metal rails and a plurality of drivers to provide a voltage or current to the memory array 120. For example, the WL decoder 114 may include at least a first set of metal rails for receiving the signal 107 from the memory controller 105 and may include at least a second set of metal rails for transmitting the decoded signal to the memory array 105. The memory controller 105 may provide decoded signals to different memory cells via different pairings of the first set and the second set of metal tracks. In one configuration, the memory controller 105 may control a voltage supply circuit included therein to provide voltage signals to the BL decoder, the I / O circuit 112, the WL decoder 114, etc. In some embodiments, such a voltage supply circuit is implemented as or includes a processor and a non-transitory computer-readable medium for storing instructions, wherein the instructions, when executed by the processor, cause the processor to perform one or more functions of the memory controller 105 described in this disclosure. The BL decoder may be coupled to the BL in the memory array 120, and the WL decoder 114 may be coupled to the WL in the memory array 120. In some embodiments, the memory controller 105 includes a processor and a non-transitory computer-readable medium for storing instructions, wherein the instructions, when executed by the processor, cause the processor to perform one or more functions of the memory controller 105 described in this disclosure. The BL decoder may be coupled to the BL in the memory array 120, and the WL decoder 114 may be coupled to the WL in the memory array 120. In some embodiments, the memory controller 105 includes a processor and a non-transitory computer-readable medium for storing instructions. Figure 1 More, fewer or different elements may be shown.

[0079] The WL decoder 114 includes multiple front-side metallization layers. Each front-side metallization layer includes multiple back-end interconnect structures, metal conductors (e.g., decode lines), and via structures, which are embedded in corresponding dielectric materials (e.g., inter-metal dielectrics (IMDs)). For example, the memory device 100 includes any number of front-side metallization layers (e.g., M0, M1, M2, etc.). Each front-side metallization layer includes multiple metal conductors (e.g., decode lines). Front-side metallization layer M0 includes decode lines (sometimes referred to as "M0 tracks") and via structures (sometimes referred to as "V0"); front-side metallization layer M1 includes decode lines (sometimes referred to as "M1 tracks") and via structures (sometimes referred to as "V1"); and front-side metallization layer M2 includes decode lines (sometimes referred to as "M2 tracks"). Similarly, the memory device 100 may include any number of front-side metallization layers, each including multiple decode lines and multiple via structures.

[0080] Figure 2 A schematic diagram of an example WL decoder 200 of a memory device (eg, memory device 100) according to various embodiments is shown. The WL decoder 200 is an example WL decoder of the WL decoder 114. The WL decoder 200 includes multiple metallization layers, each of which includes multiple decode lines.

[0081] The WL decoder 200 includes a plurality of first decode lines disposed in a first metallization layer and extending in a first direction (e.g., the X direction). The first decode lines may be M2 rails 220. As shown in the figures, each M2 rail 220 includes at least a first segment and a second segment operably coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and the second segment of each M2 rail 220 are arranged side by side along the first direction. The first segment may be an M2 rail 220N located at the proximal side 201N, and the second segment may be an M2 rail 220F located at the distal side 201F. The M2 rails 220N and 220F may be collectively referred to as M2 rails 220. The WL decoder 200 includes a plurality of second decode lines disposed in a second metallization layer and extending in a second direction (e.g., the Y direction). The second decode lines may be M1 rails 210. The M1 rail 210N is located at the proximal side 201N, while the M1 rail 210F is located at the distal side 201F. The M1 rails 210N and 210F may be collectively referred to as the M1 rail 210 .

[0082] A first segment (e.g., 220N) of each M2 rail 220 is operably coupled to a first subset of first memory cells via a first subset of M1 rails 210, and a corresponding second segment (e.g., 220F) of the M2 rail 220 is operably coupled to a first subset of second memory cells via a second subset of M1 rails 210. The first subset of M1 rails 210 and the second subset of M1 rails 210 are separated from each other in a first direction by one or more other subsets of M1 rails 210. In some examples, the second metallization layer (e.g., M1 rails) is disposed vertically below the first metallization layer (e.g., M2 rails).

[0083] The WL decoder 200 includes a plurality of third decode lines disposed in a third metallization layer and extending in a first direction. The third decode lines may be M4 rails 240. Each M4 rail extends across a first segment (e.g., 220N) and a second segment (e.g., 220F) of a corresponding one of the plurality of M2 rails 220. In some examples, the M4 rails 240 are disposed vertically above the M2 rails 220. In some examples, each M4 rail 240 is operably coupled only to the second segment (e.g., 220F) of the corresponding M2 rail. Although Figure 2Although not depicted, in some examples, the WL decoder 200 may include additional metallization layers (e.g., an M3 track disposed between the M2 track 220 and the M1 track 210). In some examples, the sheet resistance of the M4 track 240 may be lower than the sheet resistance of the M2 track 220, thereby reducing the parasitic resistance of the decoded line.

[0084] The WL decoder 200 includes a plurality of via structures, including a plurality of first via structures 251, a plurality of second via structures 252, and a plurality of third via structures 253 (collectively referred to as via structures 250). The via structures 250 can operably connect different metallization layers. Each first via structure 251 can operably connect one of the M1 rails 210 to one of the M2 rails 220. In some examples, each first via structure 251 can operably connect one of the M1 rails 210N (located at the proximal side 201N) to one of the M2 rails 220N (located at the proximal side 201N). Each second via structure 252 can operably connect one of the M2 rails 220 and one of the M3 rails (not shown). Each third via structure 253 can operably connect one of the M3 rails (not shown) to one of the M4 rails 240. In some examples, each third via structure 253 can operably connect one of the M3 rails (not shown) to one of the M4 rails 240F (located at the distal side 201F). Figure 2 As shown, the WL decoder 200 may include or be connected to a WLPY circuit 270. The memory controller (e.g., 105) may provide decoded signals (e.g., 107, 205) to the memory array 120 via metal rails (e.g., M1, M2, etc.) and the WLPY circuit 270. The WLPY circuit 270 may include or be implemented as a logic circuit (e.g., a NOR gate, an AND gate, etc.). For example, each WLPY circuit 270 may receive a corresponding decoded signal, process the multiple signals via one or more logic circuits (e.g., a NOR gate, an AND gate, etc.), and provide the processed signals to the WL driver.

[0085] In some examples, each M2 rail 220 has a first width extending in a second direction (e.g., Y direction) perpendicular to the first direction (e.g., X direction), and each M4 rail 240 has a second width in the second direction. In some examples, the second width is smaller than the first width.

[0086] In some instances, Figure 1The memory controller 105 can be physically adjacent to the WL decoder 200. For example, the memory controller 105 can be physically adjacent to the M1 track 210N (located at the proximal side 201N), while the M1 track 210F (located at the distal side 201F) is centered about the memory controller 105 relative to the M1 track 210N. The memory controller 105 can provide a decode signal 205 (e.g., DEC_X2<0:7>) to enable the first set of memory cells and the second set of memory cells via at least the M2 track 220. The decode signal 205 can be part of the signal 107 that the memory controller 105 can provide to the WL decoder 114. For example, the memory controller 105 may provide the signal DEC_X2<0:3> to WLPY<0:31> of the WLPY circuit 270 via the M2 rail 220N at the near side 201N, and provide the signal DEC_X2<4:7> to WLPY<32:63> of the WLPY circuit 270 via the M2 rail 220F and the M4 rail 240 at the far side 201F. In various embodiments, the M2 rail 220F and the M4 rail 240 run parallel to each other and are connected. By connecting the M2 rail 220F and the M4 rail 240 in parallel, parasitic resistance at the far side 201F can be advantageously reduced.

[0087] In some embodiments, each WLPY circuit 270 can be implemented as a NOR gate. Each WLPY circuit 270 has a first input and a second input for receiving a corresponding bit in the decoded signal 205 (e.g., DEC_X2<0:7>) and a corresponding bit in another decoded signal (e.g., DEC_X1), respectively. Each WLPY circuit 270 can perform a NOR operation on the received bits and provide an output signal, which can be further ANDed with another decoded signal (e.g., DEC_X0) to determine a specific word line WL. The details of the decoded signals DEC_X2, DEC_X1, and DEC_X0 will be described in detail in the following. Figure 6 and Figure 7 Discussed in.

[0088] Figure 3 Schematic diagrams of example WL decoders 300A and 300B are shown according to various embodiments. The WL decoders 300A and 300B can be substantially similar to or identical to the WL decoder 200. For example, the WL decoders 300A and 300B can be examples of the WL decoder 200. For example, the WL decoders 300A and 300B include an M1 track (e.g., 210), an M2 track (e.g., 220), an M4 track (e.g., 240), and a WLPY circuit (e.g., 270).

[0089] In WL decoder 300A, the M2 track (e.g., 220) has a width 302A, and the M4 track (e.g., 240) has a width 304A, where the width is in the second direction (e.g., the Y direction). The distance between the M4 tracks 240 (and / or the M2 tracks 220) (in the second direction, the Y direction) is a first distance 310A. In WL decoder 300B, the M2 track (e.g., 220) has a width 302B, and the M4 track (e.g., 240) has a width 304B, where the width is in the second direction (e.g., the Y direction). The distance between the M4 tracks 240 (and / or the M2 tracks 220) (in the second direction, the Y direction) is a second distance 310B.

[0090] In some examples, a first distance 310A in the WL decoder 300A is smaller than a second distance 310B in the WL decoder 300B. In some examples, a width 304A of an M4 track (e.g., 240) in the WL decoder 300A is larger than a width 304B of an M4 track (e.g., 240) in the WL decoder 300B. In some examples, a width 302A of an M2 track (e.g., 220) in the WL decoder 300A is larger than a width 302B of an M2 track (e.g., 220) in the WL decoder 300B.

[0091] The distance (e.g., 310A, 310B) between the M4 tracks (e.g., 240) (and / or the distance between the M2 tracks (e.g., 220)) can be designed to reduce parasitic capacitance between the M4 tracks (and / or the M2 tracks). In some examples, the distance (e.g., 310A) between the M4 tracks can be increased by reducing the width (e.g., 304A) of the M4 tracks in the WL decoder 300A. This allows the M4 tracks (e.g., 240) to be used to reduce parasitic capacitance without increasing resistance.

[0092] Figure 4 A schematic diagram of an example WL decoder 400 is shown, according to various embodiments. The WL decoder 400 can be substantially similar to or identical to the WL decoder 200. For example, the WL decoder 400 can be an example of the WL decoder 200. For example, the WL decoder 400 includes an M1 track (e.g., 210), an M2 track (e.g., 220N) at the near side (e.g., 201N), an M2 track (e.g., 220F) at the far side (e.g., 201F), an M4 track (e.g., 240), and a WLPY circuit (e.g., 270).

[0093] like Figure 4As shown, the WL decoder 400 includes a plurality of M2 segments 410 at the far side 201F and an M2 track (e.g., 220N) at the near side 201N. Each M2 segment 410 can be a portion of an M2 track (e.g., 220F) at the far side 201F. In the WL decoder 400, the M2 track (e.g., 220F) at the far side 201F is removed, except that each M4 track (e.g., 240) is coupled to an M2 segment 410 at the far side 201F M1 track (e.g., 210F). As shown in the figure, the M2 segments 410 on the first two columns 420 can be omitted, wherein the M4 track 240 is not coupled to the corresponding M1 track 210F at the far side 201F, but is only coupled to the corresponding M2 track 220N at the near side 201N.

[0094] Figure 5 A schematic diagram of an example WL decoder 500 and an example memory controller 505 is shown according to various embodiments. The WL decoder 500 can be substantially similar or identical to the WL decoder 200. For example, the WL decoder 500 can be an example of the WL decoder 200. For example, the WL decoder 500 includes an M1 track (e.g., 210), an M2 track (e.g., 220), an M4 track (e.g., 240), and a WLPY circuit (e.g., 270). Figure 5 For illustrative purposes, only one M2 track (e.g., 220) and one M4 track (e.g., 240) are shown. The memory controller 505 can be substantially similar to or identical to the memory controller 105. For example, the memory controller 505 can provide decoded signals (e.g., 107, 205) to the WL decoder 500.

[0095] The memory controller 505 can split one signal into two signals. For example, the memory controller 505 can split DEC_X0B <7> Divided into DEC_X0N <7> 510N and DEC_X0F <7> 510F, DEC_X0N via M2 track (e.g., 220N) <7> 510N is sent to the near side (eg, 201N), and DEC_X0F is sent via the M4 track (eg, 240) and the M2 track (eg, 220F). <7> 510F is sent to the far side (e.g., 201F). In this case, the memory unit at the far side (e.g., 220F) can be driven via the M4 track, and the delay in providing the decoded signal can be reduced.

[0096] Figure 6An example set of signals provided by a memory controller (e.g., 105) according to various embodiments is shown. The memory controller (e.g., 105) can provide a set of signals (e.g., 107) to control a memory array (e.g., 120) via a plurality of WLDRV4s 605. The WLDRV4s 605 include a plurality of WL drivers (e.g., 64 WL drivers, i.e., WLDRV4<63:0>), each configured to receive a portion of the set of signals (e.g., 107) from a corresponding WLPY circuit (e.g., 270) and assert one of a subset of the WL signals (e.g., four WL signals) at a time to control a corresponding cell of the memory array (e.g., 120).

[0097] More specifically, a memory controller (e.g., 105) may provide a set of signals (e.g., 107) including DEC_X2 610, DEC_X1 615, and DEC_X0 620 to a WLPY circuit (e.g., 270) via metal rails (e.g., M1 rail, M2 rail, etc.). A first set of logic circuits (e.g., NOR gates) in the WLPY circuit (e.g., 270) may receive and process DEC_X2 610 (e.g., DEC_X2<7:0>) and DEC_X1 620 (e.g., DEC_X1<3:0>) to provide output signals. The output signals may be further processed by DEC_X0 to provide a WL signal, thereby identifying a particular word line.

[0098] The sequence of one of the signals (e.g., DEC_X0 620) is changeable so that the memory controller (e.g., 105) can provide separate signals to the near side (e.g., 201N) and the far side (e.g., 201F). Figure 6 As shown, the sequence of DEC_X0 620 can be adjusted so that the memory controller (e.g., 105) provides DEC_X0<7:4> to WLDRV4<63:48> at the far side (e.g., 201F) and DEC_X0<3:0> to WLDRV4<47:0> at the near side (e.g., 201N). This allows the memory controller (e.g., 105) to split the decoded signal (e.g., 170) into two separate signals for the far side (e.g., 201F) and the near side (e.g., 201N), rather than providing the entire signal (e.g., DEC_X0<7:0>) to both the far side (e.g., 201F) and the near side (e.g., 201N).

[0099] For example, from WLDRV4 <63> to WLDRV4 <0> , DEC_X2 610 can be:

[0100] <7> <7> <7> <7> <6> <6> <6> <6> <5> <5> <5> <5> <4> <4> <4> <4> <3> <3> <3> <3> <2> <2> <2> <2> <1> <1> <1> <1> <0> <0> <0> <0> <7> <7> <7> <7> <6> <6> <6> <6> <5> <5> <5> <5> <4> <4> <4> <4> <3> <3> <3> <3> <2> <2> <2> <2> <1> <1> <1> <1> <0> <0> <0> <0> .

[0101] For example, from WLDRV4 <63> to WLDRV4 <0> , DEC_X1 615 can be:

[0102] <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> <3> <2> <1> <0> .

[0103] For example, for each of WLDRV4<63:48>, DEC_X0 620 may be <7> <6> <5> <4> , for each of WLDRV4<31:0>, DEC_X0 620 may be <3> <2> <1> <0> .

[0104] Figure 7 A schematic diagram of an example WL decoder 700 is shown, according to various embodiments. The WL decoder 700 can be substantially similar or identical to the WL decoder 200. For example, the WL decoder 700 can be an example of the WL decoder 200. For example, the WL decoder 700 includes an M1 track (e.g., 210), an M2 track (e.g., 220), an M4 track (e.g., 240), and a WLPY circuit (e.g., 270).

[0105] A memory controller (e.g., 105) (not shown) may provide the signal DEC_X0<0:7> to the WL decoder 700. The memory controller may selectively provide a first portion 710N of the signal (e.g., DEC_X0<3:0>) to the near side (e.g., 201N) via the M2 track (e.g., 220N) at the near side, and selectively provide a second portion 710F of the signal (e.g., DEC_X0<7:4>) to the far side (e.g., 201F) via the M4 track (e.g., 240) at the far side. For example, as shown in the first column of the WL decoder 700, the memory controller may provide DEC_X0<0:7> via the first column of the M4 track (e.g., 240F). <4> Provided to the far side (eg, 201F), while DEC_X0 is sent via the first column of the M2 track (eg, 220N). <0> Provided to the proximal side (eg, 201N).

[0106] Figure 8 A schematic diagram of an example WL decoder 800 is shown according to various embodiments. The WL decoder 800 can be substantially similar or identical to the WL decoder 200. For example, the WL decoder 800 can be an example of the WL decoder 200. For example, the WL decoder 800 includes an M1 track (e.g., 210), an M2 track (e.g., 220), an M4 track (e.g., 240), and a WLPY circuit (e.g., 270).

[0107] The WL decoder 800 may include a dual metal track 810 for each signal. Figure 8 As shown, the WL decoder 800 may include dual tracks of an M2 track (e.g., 220) and an M4 track (e.g., 240) for each of DEC_X0<7:0>. More specifically, as a non-limiting example, a memory controller (e.g., 105) (not shown) may transmit DEC_X0<7:0> to the memory controller 800 via the M2 track of the dual metal tracks 810-1 and 810-2. <0> Provided to the near side (eg, 201N), and can be DEC_X0 through the M4 track in the dual metal track 810-1 and 810-2 <4> Provided to the far side (eg, 201F). The dual metal track 810 can further reduce parasitic resistance.

[0108] In some examples, although not depicted in the figures, the WL decoder (e.g., 200) disclosed in this disclosure may have more than three metallization layers, and the techniques disclosed in this disclosure may be applied in a similar manner. For example, when the WL decoder includes more than three metallization layers, the WL decoder may include an M2 track, an M4 track, and an M6 track to be provided with separate signals, namely, DEC_X0<2:0>, DEC_X0<5:3>, and DEC_X0<7:6>.

[0109] In some examples, although not depicted in the figures, the WL decoder (e.g., 200) disclosed herein can be customized for different applications based on different metal RC values. For example, if the RC value of the M2 rail is significantly greater than the RC value of the M4 rail, the ratio of the RC values of the M4 rail to the M2 rail can be adjusted to reduce / increase utilization.

[0110] Figure 9 A schematic diagram of an example WL decoder 900 is shown, according to various embodiments. The WL decoder 900 can be substantially similar or identical to the WL decoder 200, or a portion or intermediate structure thereof. For example, the WL decoder 900 can be an example of the WL decoder 200. For example, the WL decoder 900 includes an M1 track (e.g., 210) and a WLPY circuit (e.g., 270).

[0111] The WL decoder 900 includes an M2 track 920N at the near side 901N and an M2 track 920F at the far side 901F (collectively referred to as M2 track 920). As shown in the figure, the M2 track 920N is located only at the near side 901N, and the M2 track 920F is located only at the far side 901F. The M2 track 920N is operably coupled to the M1 track 910N at the near side 901N. The M2 track 920N can be provided with DEC_X2<3:0>. The M2 track 920F is operably coupled to the M1 track 910F at the far side 901F. The M2 track 920F can be provided with DEC_X2<7:4>.

[0112] Figure 10 A schematic diagram of an example WL decoder 1000 is shown, according to various embodiments. The WL decoder 1000 can be substantially similar or identical to the WL decoder 200 or the WL decoder 900, or portions or intermediate structures thereof. For example, the WL decoder 1000 can be an example of the WL decoder 200. For example, the WL decoder 1000 includes an M1 track (e.g., 210) and a WLPY circuit (e.g., 270).

[0113] The WL decoder 1000 may be a WL decoder in which the M2 track 920F in the WL decoder 900 is shifted upward so that the M2 track 920F ( Figure 10 1020F) in a first direction (eg, X direction) with the M2 track 920N ( Figure 10 This allows the area of the M2 track to be reduced (eg, by 50% in the second direction (eg, Y direction)).

[0114] Figure 11A flow chart of an example method 1100 for operating a WL decoder according to some embodiments is shown. The method 1100 may be performed using any of the memory devices or a portion or an element of the memory device in the present disclosure. For example, the method 1100 may be performed using Figures 1 to 10 For example, at least one of the operations of method 1100 may be performed on a memory device (e.g., 100). Therefore, the following discussion of method 1100 may be performed on any of the memory devices or their components. Figures 1 to 10 Some of the reference numbers used in the present disclosure are provided as non-limiting examples. Furthermore, the method 1100 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the present disclosure may be Figure 11 Additional operations are provided before, during, and after method 1100, and other operations may only be briefly described in this disclosure.

[0115] Method 1100 may begin with receiving a plurality of decoded signals at operation 1110. In operation 1110, a WL decoder (eg, 114, 200) may receive a plurality of decoded signals from a memory controller (eg, 105).

[0116] In response to receiving the plurality of decoded signals, method 1100 may proceed to operation 1120, where a first subset of the plurality of decoded signals is transmitted to a first plurality of memory cells in a memory array via at least a respective first segment (e.g., 220N) of a plurality of first decoded lines (e.g., M2 rails 220). Method 1100 may proceed to operation 1130, where a second subset of the plurality of decoded signals is transmitted to a second plurality of memory cells in the memory array via at least a respective second segment (e.g., 220F) of a plurality of first decoded lines (e.g., M2 rails 220). The corresponding first segment (e.g., 220N) and the corresponding second segment (e.g., 220F) of each first decoded line (e.g., M2 rails 220) are physically separated from each other and physically arranged side by side along a lateral direction (e.g., X direction). Although operation 1130 is depicted and described after operation 1120, operation 1130 may be performed concurrently with operation 1120.

[0117] In some examples, method 1100 may include transmitting the second subset of decoded signals to the second plurality of memory cells via a plurality of second decode lines (e.g., M4 rails 240). The plurality of second decode lines (e.g., M4 rails 240) also extend along a lateral direction (e.g., an X direction) and each extend over a first segment (e.g., 220N) and a second segment (e.g., 220F) of a corresponding one of the first decode lines (e.g., M2 rails 220). In some examples, the plurality of first decode lines (e.g., M2 rails 220) are disposed in a first metallization layer, and the plurality of second decode lines (e.g., M4 rails 240) are disposed in a second metallization layer, the second metallization layer being disposed vertically above the first metallization layer.

[0118] In some examples, method 1100 may include providing a plurality of signals having separate signals to a first decode line (e.g., M2 track 220) and / or a second decode line (e.g., M4 track 240). For example, method 1100 may also include separating the signal into a first portion of the signal (e.g., 510N) and a second portion of the signal (e.g., 510F), and providing each signal to a first segment (e.g., 220N) and a second segment (e.g., 220F) of the first decode line (e.g., M2 track 220), respectively. The second portion of the signal (e.g., 510F) may be provided to the second segment (e.g., 220F) of the first decode line (e.g., M2 track 220) via the second decode line (e.g., M4 track 240).

[0119] In some examples, method 1100 may include providing a plurality of signals to a first decode line (eg, M2 rail 220) and / or a second decode line (eg, M4 rail 240), the signals being reordered according to the configuration of the decode lines. Figure 6 As shown, method 1100 may include: changing a signal (e.g., Figure 6 The method 1100 may also include changing the sequence of the other signals (e.g., 605, 610, 615, etc.) to separate them into a first subset of signals (e.g., DEC_X0<3:0> 620N) and a second subset of signals (e.g., DEC_X0<7:4> 620F), providing the first subset of signals to the first segment (e.g., 220N), and providing the second subset of signals to the second segment (e.g., 220F) and the second decode line (e.g., M4 track 240). Similarly, the method 1100 may include changing the sequence of other signals (e.g., 605, 610, 615, etc.).

[0120] In some examples, method 1100 may include providing multiple signals with separate signals to a first decode line (e.g., M2 track 220) and / or a second decode line (e.g., M4 track 240). For example, method 1100 may include providing a first signal (e.g., 710N) to a first segment (e.g., 220N) of a first decode line (e.g., M2 track 220) while providing a second signal (e.g., 710F) via a corresponding second decode line (e.g., M4 track 240). In some examples, method 1100 may include using more than one decode line for each signal. For example, method 1100 may include doubling each first decode line (e.g., M2 track 220) and each second decode line (e.g., M4 track 240) for each signal.

[0121] Figure 12 A flow chart of an example method 1200 for manufacturing a memory device (e.g., 100) according to some embodiments is shown. The method 1200 can be performed to form any or a portion of the memory devices described in this disclosure. For example, the method 1200 can be performed to form Figures 1 to 10 For example, at least one of the operations of method 1200 may be performed to form a memory device (e.g., 100). Therefore, the following discussion of method 1200 may be Figures 1 to 10 The reference numbers used in the present disclosure are provided as non-limiting examples. Furthermore, the method 1200 is merely an example and is not intended to limit the present disclosure. Therefore, it should be understood that the present disclosure may be Figure 12 Additional operations may be provided before, during, and after method 1200, and other operations may be only briefly described in this disclosure. Method 1200 may be performed concurrently and / or may be Figure 12 in any order other than that depicted.

[0122] Method 1200 may begin with operation 1210 of forming a memory array (eg, 120 ) in a first region of a substrate.

[0123] The substrate may be a wafer, such as a silicon wafer or a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon substrate or a glass substrate. Other substrates may also be used, such as a multilayer substrate or a gradient substrate. In some embodiments, the semiconductor material of the substrate may include silicon, germanium, a compound semiconductor (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), (gold semiconductor, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP) or a combination thereof.

[0124] The memory array includes a plurality of memory cells. In some examples, each memory cell may be implemented as a six-transistor (6T) static random access memory (SRAM) cell consisting of six transistors (e.g., N1, N2, N3, N4, P1, and P2). However, it should be understood that the first to fourth memory cells may be implemented as other types of SRAM configurations other than 6T, such as eight transistors (8T) or ten transistors (10T). In some examples, the memory cells may alternatively or additionally be implemented as other types of memory cells, such as dynamic random access memory (DRAM) cells, resistive random access memory (RRAM) cells, phase-change random access memory (PCRAM) cells, or magnetoresistive random access memory (MRAM) cells. In various embodiments, memory cells may be formed along a major (eg, front-side) surface of a substrate. The fabrication of these memory cells (and corresponding memory arrays) is sometimes referred to as front-end-of-line (FEOL) processing.

[0125] Method 1200 may continue with operation 1220 by forming a circuit portion (e.g., 270) of a WL decoder (e.g., 114) in the second region of the substrate. In some examples, at operation 1220, method 1200 includes forming a plurality of logic elements and / or a plurality of logic circuits (e.g., NOR gates, AND gates, etc.).

[0126] Method 1200 may continue to operation 1230 by forming a plurality of metallization layers (e.g., 210, 220, 240, etc.) above the substrate, wherein a plurality of decode lines are formed in a first one of the metallization layers, each decode line comprising a first segment and a second segment separated from each other along a first lateral direction (e.g., an X direction), wherein the first segment and the second segment of each decode line are operably coupled to a first portion and a second portion of the memory array.

[0127] In some embodiments, the first segment may correspond to word lines WL and WLB operatively coupled to a first portion of a memory array, and the segment may correspond to word lines WL and WLB operatively coupled to a second portion of a memory array. The first segment and the second segment may each extend laterally from a corresponding controller (e.g., 105) and toward a second edge of the controller opposite a first edge immediately adjacent to the first segment along the lateral direction. In some examples, the first segment and the second segment may comprise one or more metal materials, such as tungsten (W), copper (Cu), gold (Au), cobalt (Co), ruthenium (Ru), or combinations thereof, and may be fabricated using one or more damascene processes.

[0128] In some examples, at operation 1230, method 1200 may include forming a plurality of second decode lines in a second one of the metallization layers (e.g., 240), each second decode line operatively coupled to at least one of the first segment or the second segment. For example, method 1200 may include forming a via structure operatively coupling the second decode lines to the first segment and / or the second segment.

[0129] In one aspect of this disclosure, a memory device is disclosed. The memory device includes a plurality of first decode lines. The plurality of first decode lines are disposed in a first metallization layer and extend in a first direction. Each of the plurality of first decode lines includes at least a first segment and a second segment, each coupled to a plurality of first memory cells and a plurality of second memory cells, respectively. The first segment and the second segment of each of the plurality of first decode lines are arranged side by side along the first direction.

[0130] In some embodiments of the memory device of this aspect, the memory device further includes a plurality of second decode lines. The plurality of second decode lines are disposed in the second metallization layer and extend in a second direction perpendicular to the first direction. A first segment of each of the plurality of first decode lines is coupled to a first subset of the plurality of first memory cells via a first subset of the plurality of second decode lines, and a corresponding second segment of the first decode line is coupled to the first subset of the plurality of second memory cells via a second subset of the plurality of second decode lines.

[0131] In some embodiments of the memory device of this aspect, the second metallization layer is disposed vertically below the first metallization layer.

[0132] In some embodiments of the memory device of this aspect, the first subset of the plurality of second decode lines and the second subset of the plurality of second decode lines are separated from each other in the first direction by one or more other subsets of the plurality of second decode lines.

[0133] In some embodiments of the memory device of this aspect, the memory device further includes a memory controller configured to provide a plurality of decoding signals to the plurality of first memory units and the plurality of second memory units via at least a plurality of first decoding lines.

[0134] In some embodiments of the memory device of this aspect, the memory controller is physically adjacent to the plurality of first segments, and the plurality of second segments are arranged opposite to the plurality of first segments with the memory controller as the center.

[0135] In some embodiments of the memory device of this aspect, the memory device further includes a plurality of third decode lines. The plurality of third decode lines are disposed in the third metallization layer and extend in the first direction. Each of the plurality of third decode lines extends across the first segment and the second segment of a corresponding one of the plurality of first decode lines.

[0136] In some embodiments of the memory device of this aspect, the third metallization layer is vertically disposed above the first metallization layer.

[0137] In some embodiments of the memory device of this aspect, each of the plurality of third decode lines is coupled only to the second segment of a corresponding one of the plurality of first decode lines.

[0138] In some embodiments of the memory device of this aspect, each of the plurality of first decoding lines has a first width extending in a second direction perpendicular to the first direction, and each of the plurality of third decoding lines has a second width in the second direction that is smaller than the first width.

[0139] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a memory array, a memory controller, and a plurality of first decoding lines. The memory array includes a plurality of first memory cells and a plurality of second memory cells. The memory controller is physically adjacent to the plurality of first memory cells, and the plurality of second memory cells are physically opposite to the plurality of first memory cells along a first direction with the memory controller as the center. The memory controller is used to provide a plurality of decoding signals to the memory array. The plurality of first decoding lines are disposed in a first metallization layer and extend in a first direction. Each of the plurality of first decoding lines includes at least one first segment and one second segment, each coupled to the plurality of first memory cells and the plurality of second memory cells.

[0140] In some embodiments of the memory device of this other aspect, the first segment and the second segment of each of the plurality of first decoding lines are arranged side by side along the first direction.

[0141] In some embodiments of the memory device of this other aspect, a first subset of the plurality of decoded signals is used to activate a plurality of first memory units, and a second subset of the plurality of decoded signals is used to activate a plurality of second memory units.

[0142] In some embodiments of this other aspect of the memory device, the memory device further includes a plurality of second decode lines. The second decode lines are disposed in the second metallization layer and extend in a second direction perpendicular to the first direction. A first segment of each of the plurality of first decode lines is coupled to a first subset of the plurality of first memory cells via a first subset of the plurality of second decode lines, and a corresponding second segment of the first decode line is coupled to a second subset of the plurality of second memory cells via a second subset of the plurality of second decode lines.

[0143] In some embodiments of the memory device according to another aspect, the memory device further includes a plurality of third decode lines. The plurality of third decode lines are disposed in the third metallization layer and extend in the first direction. Each of the plurality of third decode lines extends across the first segment and the second segment of a corresponding one of the plurality of first decode lines.

[0144] In some embodiments of the memory device according to another aspect, the second metallization layer is vertically disposed below the first metallization layer, and the third metallization layer is vertically disposed above the first metallization layer.

[0145] In some embodiments of the memory device of this other aspect, each of the plurality of third decode lines is coupled only to the second segment of a corresponding one of the plurality of first decode lines.

[0146] In yet another aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes receiving a plurality of decoded signals; transmitting a first subset of the plurality of decoded signals to a plurality of first memory cells in a memory array via at least respective first segments of a plurality of first decoded lines; and transmitting a second subset of the plurality of decoded signals to a plurality of second memory cells in the memory array via at least respective second segments of the plurality of first decoded lines. The corresponding first segment and the corresponding second segment in each first decoded line are physically separated from each other and physically arranged side by side along a lateral direction.

[0147] In yet another aspect of the present disclosure, a method for forming a memory device is disclosed. The method includes forming a memory array in a first region of a substrate; forming a decoder circuit portion in a second region of the substrate; and forming a plurality of metallization layers above the substrate. A plurality of decoder lines are formed in a first of the plurality of metallization layers, each of the plurality of decoder lines including a first segment and a second segment separated from each other along a first lateral direction. The first segment and the second segment of each of the plurality of decoder lines are coupled to a first portion and a second portion of the memory array, respectively.

[0148] In some embodiments of the formation method of the yet another aspect, the formation method further includes: forming a plurality of second decoding lines in a second of the plurality of metallization layers, each of the plurality of second decoding lines being coupled to at least one of the first segment or the second segment.

[0149] In some embodiments of the formation method of yet another aspect, each of the plurality of decoding lines has a first width extending in a second direction perpendicular to the first direction, and each of the plurality of second decoding lines has a second width in the second direction that is smaller than the first width.

[0150] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes a substrate, a memory array, a decoder, and a plurality of decoder lines. The memory array is formed in a first region of the substrate and includes a first portion and a second portion. Circuitry for the decoder is formed in a second region of the substrate. A plurality of decoder lines are formed in a first of a plurality of metallization layers on the substrate, each of the plurality of decoder lines including a first segment and a second segment separated from each other along a first lateral direction. The first segment and the second segment of each of the plurality of decoder lines are respectively coupled to the first portion and the second portion of the memory array.

[0151] As used herein, the terms "about" and "approximately" generally indicate a value of a given amount that may vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term "approximately" may indicate a value of a given amount that varies within, for example, 10% to 30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0152] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use this disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that: Include: A plurality of first decoding lines are disposed in a first metallization layer and extend in a first direction, Each of the plurality of first decoding lines comprises at least a first segment and a second segment coupled to a plurality of first memory units and a plurality of second memory units, respectively; and The first segment and the second segment of each of the plurality of first decoding lines are arranged side by side along the first direction.

2. The memory device according to claim 1, wherein Also includes: A plurality of second decoding lines are disposed in a second metallization layer and extend in a second direction perpendicular to the first direction, wherein the first segment of each of the plurality of first decoding lines is coupled to a first subset of the plurality of first memory cells via a first subset of the plurality of second decoding lines, and the corresponding second segment of the first decoding line is coupled to a first subset of the plurality of second memory cells via a second subset of the plurality of second decoding lines.

3. The memory device according to claim 2, wherein: The first subset of the plurality of second decoding lines and the second subset of the plurality of second decoding lines are separated from each other in the first direction by one or more other subsets of the plurality of second decoding lines.

4. The memory device according to claim 1, wherein: Also includes: A memory controller is configured to provide a plurality of decoding signals to the plurality of first memory units and the plurality of second memory units via at least the plurality of first decoding lines.

5. The memory device according to claim 4, wherein: The memory controller is physically adjacent to the plurality of first segments, and the plurality of second segments are arranged to be opposite to the plurality of first segments with the memory controller as the center.

6. The memory device according to claim 1, wherein: Also includes: A plurality of third decoding lines are disposed in a third metallization layer and extend in the first direction, Each of the plurality of third decoding lines extends across the first segment and the second segment of a corresponding one of the plurality of first decoding lines.

7. The memory device according to claim 6, wherein: Each of the plurality of third decoding lines is coupled only to the second segment of the corresponding one of the plurality of first decoding lines.

8. The memory device according to claim 6, wherein: Each of the plurality of first decoding lines has a first width extending in a second direction perpendicular to the first direction, and each of the plurality of third decoding lines has a second width in the second direction, and the second width is smaller than the first width.

9. A memory device, characterized in that: Include: a memory array comprising a plurality of first memory units and a plurality of second memory units; a memory controller physically adjacent to the plurality of first memory units, the plurality of second memory units physically opposite to the plurality of first memory units along a first direction with the memory controller as the center, wherein the memory controller is configured to provide a plurality of decoding signals to the memory array; as well as A plurality of first decoding lines are disposed in a first metallization layer and extend in the first direction, Each of the plurality of first decoding lines includes at least a first segment and a second segment respectively coupled to the plurality of first memory units and the plurality of second memory units.

10. A memory device, characterized in that: Include: a substrate; A memory array is formed in a first area of the substrate and includes a first portion and a second portion; a decoder, wherein a circuit portion of the decoder is formed in a second area of the substrate; as well as A plurality of decoding lines are formed in a first of a plurality of metallization layers on the substrate, each of the plurality of decoding lines comprising a first segment and a second segment separated from each other along a first lateral direction, The first segment and the second segment of each of the plurality of decoding lines are respectively coupled to the first portion and the second portion of the memory array.

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