Maximum on-time control circuit capable of adaptively changing along with frequency

Abstract

The utility model belongs to the technical field of electronic circuits, and particularly discloses a maximum on-time control circuit capable of adaptively changing along with frequency, which comprises an IBIAS reference current module, a capacitor and a logic control module, the output end of the IBIAS reference current module is respectively connected with one end of the capacitor and the input end of the logic control module, the other end of the capacitor is grounded, and the logic control module is connected with the logic control module. The logic control module comprises a D trigger, the output end of the D trigger is connected with the input end of a power tube driving control circuit in the Buck circuit, and the IBIAS reference current module comprises a turn-off signal control end used for inputting a turn-off signal and a charging and discharging control end used for controlling charging and discharging of a capacitor. According to the utility model, the maximum conduction time of the power tube on the Buck circuit can be controlled, and the Buck circuit can work normally when the input voltage of the Buck circuit is slightly higher than the output voltage or the turn-off speed of the input voltage is very slow. The Buck circuit control circuit is suitable for control of a Buck circuit.

Description

Technical Field

[0001] The utility model belongs to the technical field of electronic circuits, in particular to a maximum on-time control circuit that changes adaptively with frequency. Background Art

[0002] In the field of power electronics, buck-type switching converters are widely used in power conversion processes to step down the input voltage to the required output voltage. The voltage driving the upper power transistor in a buck-type switching converter must be higher than the supply voltage to turn it on. This voltage is typically achieved through a bootstrap circuit. The bootstrap circuit charges the bootstrap capacitor when the lower power transistor is on, providing power to the upper power transistor when it is on. Therefore, the bootstrap capacitor needs sufficient time to fully charge during each switching cycle to properly drive the upper power transistor. When the input voltage is slightly higher than the output voltage or the input voltage turns off very slowly, the output voltage duty cycle is very high. At high clock frequencies, the lower power transistor's on-time becomes very short, and the bootstrap capacitor will not be fully charged, causing the buck circuit to malfunction and further impacting subsequent circuits.

[0003] In the prior art, three solutions are commonly used to address the issue of abnormal output states caused by insufficient bootstrap capacitor charging time. The first solution is to change the driver power supply method. For example, the upper power transistor can be replaced with a PMOS transistor. However, because PMOS current driving capability is lower than that of NMOS, it requires several times the area to achieve the same current driving capability. Alternatively, a charge pump circuit can be used to power the upper power transistor. The charge pump can always provide a stable high voltage higher than the power supply voltage to the driver circuit, allowing the driver circuit to operate independently of the switch state. However, the charge pump circuit increases circuit complexity, and a charge pump voltage higher than the power supply voltage limits the maximum power supply voltage for the same process. The second solution is to monitor the bootstrap capacitor voltage. When the capacitor voltage falls below a certain threshold, the switch node voltage is forced to drop. In the normal state with a high duty cycle, the voltage on the bootstrap capacitor drops to a low level, and the additional lower MOS transistor is turned on to supplement it, resulting in a lower average voltage, which increases the on-resistance of the MOS transistor and increases power consumption. The third solution is to design a fixed maximum on-time. When the on-time exceeds the preset time, the upper power transistor is automatically shut down and the lower power transistor is turned on. Because the device is significantly affected by process and temperature, the maximum on-time fluctuates greatly. In addition, when the internal oscillator frequency increases, the maximum on-time may exceed one cycle and no longer have a limiting function. Utility Model Content

[0004] The purpose of this utility model is to provide a maximum on-time control circuit that adaptively changes with frequency to limit the maximum on-time of the power tube in the Buck circuit, ensuring that the Buck circuit can operate normally even when the input voltage is slightly higher than the output voltage or the input voltage is turned off very slowly.

[0005] In order to achieve the above-mentioned purpose, the technical methods adopted by the present invention are as follows:

[0006] A maximum on-time control circuit that changes adaptively with frequency is used in a Buck circuit. In the Buck circuit, an upper power tube and a lower power tube are connected in series, and their connection point generates an output voltage through a power inductor. Control ends of the upper and lower power tubes are controlled to turn on and off via a power tube drive control circuit. The maximum on-time control circuit includes an IBIAS reference current module, a capacitor, and a logic control module. The output end of the IBIAS reference current module is respectively connected to one end of the capacitor and the input end of the logic control circuit, and the other end of the capacitor is grounded. The logic control module includes a D-type flip-flop, the output end of the D-type flip-flop is connected to the input end of the power tube drive control circuit in the Buck circuit. The IBIAS reference current module includes a shutdown signal control end for inputting a shutdown signal and a charge / discharge control end for controlling the charging and discharging of the capacitor.

[0007] As a limitation: the logic control module also includes a first inverter, a second inverter and a NAND gate, the output end of the IBIAS reference current module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the NAND gate, the second input end of the NAND gate inputs the upper power tube gate signal, the output end of the NAND gate is connected to the D input end of the D flip-flop, the clock signal input end of the D flip-flop inputs the clock signal, the reset signal input end of the D flip-flop is connected to the output end of the second inverter, and the input end of the second inverter is connected to the charge and discharge control end of the BIAS reference current module.

[0008] As a further limitation: the maximum on-time control circuit also includes a PMOS tube, the source of the PMOS tube is connected to the power supply, the drain of the PMOS tube is connected to the input end of the first inverter, and the gate of the PMOS tube is connected to the output end of the first inverter.

[0009] As a further limitation: a resistor is connected between the output terminal of the IBIAS reference current module and the capacitor.

[0010] Due to the adoption of the above solution, the present invention has the following beneficial effects compared with the prior art:

[0011] The utility model provides a maximum on-time control circuit that adaptively changes with frequency. By setting an IBIAS reference current module, a capacitor, and a logic control module, the IBIAS reference current module charges the capacitor and provides a flip voltage for the logic control module. The maximum on-time of the power tube on the Buck circuit is then controlled by the potential output by the logic control module. This ensures that the Buck circuit can operate normally even when the input voltage of the Buck circuit is slightly higher than the output voltage or the input voltage is turned off very slowly. In addition, the utility model has a simple structure, reduces the occupied area, and reduces the cost. The charging capacitor is reduced, and the current of the IBIAS reference current module can be limited to a very low level, reducing power consumption. The maximum on-time of the power tube adaptively changes with the clock frequency, and can operate normally within the operating frequency range of the Buck circuit. The maximum on-time is not affected by the charging current and the size of the charging capacitor, and is less affected by the process and temperature.

[0012] The utility model is suitable for controlling Buck circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0014] Figure 1 This is a circuit diagram of a maximum on-time control circuit that adaptively changes with frequency according to an embodiment of the utility model;

[0015] Figure 2 This is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK, and the output terminal VOUT signal of the maximum on-time control circuit of the present invention when the clock frequency is 1MHz and the ratio of the output voltage to the input voltage of the Buck circuit is less than 95%;

[0016] Figure 3 This is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK, and the output terminal VOUT signal of the maximum on-time control circuit of the present invention when the clock frequency is 1MHz and the ratio of the output voltage to the input voltage of the Buck circuit exceeds 95%;

[0017] Figure 4 This is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK, and the output terminal VOUT signal of the maximum on-time control circuit of the present invention when the clock frequency is 2MHz and the ratio of the output voltage to the input voltage of the Buck circuit is less than 95%;

[0018] Figure 5This is a waveform relationship diagram of the charge and discharge control terminal CTRL, the clock signal input terminal CLK, and the output terminal VOUT signal of the maximum on-time control circuit of the present invention when the clock frequency is 500kHz and the ratio of the output voltage to the input voltage of the Buck circuit exceeds 95%;

[0019] In the figure: 1. Logic control module. DETAILED DESCRIPTION

[0020] The present invention will be further described below with reference to the following embodiments. However, those skilled in the art should understand that the present invention is not limited to the following embodiments, and any improvements and equivalent changes made based on the specific embodiments of the present invention are within the scope of protection of the claims of the present invention.

[0021] Embodiment 1: A maximum on-time control circuit adaptively changing with frequency

[0022] A maximum on-time control circuit that changes adaptively with frequency is used in a Buck circuit. In the Buck circuit, an upper power tube and a lower power tube are connected in series, and their connection point is filtered by an inductor and a capacitor to generate a stable output voltage. The control terminals of the upper power tube and the lower power tube are controlled to turn on and off by a power tube drive control circuit. The circuit diagram of the maximum on-time control circuit is shown in FIG. Figure 1 As shown, it includes an IBIAS reference current module, a resistor R, a capacitor C, a PMOS tube and a logic control module 1. The IBIAS reference current module includes a shutdown signal control terminal SHDN for inputting a shutdown signal and a charge and discharge control terminal CTRL for controlling the charging and discharging of the capacitor. The logic control module 1 includes a first inverter INV1, a second inverter INV2, a NAND gate NAND and a D trigger. The output end of the IBIAS reference current module is respectively connected to one end of the resistor R, the drain of the PMOS tube and the input end of the first inverter INV1, the other end of the resistor R is connected to one end of the capacitor C, the other end of the capacitor C is grounded, the source of the PMOS tube is connected to the power supply, and the PMOS tube is connected to the power supply. The gate is connected to the output end of the first inverter INV1, the output end of the first inverter INV1 is connected to the first input end of the NAND gate NAND, the second input end of the NAND gate NAND inputs the power tube gate signal VGH, the output end of the NAND gate NAND is connected to the D input end of the D flip-flop, the clock signal input end CLK of the D flip-flop inputs the clock signal, the reset signal input end Reset of the D flip-flop is connected to the output end of the second inverter INV2, the output end VOUT of the D flip-flop is connected to the input end of the power tube drive control circuit in the Buck circuit, and the input end of the second inverter INV2 is connected to the charge and discharge control end CTRL of the BIAS reference current module.

[0023] The IBIAS current reference module provides charging current for capacitor C, while resistor R reduces transient current. IBIAS is controlled by two control signals. The shutdown signal control terminal SHDN inputs the shutdown signal of the Buck circuit. When the Buck circuit is shut down, the IBIAS current reference module also shuts down—that is, when the shutdown signal control terminal SHDN inputs a high level, the IBIAS current reference module shuts down, saving power. The charge / discharge control terminal CTRL of the IBIAS current reference module charges capacitor C when a high level is input, and discharges capacitor C when a low level is input. A PMOS transistor is connected to the first inverter INV1, forming positive feedback that increases the switching speed of the voltage at node B. With the falling edge of the clock signal, the charge / discharge control terminal CTRL of the IBIAS current reference module goes high, turning on the upper power transistor of the Buck circuit and simultaneously charging capacitor C. When the voltage at node A reaches the switching voltage of the first inverter INV1, the voltage at node B goes low, and the voltage at node C goes high. If the input voltage of the Buck circuit is slightly higher than the output voltage or the input voltage shuts off very slowly, the output voltage duty cycle is high, the upper power transistor is on for a long time, and the charge / discharge control terminal CTRL of the BIAS reference current module remains high for a long time, causing the BIAS reference current module to continuously charge capacitor C. When the next rising clock edge arrives, node C remains high, the output terminal VOUT of the D flip-flop outputs a high level, and then controls the upper power transistor of the Buck circuit to turn off. The maximum on-time control circuit of this embodiment sets the maximum on-time of the upper power transistor of the Buck circuit, which is equal to the width of the clock pulse. When the Buck circuit is in normal operation, the upper power transistor is turned off before the next rising clock edge arrives. Therefore, the charge / discharge control terminal CTRL of the IBIAS reference current module will go low early, node A will begin discharging, and node E will go high, setting the output of the D flip-flop to 0 and outputting a low level at the output terminal VOUT, without turning off the upper power transistor of the Buck circuit.

[0024] The maximum on-time control circuit of this embodiment is designed using 0.18μm BCD technology. The circuit is integrated into the Buck chip. The pulse width of the clock signal square wave of the chip is preset to 50ns, so the maximum on-time is 1 time period minus 50ns. When the clock frequency is 1MHz, Figure 2 As shown, when the ratio of the output voltage to the input voltage of the Buck circuit is lower than 95%, the on-time is lower than 950ns, and the maximum on-time control circuit of this embodiment will not work; Figure 3As shown in FIG, when the ratio of the output voltage to the input voltage exceeds 95%, the conduction time exceeds 950ns. The maximum conduction time control circuit of this embodiment will take effect when the conduction time is 950ns, turning off the upper power tube. When the clock frequency is 2MHz, as shown in FIG. Figure 4 As shown in FIG, when the ratio of the output voltage to the input voltage of the Buck circuit exceeds 90%, the on-time exceeds 450ns. The maximum on-time control circuit of this embodiment will take effect when the on-time is 450ns, turning off the upper power tube. When the clock frequency is 500kHz, as shown in FIG. Figure 5 As shown, when the ratio of the Buck circuit's output voltage to its input voltage exceeds 97.5%, the on-time exceeds 1950ns. The maximum on-time control circuit of this embodiment activates at 1950ns, shutting off the upper power transistor. This maximum on-time control circuit of this embodiment adaptively controls the maximum on-time of the upper power transistor in the Buck circuit as the clock frequency changes. This limits the maximum on-time of the upper power transistor, ensuring normal operation of the Buck circuit even when the input voltage is slightly higher than the output voltage.

Claims

1. A maximum on-time control circuit that adaptively changes with frequency, used in a Buck circuit, wherein an upper power tube and a lower power tube are connected in series and their connection point is filtered by an inductor and a capacitor to generate a stable output voltage. The control terminals of the upper power tube and the lower power tube are controlled to turn on and off by a power tube drive control circuit, characterized in that: The maximum on-time control circuit includes an IBIAS reference current module, a capacitor, and a logic control module. The output end of the IBIAS reference current module is respectively connected to one end of the capacitor and the input end of the logic control circuit, and the other end of the capacitor is grounded. The logic control module includes a D trigger, the output end of the D trigger is connected to the input end of the power tube drive control circuit in the Buck circuit. The IBIAS reference current module includes a shutdown signal control end for inputting a shutdown signal and a charge and discharge control end for controlling the charging and discharging of the capacitor.

2. The maximum on-time control circuit that adaptively changes with frequency according to claim 1, characterized in that: The logic control module also includes a first inverter, a second inverter and a NAND gate. The output end of the IBIAS reference current module is connected to the input end of the first inverter, the output end of the first inverter is connected to the first input end of the NAND gate, the second input end of the NAND gate inputs the upper power tube gate signal, the output end of the NAND gate is connected to the D input end of the D flip-flop, the clock signal input end of the D flip-flop inputs the clock signal, the reset signal input end of the D flip-flop is connected to the output end of the second inverter, and the input end of the second inverter is connected to the charge and discharge control end of the BIAS reference current module.

3. The maximum on-time control circuit that adaptively changes with frequency according to claim 2, characterized in that: The maximum on-time control circuit further includes a PMOS tube, a source of the PMOS tube connected to the power supply, a drain of the PMOS tube connected to the input end of the first inverter, and a gate of the PMOS tube connected to the output end of the first inverter.

4. A maximum on-time control circuit that adaptively changes with frequency according to any one of claims 1 to 3, characterized in that: A resistor is connected between the output of the IBIAS reference current module and the capacitor.

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