Sic VDMOSFET structure with low manufacturing cost
By introducing multiple conductive channels and heat dissipation particles into Sic VDMOSFET devices, the stability and leakage loss problems of the device under high electric fields are solved, high temperature self-protection and current control are achieved, and the device usage effect is improved.
Patent Information
- Application Number
- CN202421822150.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-30
- Publication Date
- 2025-08-12
- Estimated Expiration
- 2034-07-30
AI Technical Summary
Existing Sic VDMOSFET devices are prone to breakdown under high electric fields, resulting in poor stability and reliability, and serious leakage losses caused by the movement of charged particles.
The multi-conductive channel structure and conductive polycrystalline silicon carbide layer are adopted, combined with heat dissipation particles and asymmetric gate dielectric layer design, reducing the electric field strength and adjusting the resistance value to avoid breakdown and leakage losses.
It improves the working stability and reliability of the device, avoids gate oxygen breakdown and bipolar degradation effects, reduces leakage loss, and realizes self-protection function.
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Figure CN223219401U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor power devices, in particular to a SicVDMOSFET structure with low manufacturing cost. Background Art
[0002] SiC VDMOSFET is an emerging power device with great potential in power semiconductor devices. It uses a new semiconductor material, silicon carbide. With its various electrical properties, it has extremely promising prospects in the application fields of high-voltage, high-temperature and high-power devices. Specifically, it has high withstand voltage, wide bandgap, high temperature resistance and high electron mobility, etc. Therefore, as one of the most cutting-edge power devices, SiC VDMOSFET power devices urgently need to be studied and also have great scientific research significance. With the rapid development of science and technology, the application scope of silicon carbide materials is becoming more and more extensive.
[0003] Currently, when the SiC VDMOSFET structure is in use, when an extremely high electric field appears, this electric field will exceed the critical breakdown electric field of silicon dioxide, causing gate oxide breakdown before breakdown, affecting the operating stability and reliability of the device. At the same time, existing SiC VDMOSFET devices are prone to bipolar degradation effects, resulting in poor operating stability of the SiC VDMOSFET devices. In addition, under the action of an external electric field, charged particles in the insulating material will move, causing a weak current. When the leakage current flows through the dielectric, the dielectric heats up and energy loss occurs, thereby causing leakage loss, which affects the performance of the SiC VDMOSFET device.
[0004] Therefore, a SiC VDMOSFET structure with lower manufacturing cost is proposed to solve the above-mentioned problems. Summary of the Invention
[0005] The purpose of this utility model is to provide a SiC VDMOSFET structure with low manufacturing cost to solve the problems raised in the above background technology:
[0006] In order to achieve the above purpose, the present invention provides the following technical solutions:
[0007] A SiC VDMOSFET structure with low manufacturing cost includes a drain, a conductive substrate layer disposed above the drain, conductive epitaxial layers disposed on both sides of the upper end of the conductive substrate layer, a conductive pillar region disposed in the middle of the upper end of the conductive substrate layer, a gate dielectric layer and a gate electrode disposed above the conductive pillar region, the gate dielectric layer being located within the gate electrode, a conductive polycrystalline silicon carbide layer disposed within the gate dielectric layer, a buffer structure disposed above each of the two conductive epitaxial layers, a conductive source region and a conductive well region disposed above each of the two buffer structures, a source electrode disposed above the conductive source region, the gate dielectric layer, and the conductive well region, one end of the source electrode contacting the buffer structure, two first and second light-blocking layers disposed above the source electrode, the two first light-blocking layers being interlaced with the two second light-blocking layers, and a conductive extension layer and a conductive shielding region disposed between the conductive epitaxial layer and the buffer structure.
[0008] Preferably, the doping concentration of the conductive substrate layer is 5×1018 cm -3 ;
[0009] A conductive polycrystalline silicon carbide layer is provided in the gate dielectric layer, and the doping concentration of the conductive polycrystalline silicon carbide layer is 1.5×1027 cm -3 , an isolation dielectric layer is provided in the gate dielectric layer;
[0010] The top of the isolation dielectric layer contacts the source electrode, the thickness of the isolation dielectric layer is no more than 2.5 μm, and the surface doping concentration of the isolation dielectric layer is 1.5×1017 cm -3 ,
[0011] By adopting the above technical solution, the gate trench and the dielectric layer trench form multiple conductive channels, which penetrate the conductive well area. The depth of the dielectric layer trench in the conductive well area is significantly greater than the depth of the gate trench. This can effectively reduce the electric field strength that the gate dielectric of the SicVDMOSFET device is subjected to when the power is off.
[0012] Preferably, the conductive shielding area is located below the conductive extension layer, and the depth of the conductive shielding area is not less than 1.5 μm, and the doping concentration is 1e17 cm -3 ~5e19cm -3 ,
[0013] By adopting the above technical solution, gate oxide breakdown can be avoided before the device is broken down, thereby improving the working stability and reliability of the device.
[0014] Preferably, the conductive extension layer is provided with a first P+ contact region, a P- contact region and a second P+ contact region, and the conductive extension layer is provided with a groove corresponding to the conductive shielding region.
[0015] By adopting the above technical solution, the working stability and reliability of the device are improved.
[0016] Preferably, a gate trench and a dielectric layer trench are provided in the conductive shielding region, and the doping ions of the gate trench and the dielectric layer trench are set to be one or more of phosphorus ions, copper ions, silicon ions and carbon ions;
[0017] A heterojunction contact is formed on a side of the buffer structure away from the source electrode, wherein the heterojunction contact is formed by depositing a conductive polycrystalline silicon carbide layer.
[0018] By adopting the above technical solution, the gate dielectric layer divides the Sic VDMOSFET device into an asymmetric structure, so that the Sic VDMOSFET device avoids the occurrence of bipolar degradation effect.
[0019] Preferably, the surface doping concentration of the conductive well region is 2.5×1027 cm -3 ;
[0020] The doping concentration of the conductive well region near the source electrode boundary is 1×1036cm -3 ,
[0021] By adopting the above technical solution, the stability of the use of the SiC VDMOSFET device is increased.
[0022] Preferably, the depth of the conductive column region is not less than 1.5 μm, and the doping concentration is 5e16 cm -3 ~1e18cm -3 ;
[0023] The upper end surface of the conductive column region is flush with the upper end surfaces of the two conductive epitaxial layers.
[0024] By adopting the above technical solution, when the Sic VDMOSFET performs power transmission, the size of the resistance can be adjusted by high temperature according to the heat dissipation particles, thereby ensuring that when the Sic VDMOSFET structure transmits high power, the ultra-high electric field will not exceed the critical value of silicon dioxide.
[0025] Preferably, two heat dissipation particles are provided in the buffer structure, the two heat dissipation particles are located at different positions and have different sizes, and the distance between two adjacent heat dissipation particles is no more than 12.0 μm;
[0026] The thickness of the conductive well region is no more than 2.5 μm, and the gate trench is completely filled after the power transmission is completed.
[0027] By adopting the above technical solution, the Sic VDMOSFET structure can adjust its resistance value in time according to the high temperature generated during power transmission, thereby avoiding short circuit caused by high temperature inside the Sic VDMOSFET structure.
[0028] Preferably, the groove of the source electrode is arranged between the gate grooves and passes through the conductive well region and the source electrode, and the groove of the source electrode is flush with the top of the conductive source region.
[0029] By adopting the above technical solution, the limitations of the use of the SiC VDMOSFET structure are reduced, and at the same time, the problem that the movement of charged particles causes the medium to heat up, which increases the current and causes leakage loss is solved.
[0030] Preferably, the conductive polycrystalline silicon carbide layer is an N-type polycrystalline silicon material with a doping concentration of 1×1020 cm -3 The doping ions are phosphorus ions, copper ions, silicon ions and carbon ions. The first light-blocking layer and the second light-blocking layer are both P-type SiC materials. The doping concentration of the first light-blocking layer is 0.5×1027cm -3 The doping concentration of the second light-blocking layer is 1.5×1027cm -3 , and the doping ions of the P-type SiC material on the first light-blocking layer and the second light-blocking layer are one or more of phosphorus ions, copper ions, silicon ions and carbon ions,
[0031] By adopting the above technical solution, the current can be controlled in real time through the heat dissipation particles, thereby improving the use effect of the SicVDMOSFET device and reducing the production cost. The light-blocking layer can effectively reduce light reflection during device preparation and increase the device etching accuracy.
[0032] Compared with the prior art, the beneficial effects of the present invention are:
[0033] 1. In the present invention, by providing gate trenches and dielectric layer trenches, when the Sic VDMOSFET structure is in use, the gate trenches and the dielectric layer trenches form multiple conductive channels. By penetrating the conductive well region, and the depth of the dielectric layer trench in the conductive well region is significantly greater than the depth of the gate trench, the electric field strength to which the gate dielectric of the Sic VDMOSFET device is subjected in the power-off state can be effectively reduced, thereby preventing gate oxide breakdown before the device is broken down, thereby improving the operating stability and reliability of the device. At the same time, the gate dielectric layer divides the Sic VDMOSFET device into an asymmetric structure, thereby preventing the Sic VDMOSFET device from bipolar degradation effect and increasing the stability of the Sic VDMOSFET device in use.
[0034] 2. In the present invention, by providing heat dissipation particles and adding carbon ions to the doping material of the Sic VDMOSFET, when the Sic VDMOSFET performs power transmission, the resistance can be adjusted by high temperature according to the heat dissipation particles, thereby ensuring that when the Sic VDMOSFET structure transmits high power, the ultra-high electric field will not exceed the critical value of silicon dioxide, thereby achieving self-protection of the Sic VDMOSFET structure, and enabling the Sic VDMOSFET structure to adjust its resistance value in time according to the high temperature generated during power transmission, avoiding the short circuit caused by high temperature inside the Sic VDMOSFET structure, reducing the limitations of the use of the Sic VDMOSFET structure, and solving the problem that the movement of charged particles causes the medium to heat up, which increases the current and causes leakage loss. The heat dissipation particles can control the current in real time, improve the use effect of the Sic VDMOSFET device, and have low production cost. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 This is a schematic diagram of the overall structure of a SiC VDMOSFET structure with low manufacturing cost in the present invention.
[0036] In the figure: 1. drain; 2. conductive substrate layer; 3. conductive epitaxial layer; 4. conductive column region; 41. first P+ contact region; 42. P- contact region; 43. second P+ contact region; 5. buffer structure; 51. heat dissipation particles; 6. gate dielectric layer; 61. conductive polycrystalline silicon carbide layer; 7. conductive well region; 8. source electrode; 9. No. 1 light-blocking layer; 10. No. 2 light-blocking layer; 11. isolation dielectric layer; 12. conductive source region; 13. conductive extension layer; 14. conductive shielding region; 141. gate trench; 142. dielectric layer trench; 71. gate electrode. DETAILED DESCRIPTION
[0037] Example 1
[0038] See also Figure 1, a Sic with lower manufacturing cost A VDMOSFET structure includes a drain 1, a conductive substrate layer 2 is provided above the drain 1, a conductive epitaxial layer 3 is provided on both sides of the upper end of the conductive substrate layer 2, a conductive column region 4 is provided in the middle of the upper end of the conductive substrate layer 2, a gate dielectric layer 6 and a gate electrode 7 are provided above the conductive column region 4, the gate dielectric layer 6 is located within the gate electrode 7, and a conductive polycrystalline silicon carbide layer 61 is provided within the gate dielectric layer 6, a buffer structure 5 is provided above each of the two conductive epitaxial layers 3, a conductive source region 12 and a conductive well region 7 are provided above the two buffer structures 5, a source electrode 8 is provided above the conductive source region 12, above the gate dielectric layer 6, and above the conductive well region 7, one end of the source electrode 8 contacts the buffer structure 5, two first light-blocking layers 9 and a second light-blocking layer 10 are provided above the source electrode 8, the two first light-blocking layers 9 are interlaced with the two second light-blocking layers 10, and a conductive extension layer 13 and a conductive shielding region 14 are provided between the conductive epitaxial layer 3 and the buffer structure 5.
[0039] The doping concentration of the conductive substrate layer 2 is 5×1018 cm -3 ;
[0040] A conductive polycrystalline silicon carbide layer 61 is provided in the gate dielectric layer 6. The doping concentration of the conductive polycrystalline silicon carbide layer 61 is 1.5×10 27 cm -3 , an isolation dielectric layer 11 is provided in the gate dielectric layer 6;
[0041] The top of the isolation dielectric layer 11 contacts the source electrode 8. The thickness of the isolation dielectric layer 11 is not greater than 2.5 μm. The surface doping concentration of the isolation dielectric layer 11 is 1.5×1017 cm -3 .
[0042] The conductive shielding area 14 is located below the conductive extension layer 13, and the depth of the conductive shielding area 14 is not less than 1.5 μm, and the doping concentration is 1e17 cm -3 ~5e19cm -3 .
[0043] A first P+ contact area 41, a P- contact area 42 and a second P+ contact area 43 are provided in the conductive extension layer 13, and a groove corresponding to the conductive shielding area 14 is provided in the conductive extension layer 13, which effectively protects the Schottky diode and reduces the leakage current in the off state, so that the breakdown characteristics of the device are no longer affected by the Schottky diode.
[0044] A gate trench 141 and a dielectric layer trench 142 are provided in the conductive shielding region 14 , and the doping ions of the gate trench 141 and the dielectric layer trench 142 are both set to be one or more of phosphorus ions, copper ions, silicon ions and carbon ions;
[0045] A heterojunction contact is formed on the side of the buffer structure 5 away from the source electrode 8. The heterojunction contact forms a conductive polycrystalline silicon carbide layer 61 by deposition. Under the third quadrant working condition, the unipolar conduction working mechanism of the integrated Schottky diode can eliminate the bipolar degeneration effect.
[0046] The surface doping concentration of the conductive well region 7 is 2.5×1027cm -3 ;
[0047] The doping concentration of the conductive well region 7 near the source electrode 8 is 1×1036 cm -3 , so that the Sic VDMOSFET device can avoid the bipolar degradation effect and increase the stability of the use of the Sic VDMOSFET device.
[0048] The utility model is used in the following steps: In the utility model, when the Sic VDMOSFET structure is in use, the gate trench 141 and the dielectric layer trench 142 form multiple conductive channels, which penetrate the conductive well region 7, and the depth of the dielectric layer trench 142 of the conductive well region 7 is significantly greater than the depth of the gate trench 141. This can effectively reduce the electric field strength borne by the gate dielectric layer 6 of the Sic VDMOSFET device in the power-off state, so that the gate oxide breakdown phenomenon is avoided before the device is broken down, thereby improving the working stability and reliability of the device. At the same time, the gate dielectric layer 6 divides the Sic VDMOSFET device into an asymmetric structure, so that the SicVDMOSFET device avoids the bipolar degradation effect and increases the stability of the Sic VDMOSFET device in use.
[0049] Example 2
[0050] See also Figure 1 , a Sic with lower manufacturing cost A VDMOSFET structure includes a drain 1, a conductive substrate layer 2 is provided above the drain 1, a conductive epitaxial layer 3 is provided on both sides of the upper end of the conductive substrate layer 2, a conductive column region 4 is provided in the middle of the upper end of the conductive substrate layer 2, a gate dielectric layer 6 and a gate electrode 7 are provided above the conductive column region 4, the gate dielectric layer 6 is located within the gate electrode 7, and a conductive polycrystalline silicon carbide layer 61 is provided within the gate dielectric layer 6, a buffer structure 5 is provided above each of the two conductive epitaxial layers 3, a conductive source region 12 and a conductive well region 7 are provided above the two buffer structures 5, a source electrode 8 is provided above the conductive source region 12, above the gate dielectric layer 6, and above the conductive well region 7, one end of the source electrode 8 contacts the buffer structure 5, two first light-blocking layers 9 and a second light-blocking layer 10 are provided above the source electrode 8, the two first light-blocking layers 9 are interlaced with the two second light-blocking layers 10, and a conductive extension layer 13 and a conductive shielding region 14 are provided between the conductive epitaxial layer 3 and the buffer structure 5.
[0051] The depth of the conductive column region 4 is not less than 1.5 μm, and the doping concentration is 5e16 cm -3 ~1e18cm -3 ;
[0052] The upper end surface of the conductive column area 4 is flush with the upper end surfaces of the two conductive epitaxial layers 3. The resistance can be adjusted by high temperature according to the heat dissipation particles, thereby ensuring that when the Sic VDMOSFET structure transmits high power, the ultra-high electric field will not exceed the critical value of silicon dioxide.
[0053] Two heat dissipation particles 51 are provided in the buffer structure 5 . The two heat dissipation particles 51 are located at different positions and have different sizes. The distance between two adjacent heat dissipation particles 51 is no more than 12.0 μm.
[0054] The thickness of the conductive well region 7 is no more than 2.5 μm, and the gate trench 141 is completely filled after the power transmission is completed.
[0055] The groove of the source electrode 8 is arranged between the gate groove 141 and passes through the conductive well area 7 and the source electrode 8. The groove of the source electrode 8 is flush with the top of the conductive source area 12, which solves the problem that the movement of charged particles causes the medium to heat up, which increases the current and causes leakage loss. The current can be controlled in real time through the heat dissipation particles, thereby improving the use effect of the Sic VDMOSFET device.
[0056] The conductive polycrystalline silicon carbide layer 61 is made of N-type polycrystalline silicon material with a doping concentration of 1×1020 cm -3 The doping ions are phosphorus ions, copper ions, silicon ions and carbon ions. The first light-blocking layer 9 and the second light-blocking layer 10 are both P-type SiC materials. The doping concentration of the first light-blocking layer 9 is 0.5×1027cm -3 The doping concentration of the second light-blocking layer 10 is 1.5×1027cm -3 , and the doping ions of the P-type SiC material on the first light-blocking layer 9 and the second light-blocking layer 10 are one or more of phosphorus ions, copper ions, silicon ions and carbon ions.
[0057] The utility model uses the following steps: The utility model adds carbon ions to the doping material of the Sic VDMOSFET, so that when the Sic VDMOSFET performs power transmission, the resistance can be adjusted by high temperature according to the heat dissipation particles 51, thereby ensuring that when the Sic VDMOSFET structure transmits high power, the ultra-high electric field will not exceed the critical value of silicon dioxide, thereby achieving self-protection of the Sic VDMOSFET structure, so that the Sic VDMOSFET structure can adjust its resistance value in time according to the high temperature generated during power transmission, avoiding the short circuit caused by high temperature inside the Sic VDMOSFET structure, reducing the limitations of the use of the Sic VDMOSFET structure, and solving the problem that under the action of an external electric field, the charged particles of the insulating material will move and cause a weak current, and the leakage current will cause the medium to heat up when flowing through the medium, which will increase the current and cause leakage loss. The two heat dissipation particles 51 have different positions and different transmission powers. The heat dissipation particles can control the current in real time, thereby improving the use effect of the Sic VDMOSFET device.
[0058] The above shows and describes the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The above embodiments and descriptions are merely preferred examples of the present invention and are not intended to limit the present invention. Various changes and improvements may be made to the present invention without departing from the spirit and scope of the present invention, and such changes and improvements fall within the scope of the present invention. The scope of protection claimed in the present invention is defined by the appended claims and their equivalents.
Claims
1. A SiC VDMOSFET structure with low manufacturing cost, comprising a drain (1), characterized in that: A conductive substrate layer (2) is provided above the drain electrode (1), conductive epitaxial layers (3) are provided on both sides of the upper end of the conductive substrate layer (2), a conductive column region (4) is provided in the middle of the upper end of the conductive substrate layer (2), a gate dielectric layer (6) and a gate electrode (71) are provided above the conductive column region (4), the gate dielectric layer (6) is located inside the gate electrode (71), a conductive polycrystalline silicon carbide layer (61) is provided inside the gate dielectric layer (6), a buffer structure (5) is provided above the two conductive epitaxial layers (3), and a buffer structure (5) is provided above the two buffer structures (5). A conductive source region (12) and a conductive well region (7) are provided; a source electrode (8) is provided above the conductive source region (12), above the gate dielectric layer (6), and above the conductive well region (7); one end of the source electrode (8) is in contact with the buffer structure (5); two first light-blocking layers (9) and a second light-blocking layer (10) are provided above the source electrode (8); the two first light-blocking layers (9) are respectively interlaced with the two second light-blocking layers (10); and a conductive extension layer (13) and a conductive shielding region (14) are provided between the conductive epitaxial layer (3) and the buffer structure (5).
2. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: The doping concentration of the conductive substrate layer (2) is 5×1018 cm -3 ; A conductive polycrystalline silicon carbide layer (61) is provided in the gate dielectric layer (6), and the doping concentration of the conductive polycrystalline silicon carbide layer (61) is 1.5×1027 cm -3 , an isolation dielectric layer (11) is provided in the gate dielectric layer (6); The top of the isolation dielectric layer (11) contacts the source electrode (8), the thickness of the isolation dielectric layer (11) is no more than 2.5 μm, and the surface doping concentration of the isolation dielectric layer (11) is 1.5×1017 cm -3 .
3. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: The conductive shielding area (14) is located below the conductive extension layer (13), and the depth of the conductive shielding area (14) is not less than 1.5 μm, and the doping concentration is 1e17 cm -3 ~5e19cm -3 .
4. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: A first P+ contact area (41), a P- contact area (42) and a second P+ contact area (43) are provided in the conductive extension layer (13), and a groove corresponding to the conductive shielding area (14) is provided in the conductive extension layer (13).
5. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: A gate trench (141) and a dielectric layer trench (142) are provided in the conductive shielding area (14), and the doping ions of the gate trench (141) and the dielectric layer trench (142) are both set to be one or more of phosphorus ions, copper ions, silicon ions and carbon ions; A heterojunction contact is formed on a side of the buffer structure (5) away from the source electrode (8), and the heterojunction contact forms a conductive polycrystalline silicon carbide layer (61) by deposition.
6. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: The surface doping concentration of the conductive well region (7) is 2.5×1027 cm -3 ; The doping concentration of the conductive well region (7) close to the source electrode (8) boundary is 1×1036 cm -3 .
7. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: The depth of the conductive column region (4) is not less than 1.5 μm, and the doping concentration is 5e16 cm -3 ~1e18cm -3 ; The upper end surface of the conductive column region (4) is flush with the upper end surfaces of the two conductive epitaxial layers (3).
8. The SiC VDMOSFET structure with low manufacturing cost according to claim 1, characterized in that: Two heat dissipation particles (51) are provided in the buffer structure (5), the two heat dissipation particles (51) are located at different positions and have different sizes, and the distance between two adjacent heat dissipation particles (51) is no more than 12.0 μm; The thickness of the conductive well region (7) is no more than 2.5 μm, and the gate trench (141) is completely filled after power transmission is completed.
9. The SiC VDMOSFET structure with low manufacturing cost according to claim 4, characterized in that: The groove of the source electrode (8) is arranged between the gate grooves (141) and passes through the conductive well region (7) and the source electrode (8), and the groove of the source electrode (8) is flush with the top of the conductive source region (12).
10. The SiC VDMOSFET structure with low manufacturing cost according to claim 2, characterized in that: The conductive polycrystalline silicon carbide layer (61) is an N-type polycrystalline silicon material with a doping concentration of 1×1020 cm -3 The doping ions are phosphorus ions, copper ions, silicon ions and carbon ions. The first light-blocking layer (9) and the second light-blocking layer (10) are both P-type SiC materials. The doping concentration of the first light-blocking layer (9) is 0.5×1027 cm -3 The doping concentration of the second light-blocking layer (10) is 1.5×1027cm -3 , and the doping ions of the P-type SiC material on the first light-blocking layer (9) and the second light-blocking layer (10) are one or more of phosphorus ions, copper ions, silicon ions and carbon ions.
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