Array substrate, display panel and display device

Abstract

The embodiment of the utility model provides an array substrate, a display panel and a display device, relates to the technical field of display, and is used for improving the electrostatic protection capability of the display device. The array substrate comprises a display area and a fan-out area located on one side of the display area. The array substrate comprises a substrate, a plurality of data lines, a plurality of fan-out lines, an electrostatic protection structure and a grounding structure, wherein the data lines and the fan-out lines are arranged on the substrate, and the electrostatic protection structure and the grounding structure are arranged in the fan-out area. The plurality of fan-out lines are located in the fan-out area, and each fan-out line is connected with at least one data line; the electrostatic protection structure is located on the side, away from the substrate, of the fan-out lines, and the electrostatic protection structure is electrically connected with the grounding structure. Wherein the fan-out lines comprise target wiring sections, the multiple target wiring sections of the multiple fan-out lines are arranged at intervals in the first direction, and the first direction is parallel to a boundary line of the fan-out area and the display area; in the thickness direction of the substrate, the electrostatic protection structure covers a plurality of target wiring sections of the plurality of fan-out lines.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Liquid crystal displays (LCDs) are widely used in the display field due to their small size, low power consumption, thinness, and radiation-free nature. With the development of display technology, their display quality has also been continuously improved along with advancements in manufacturing processes. Utility Model Content

[0003] An object of the embodiments of the present disclosure is to provide an array substrate, a display panel, and a display device, so as to improve the electrostatic protection capability of the display device.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, an array substrate is provided. The array substrate includes a display area and a fan-out area located on one side of the display area. The array substrate includes a substrate, a plurality of data lines and a plurality of fan-out lines disposed on the substrate, and an electrostatic protection structure and a grounding structure disposed in the fan-out area. The plurality of fan-out lines are located in the fan-out area, each of the fan-out lines being connected to at least one data line. The electrostatic protection structure is located on a side of the plurality of fan-out lines away from the substrate and is electrically connected to the grounding structure. The fan-out lines include target routing segments, and the plurality of target routing segments of the plurality of fan-out lines are arranged at intervals along a first direction parallel to a boundary between the fan-out area and the display area. The electrostatic protection structure covers the plurality of target routing segments of the plurality of fan-out lines in the thickness direction of the substrate.

[0006] An electrostatic protection structure is arranged on a side of the plurality of fan-out lines away from the substrate, and the electrostatic protection structure covers a plurality of target routing segments of the plurality of fan-out lines. That is, when static electricity generated by friction between a human hand and the surface of the liquid crystal display device enters the display panel, the static electricity will be adsorbed on the electrostatic protection structure and transmitted to the grounding structure electrically connected to the electrostatic protection structure through the electrostatic protection structure. The static electricity is discharged through the grounding structure, which can prevent the static electricity from being released on the target routing segment and causing damage to the target routing segment. The electrostatic protection capability can be improved without affecting the contrast of the display device, thereby improving the service life and reliability of the display device.

[0007] In some embodiments, the grounding structure includes a first grounding electrode, which is arranged on at least one of the two opposite sides of the multiple fan-out lines in the first direction; the electrostatic protection structure includes connected connecting lines and at least one shielding portion, the connecting lines extend along the first direction and are connected to the first grounding electrode; in the thickness direction of the substrate, each of the shielding portions covers at least one target routing segment of at least one of the fan-out lines.

[0008] In some embodiments, the electrostatic protection structure includes a plurality of shielding parts, which are arranged along the first direction, and each shielding part covers a target routing segment of the fan-out line; the connecting line is located on one side of the plurality of shielding parts in the second direction, and the second direction is perpendicular to the first direction.

[0009] In some embodiments, the shielding portion includes a first sub-portion and a second sub-portion connected to each other, the width of the first sub-portion being greater than the width of the second sub-portion; the width of the first sub-portion or the second sub-portion is the dimension of the first sub-portion or the second sub-portion in the width direction of the shielding portion.

[0010] In some embodiments, the shielding portion includes two second sub-portions, and the first sub-portion is connected between the two second sub-portions.

[0011] In some embodiments, the two second sub-portions have different sizes in the length direction.

[0012] In some embodiments, a midpoint of the first sub-portion in the length direction of the shielding portion coincides with a midpoint of the shielding portion in the length direction.

[0013] In some embodiments, the fan-out line includes a first sub-fan-out line and a second sub-fan-out line connected to each other, the first sub-fan-out line is close to the display area relative to the second sub-fan-out line, the second sub-fan-out line extends along the second direction, and the extension direction of the first sub-fan-out line intersects with the extension direction of the second sub-fan-out line; the distances from the intersection of the first sub-fan-out line and the second sub-fan-out line of at least two of the fan-out lines to the connecting line are not equal; the connecting line is located on the side of the multiple shielding parts close to the display area, and the distance between the first sub-part of the shielding part and the connecting line is positively correlated with the distance from the intersection of the first sub-fan-out line and the second sub-fan-out line of the fan-out line corresponding to the shielding part to the connecting line.

[0014] In some embodiments, a difference between a width of the first sub-portion and a width of the second sub-portion ranges from 3 μm to 6 μm.

[0015] In some embodiments, the width of the connecting line is equal to the width of the shielding portion.

[0016] In some embodiments, the electrostatic protection structure includes a plurality of shielding parts, which are arranged along the first direction, and each shielding part covers a target routing segment of the fan-out line; the connecting line is arranged to intersect with the plurality of shielding parts, and the two ends of each shielding part are respectively located on both sides of the connecting line in the second direction, and the second direction is perpendicular to the first direction.

[0017] In some embodiments, the shielding portion includes a first part and a second part respectively located on both sides of the connecting line in the second direction, and the lengths of the first part and the second part are equal; the length of the first part or the second part is the dimension of the first part or the second part in the length direction of the shielding portion.

[0018] In some embodiments, the width of the connecting line is greater than the width of the shielding portion.

[0019] In some embodiments, the shielding portion has a width greater than or equal to a width of a target routing segment of the fan-out line.

[0020] In some embodiments, the electrostatic protection structure includes a shielding portion, which extends along the first direction and covers at least two target routing segments of at least two fan-out lines; the connecting line is located on one side of the shielding portion in a second direction, and the second direction is perpendicular to the first direction.

[0021] In some embodiments, a dimension of the shielding portion in a second direction is greater than or equal to 400 μm, and the second direction is perpendicular to the first direction.

[0022] In some embodiments, the array substrate further includes a gate conductive layer, a source-drain conductive layer, and a transparent conductive layer stacked in sequence in a direction away from the substrate; wherein the first ground electrode is located in the gate conductive layer, and the electrostatic protection structure is located in the source-drain conductive layer and / or the transparent conductive layer.

[0023] In some embodiments, the array substrate also includes a gate dielectric layer located between the gate conductive layer and the source-drain conductive layer, and a passivation layer located between the source-drain conductive layer and the transparent conductive layer; the transparent conductive layer includes a first transfer electrode, which is arranged on at least one of the two opposite sides of the multiple fan-out lines in the first direction; the electrostatic protection structure is located in the source-drain conductive layer; the first transfer electrode is connected to the first ground electrode through a first via hole penetrating the gate dielectric layer and the passivation layer, and the first transfer electrode is connected to the connecting line of the electrostatic protection structure through a second via hole penetrating the passivation layer.

[0024] In some embodiments, the multiple fan-out lines are divided into multiple fan-out line groups, each of which includes at least one fan-out line; the electrostatic protection structure also includes a shielding connection portion, which is arranged between two adjacent fan-out line groups, and the shielding connection portion is connected to the connection line.

[0025] In some embodiments, the shielding connection portion is located in the source-drain conductive layer, and the shielding connection portion is provided with a plurality of hollow holes penetrating the shielding connection portion.

[0026] In some embodiments, the plurality of hollow holes further penetrate the gate dielectric layer and the passivation layer.

[0027] In some embodiments, a dimension of the shielding connection portion in a second direction is greater than a length of the shielding portion, and the second direction is perpendicular to the first direction.

[0028] In some embodiments, the array substrate further includes a plurality of binding pin groups, each of the binding pin groups includes at least one binding pin, and each of the binding pins is connected to one of the fan-out lines; the grounding structure includes a second grounding electrode, which is arranged on at least one side of the binding pin group in the first direction, and the second grounding electrode is connected to the shielding connection portion.

[0029] In some embodiments, two second ground electrodes are provided between two adjacent binding pin groups, one of the second ground electrodes is provided close to one of the binding pin groups, and the other second ground electrode is provided close to the other binding pin group; the two ends of the shielding connection part in the first direction are respectively connected to the two second ground electrodes.

[0030] In some embodiments, the binding pin group includes a ground pin; the second ground electrode is located on a side of the ground pin away from the substrate, and the second ground electrode and the ground pin overlap in the thickness direction of the substrate; the second ground electrode is connected to the ground pin.

[0031] In some embodiments, the ground pin is located in the gate conductive layer, and the second ground electrode is located in the source and drain conductive layer; the transparent conductive layer includes a second transfer electrode, which is arranged on the side of the second ground electrode away from the substrate; the second transfer electrode is connected to the second ground electrode and the ground pin through a third via hole that penetrates the passivation layer, the second ground electrode and the gate dielectric layer.

[0032] In another aspect, a display panel is provided. The display panel includes: an array substrate according to any embodiment of the first aspect above; and an opposing substrate disposed opposite the array substrate; wherein the opposing substrate includes a first boundary, the first boundary being located in an area where multiple target routing segments of multiple fan-out lines of the array substrate are located, and the first boundary intersects the multiple target routing segments.

[0033] The above-mentioned display panel has the same structure and beneficial technical effects as the array substrate provided in some of the above-mentioned embodiments, which will not be described in detail here.

[0034] In some embodiments, the first boundary of the opposing substrate passes through midpoints of the plurality of target trace segments in the length direction.

[0035] In another aspect, a display device is provided, comprising: a display panel according to any one of the embodiments in the above-mentioned other aspect, and a driving circuit board connected to the display panel.

[0036] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0038] Figure 1 A planar structural diagram of a display device provided according to some embodiments of the present disclosure;

[0039] Figure 2 Another structural diagram of a display device provided according to some embodiments of the present disclosure;

[0040] Figure 3 is another cross-sectional structural diagram of a display device provided according to some embodiments of the present disclosure;

[0041] Figure 4 A cross-sectional structural diagram of a display device provided by some embodiments of the related art;

[0042] Figure 5A A planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0043] Figure 5B According to some embodiments of the present disclosure, Figure 5A A partially enlarged structural diagram of the array substrate in FIG.

[0044] Figure 5C Another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0045] Figure 5D According to some embodiments of the present disclosure, Figure 5C A partially enlarged structural diagram of the array substrate in FIG.

[0046] Figure 6A A planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0047] Figure 6B According to some embodiments of the present disclosure, Figure 6A A partially enlarged structural diagram of the array substrate in FIG.

[0048] Figure 6C According to some embodiments of the present disclosure, Figure 6B A cross-sectional view of the array substrate taken along section line CC';

[0049] Figure 6D According to some embodiments of the present disclosure, Figure 6B A cross-sectional view of the array substrate taken along the cross-sectional line DD';

[0050] Figure 6E According to some embodiments of the present disclosure, Figure 5D A cross-sectional view of the array substrate taken along the cross-sectional line EE';

[0051] Figure 7A FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0052] Figure 7B According to some embodiments of the present disclosure, Figure 7A A partially enlarged structural diagram of the array substrate in FIG.

[0053] Figure 8 FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0054] Figure 9A FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0055] Figure 9B According to some embodiments of the present disclosure, Figure 9A A partially enlarged structural diagram of the array substrate in FIG.

[0056] Figure 10 FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0057] Figure 11A FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0058] Figure 11B According to some embodiments of the present disclosure, Figure 11A A cross-sectional view of the array substrate taken along the cross-sectional line FF';

[0059] Figure 11C According to some embodiments of the present disclosure, Figure 11A A cross-sectional view of the array substrate taken along the cross-sectional line GG';

[0060] Figure 12 FIG1 is another planar structural diagram of an array substrate provided according to some embodiments of the present disclosure;

[0061] Figure 13 A structural diagram of a display device provided according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0062] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0063] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0064] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0065] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0066] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0067] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining that" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0068] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0069] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values may, in practice, be based on additional conditions or values beyond those stated.

[0070] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0071] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0072] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0073] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0074] For ease of description below, an XYZ coordinate system is established. The third direction Z is perpendicular to the substrate, i.e., the thickness direction in this application. The XY plane is perpendicular to the Z direction, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0075] It should be noted that, for example, 51 / 5 appearing in the drawings of the present disclosure indicates that component 51 belongs to component 5, and for example, 1051 (105) indicates that component 1051 is arranged in the film layer 105. Other similar numbers appearing in the drawings also follow the above description.

[0076] like Figure 1 As shown, some embodiments of the present disclosure provide a display device 1000 .

[0077] Exemplarily, the display device 1000 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or graphic. More specifically, it is contemplated that the embodiments described may be implemented in or associated with a variety of electronic devices, such as, but not limited to, mobile phones, television (TV) products, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., speedometer displays), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), and the like. Figure 1 In the figure, the display device 1000 is taken as a TV product as an example for illustration.

[0078] Exemplarily, the display device 1000 may be a Thin Film Transistor-Liquid Crystal Display (TFT-LCD) device.

[0079] In some embodiments, please refer to Figure 1 and Figure 2 The display device 1000 includes a display panel 100 and a driving circuit board 200. The driving circuit board 200 is electrically connected to the display panel 100.

[0080] For example, the driving circuit board 200 in the display device 1000 may be a printed circuit board (PCB).

[0081] Exemplarily, the display device 1000 further includes a plurality of chip on films 300 (COFs), which are connected to the driving circuit board 200 , and the driving circuit board 200 can be electrically connected to the display panel 100 through the chip on films 300 (COFs).

[0082] Exemplarily, the display device 1000 also includes a driver chip 400, which is configured to drive the display panel 100 to display images. The driver chip 400 can be packaged by a chip-on-film 300, chip-on-glass (COG), chip-on-flexible material (Chip-On-Pi, COP), etc., and bound to the display panel 100.

[0083] For example, the driver chip 400 in the display device 1000 can be packaged by a chip on film 300 (Chip On Film, referred to as COF). In the case where the driver chip 400 in the display device 1000 is packaged by a chip on film 300 (Chip On Film, referred to as COF), the display device 1000 includes a chip on film assembly, and the chip on film assembly may include a flexible printed circuit (FPC) and a driver chip bound to the flexible printed circuit (FPC). Exemplarily, one end of the flexible circuit board connected to the chip on film has a gold finger (not shown in the figure), and the gold finger and the chip on film 300 are connected by an anisotropic conductive film (ACF), and the ACF film includes a glue layer and a plurality of metal balls (such as gold balls) distributed in the glue layer.

[0084] In some embodiments, the display device 1000 may further include an optical element (not shown).

[0085] For example, the optical element may include a camera, so that the display device 1000 can realize various functions such as taking photos, recording videos, or face recognition.

[0086] The optical element may also include a sensor, etc. For example, the optical element may include an under-screen fingerprint recognition sensor, so that the display device 1000 can implement functions such as fingerprint recognition. For another example, the optical element may include an infrared sensor.

[0087] The display panel 100 is described in detail below.

[0088] In some embodiments, as Figure 1 As shown, Figure 1FIG1 is a planar structural diagram of a display panel 100 according to some embodiments. The display panel 100 may be a rectangular structure.

[0089] It should be noted that the above-mentioned “rectangular structure” means that the shape of the boundary of the display panel 100 is rectangular as a whole, for example, Figure 1 As shown, the long side and the short side of the rectangle are right angles at each intersection (ie, corners), so that the boundary of the display panel 100 is a right-angled rectangle in a plan view.

[0090] In other embodiments, the display panel 100 may also be a circular structure, or other shapes with corners.

[0091] In the following, some embodiments of the present disclosure are schematically described by taking the display panel 100 as a rectangular structure as an example. However, the embodiments of the present disclosure include but are not limited to this. The shape of the display panel 100 may also be any other shape.

[0092] In some embodiments, please refer to Figure 1 The display panel 100 includes a display area AA for displaying an image, and a peripheral area AN located on at least one side of the display area AA.

[0093] For example, the peripheral area AN of the display panel 100 may be located at one side of the display area AA of the display panel 100 .

[0094] Alternatively, the peripheral area AN of the display panel 100 may be located on opposite sides of the display area AA of the display panel 100 .

[0095] Alternatively, please continue reading Figure 1 , the peripheral area AN of the display panel 100 may surround the display area AA of the display panel 100 .

[0096] It should be noted that the specific configuration of the peripheral area AN of the display panel 100 is related to the specific design of the display panel 100 and can be designed according to actual needs. The following uses the example of the peripheral area AN of the display panel 100 surrounding the display area AA of the display panel 100 as an example to schematically illustrate some embodiments of the present disclosure.

[0097] For example, a gate driver array (GOA) and control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) may be disposed in the peripheral area AN of the display panel 100. However, the functions of the peripheral area AN of the display panel 100 include but are not limited to these.

[0098] In some embodiments, as Figure 3As shown, when the display panel 100 is a thin film transistor liquid crystal display (TFT-LCD) panel, the display panel 100 may include an array substrate 10, an opposing substrate 20, and a liquid crystal layer 30. The opposing substrate 20 and the array substrate 10 are disposed opposite to each other and spaced apart, and the liquid crystal layer 30 is disposed between the array substrate 10 and the opposing substrate 20.

[0099] For example, please refer to Figure 3 , the opposing substrate 20 in the display panel 100 may be a color filter substrate.

[0100] Exemplarily, the liquid crystal layer includes liquid crystal material located in the display area AA. The display panel further includes a sealant (not shown) surrounding the liquid crystal material, which can connect the array substrate 10 and the counter substrate 20 .

[0101] In one possible embodiment, the display panel is a liquid crystal display panel, the display device including the display panel is a liquid crystal display device, and the liquid crystal display device further includes a backlight panel, which is located on the side of the array substrate 10 away from the opposing substrate 20. Exemplarily, the liquid crystal display panel can be an advanced super dimensional field switching (Advanced Super Dimension Switch, ADS) liquid crystal display panel, or the liquid crystal display panel is a high aperture ratio and advanced super dimensional field switching (High-Adwanced Dimension Switch, HADS) liquid crystal display panel. Exemplarily, the liquid crystal display device further includes a backlight panel and a power supply circuit, the backlight panel is located on the backlight surface of the display panel and is used to provide a light source for the liquid crystal display panel, and the power supply circuit is used to power the display panel.

[0102] For example, the display area AA of the display panel 100 includes a plurality of sub-pixels, each of which may include a pixel electrode and a common electrode. The pixel electrode and the common electrode are disposed opposite to each other, and a pixel capacitor may be formed between the pixel electrode and the common electrode.

[0103] Exemplarily, the material of the pixel electrode may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0104] The material of the common electrode may also include a transparent conductive material, for example, the material of the common electrode may include indium tin oxide (ITO) or indium zinc oxide (IZO).

[0105] An electric field is generated within the display panel 100, causing the liquid crystal molecules within the liquid crystal layer 30 of the display panel 100 to deflect under the action of the electric field. By adjusting the intensity of the electric field applied to the liquid crystal layer 30 of the display panel 100, the degree of deflection of the liquid crystal molecules within the liquid crystal layer 30 can be controlled, thereby controlling the amount of light transmitted through the region where the liquid crystal molecules are located within the liquid crystal layer 30, thereby enabling the display panel 100 to display images.

[0106] For example, the electric field driving the liquid crystal molecules in the liquid crystal layer 30 to deflect in the display panel 100 may be generated when a voltage is applied to the pixel electrode and the common electrode in the sub-pixel.

[0107] Figure 4 FIG. 1 is a cross-sectional structural diagram of a liquid crystal display device in the related art. Figure 4 As shown, in the related art, the liquid crystal display device includes a liquid crystal display panel 100' and a circuit board 200'. The liquid crystal display panel includes an array substrate 10' and an opposing substrate 20', and a liquid crystal layer 30' located between the array substrate 10' and the opposing substrate 20'. The array substrate 10' includes a substrate 1' and a plurality of data lines 2' located on the substrate 1'. The substrate 1' has a display area A' and a fan-out area B' located outside the display area. The orthographic projection of the plurality of data lines 2' on the substrate 1' overlaps with the fan-out area B', and at least part of the fan-out area B' is located outside the orthographic projection of the opposing substrate 2' on the substrate 1'. The orthographic projection of part of the circuit board 200' on the substrate 1' is located in the fan-out area B' and the circuit board 200' is electrically connected to the data lines 2'. It should be noted that, Figure 1 Only one data line 2' is shown as an example.

[0108] It should be noted that as the display field has gradually increased the contrast requirements for liquid crystal display panels, in addition to reducing the problem of dark-state light leakage, it is also necessary to reduce the reflectivity of external light to the liquid crystal display panel. In order to reduce the reflectivity, the above-mentioned liquid crystal display device removes the electrode layer for grounding arranged on the side of the opposing substrate 20' away from the array substrate 10'. However, in actual application of the above-mentioned liquid crystal display device, human hands will inevitably touch the surface of the liquid crystal display device, and static electricity will be generated due to friction. After the electrode layer is removed, the surface of the opposing substrate 20' loses the ability to conduct static electricity, resulting in a weakening of the electrostatic protection capability of the entire liquid crystal display device. External static electricity will enter the liquid crystal display panel along the edge of the opposing substrate 20' close to the fan-out area B', and then flow to the fan-out area, causing the data line 2' to be damaged by static electricity. As Figure 4As shown, the liquid crystal display panel also includes an adhesive structure 5', which is located in the fan-out area B' and between the array substrate 10' and the counter substrate 20'. In the actual production process, the adhesive structure 5' may be concave on the side close to the counter substrate 20', resulting in a gap between the adhesive structure 5' and the counter substrate 20'. As a result, external static electricity may enter the liquid crystal display panel through the gap. The path of static electricity entering the liquid crystal display panel is shown in the figure. Figure 4 As shown by the arrows in FIG, after the static current reaches the part of the data line 2' located in the fan-out area B', it may further flow along the data line 2' toward the display area A', or further flow along the data line 2' away from the display area A' to the circuit board 200', thereby affecting the display function.

[0109] In other related technologies, in order to improve the electrostatic protection capability of the display device, a whole layer of electrode layer for grounding is made on the side of the opposing substrate 20' away from the array substrate 10', and the electrode layer is located in the display area A' and the fan-out area B'. However, the whole layer of electrode layer in this solution will cause the display panel to have a higher reflectivity to ambient light. If the display panel is a liquid crystal display panel, the whole layer of electrode layer in this solution will also have a high reflectivity to the backlight source emitted by the backlight panel. Therefore, the whole layer of electrode layer for grounding will reduce the contrast of the display panel, resulting in the brightness of the display panel in the dark state not being small enough, which does not meet the needs of users of products such as televisions.

[0110] Based on this, some embodiments of the present disclosure provide an array substrate, a display panel and a display device. By setting an electrostatic protection structure and without setting an electrode layer for grounding that covers the entire display area, the above-mentioned poor display problem can be avoided. At the same time, the electrostatic protection capability of the display device can be improved, the reflectivity can be reduced, and the contrast and reliability of the display device can be improved.

[0111] The array substrate, display panel, and display device provided by the present disclosure are described in detail below.

[0112] In some embodiments, as Figure 2 and Figure 3 As shown, the array substrate 10 provided by the present disclosure includes a display area AA and a fan-out area BB located on one side of the display area AA. The array substrate 10 includes a substrate 1, a plurality of data lines 2 and a plurality of fan-out lines 3 disposed on the substrate 1, and an electrostatic protection structure 4 and a grounding structure 5 disposed in the fan-out area BB. The plurality of fan-out lines 3 are located in the fan-out area BB, each fan-out line 3 being connected to at least one data line 2. The electrostatic protection structure 4 is located on a side of the plurality of fan-out lines 3 away from the substrate 1, and the electrostatic protection structure 4 is electrically connected to the grounding structure 5. Figure 5AThe fan-out line 3 includes a target routing segment 31. The target routing segments 31 of the plurality of fan-out lines 3 are arranged at intervals along a first direction X, and the first direction X is parallel to the boundary line J1 between the fan-out area BB and the display area AA. In the thickness direction of the substrate 1, the electrostatic protection structure 4 covers the target routing segments 31 of the plurality of fan-out lines 3.

[0113] Illustratively, the substrate 1 can be a flexible substrate 1, such as polyethylene terephthalate (PET) film, polyethylene naphthalate two-formicacid glycolester (PEN), polyimide (PI) film, etc.; it can also be a rigid substrate 1, such as a glass substrate 1.

[0114] For example, referring to Figure 2 , multiple fan-out lines 3 are located in the fan-out area BB, each fan-out line 3 is connected to at least one data line 2, that is, one fan-out line 3 can be connected to one data line 2, and one fan-out line 3 can also be connected to multiple data lines 2. Multiple data lines 2 are located in the display area AA, and multiple data lines 2 are used to connect sub-pixels in the display area AA.

[0115] In some embodiments, reference Figure 2 The opposing substrate 20 includes a first boundary B1 , which is located in an area where multiple target routing segments 31 of the multiple fan-out lines 3 of the array substrate 10 are located, and the first boundary B1 intersects the multiple target routing segments 31 .

[0116] It should be noted that, referring to Figure 2 The first boundary B1 is the boundary where static electricity generated by a human hand touching the surface of the liquid crystal display device enters the display panel 100. This first boundary B1 is close to the fan-out area BB. The area where multiple target trace segments 31 are located, i.e., the fan-out lines 3 are susceptible to damage due to static electricity, affecting the display, is referred to as the target area C. The first boundary B1 is located in the area where multiple target trace segments 31 of the multiple fan-out lines 3 of the array substrate 10 are located. In other words, the first boundary B1 is located within the target area C and intersects the multiple target trace segments 31. That is, the two ends of each target trace segment 31 are located on either side of the first boundary B1 in the second direction Y. The second direction Y is perpendicular to the first direction X. The plane formed by the first and second directions X is parallel to the surface of the array substrate 10 on the side closest to the opposing substrate 20. The second direction Y and the first direction X are both perpendicular to the thickness direction.

[0117] Compared with related technologies, Figure 2 Combined with Figure 3In the present application, an electrostatic protection structure 4 is arranged on a side of the plurality of fan-out lines 3 away from the substrate 1, and the electrostatic protection structure 4 covers a plurality of target routing segments 31 of the plurality of fan-out lines 3, that is, the electrostatic protection structure 4 covers the target area C, and the electrostatic protection structure 4 overlaps with the first boundary B1. When static electricity generated by friction between a human hand and the surface of the liquid crystal display device enters the display panel 100 along the first boundary B1, the static electricity will be adsorbed on the electrostatic protection structure 4 and transmitted to the grounding structure 5 electrically connected to the electrostatic protection structure 4 through the electrostatic protection structure 4. The static electricity is discharged through the grounding structure 5, which can avoid the static electricity from being released on the target routing segment 31 in the target area C, causing damage to the target routing segment 31, and can improve the electrostatic protection capability without affecting the contrast of the display device, thereby improving the service life and reliability of the display device.

[0118] It should be noted that the electrostatic protection structure 4 covers multiple target routing segments 31 of multiple fan-out lines 3. In addition to the above-mentioned function of providing electrostatic protection to the multiple target routing segments 31, the electrostatic protection structure 4 can also protect the multiple target routing segments 31 from being scratched. Since the electrostatic protection structure 4 overlaps with the first boundary B1, the first boundary B1 needs to be cut in the process of forming the opposing substrate 20. During the cutting process, the electrostatic protection structure 4 can prevent cutting debris from causing damage to the multiple target routing segments 31.

[0119] In some embodiments, reference Figure 5A and Figure 5C The grounding structure 5 includes a first grounding electrode 51, which is arranged on at least one side of the plurality of fan-out lines 3 on opposite sides in the first direction X; the electrostatic protection structure 4 includes a connecting line 41 and at least one shielding portion 42 connected thereto, the connecting line 41 extending along the first direction X and connected to the first grounding electrode 51; Figure 6A 、 Figure 7A 、 Figure 8 、 Figure 9A and Figure 10 , combined with Figure 3 In the thickness direction of the substrate 1 , each shielding portion 42 covers at least one target routing segment 31 of at least one fan-out line 3 .

[0120] It should be noted that, referring to Figure 5A and Figure 5C , in some embodiments, Figure 5C The portion of the connecting line 41 close to the ground structure 5 is a bent structure. Figure 5CThe bending structure of the connecting line 41 is bent at a right angle, that is, the extending direction of the connecting line 41 is bent from the first direction X to the second direction Y, and then bent again through the second direction Y to the first direction X, and finally connected to the ground structure 5 in the first direction X. This arrangement is to avoid other components provided on the array substrate, avoid interference between the connecting line 41 and other components, and at the same time avoid interference between signals transmitted between other lines provided on the same layer as the connecting line 41, thereby improving the quality of the display device.

[0121] It is understandable that, referring to Figure 5D The position where the connecting wire 41 is connected to the ground structure 5 is slightly below the ground structure 5 in the second direction Y, and is set according to the wiring method of the above-mentioned connecting wire 41. That is, based on the arrangement of the connecting wire 41, the position of the ground structure 5 slightly below in the second direction Y is easier to connect with the connecting wire 41 at a position relatively lower than the ground structure 5. Therefore, in addition to complying with the principle of proximity, this setting can also simplify wiring and avoid winding.

[0122] Exemplarily, the first ground electrode 51 is provided on at least one of the two opposite sides of the plurality of fan-out lines 3 in the first direction X, that is, the first ground electrode 51 is provided on any one of the two opposite sides of the plurality of fan-out lines 3 in the first direction X, or the first ground electrode 51 is provided on the two opposite sides of the plurality of fan-out lines 3 in the first direction X. Figure 5A , Figure 5A The first grounding electrodes 51 shown in FIG are arranged on opposite sides of the plurality of fan-out lines 3 in the first direction X. In this way, static electricity can be grounded simultaneously through the first grounding electrodes 51 on both sides, thereby achieving the effect of quickly releasing static electricity.

[0123] In some embodiments, reference Figure 6A 、 Figure 7A 、 Figure 8 and Figure 9A The electrostatic protection structure 4 includes a plurality of shielding portions 42, which are arranged along the first direction X, and each shielding portion 42 covers a target routing segment 31 of a fan-out line 3; the connecting line 41 is located on one side of the plurality of shielding portions 42 in the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0124] For example, referring to Figure 6A 、 Figure 7A 、 Figure 8 and Figure 9A The connecting line 41 is located on one side of the plurality of shielding parts 42 in the second direction Y, and the connecting line 41 is located on the one side of the plurality of shielding parts 42 in the second direction Y. Figure 2 , that is, the connecting line 41 may be located on the side of the plurality of shielding portions 42 close to the display area AA, or the connecting line 41 may be located on the side of the plurality of shielding portions 42 away from the display area AA. Figure 6A 、 Figure 7A 、 Figure 8 and Figure 9A The connecting line 41 shown in FIG. 4 may be located on a side of the plurality of shielding portions 42 close to the display area AA. This is only an example and is not specifically limited here.

[0125] In some embodiments, reference Figure 7B and Figure 8 , Figure 7B for Figure 7A The shielding portion 42 includes a first sub-portion 42a and a second sub-portion 42b connected to each other. The width W1 of the first sub-portion 42a is greater than the width W2 of the second sub-portion 42b. The width of the first sub-portion 42a or the second sub-portion 42b is the dimension of the first sub-portion 42a or the second sub-portion 42b in the width direction of the shielding portion 42.

[0126] It will be understood that the first sub-portion 42a includes a first side c1 and a second side c2 that are opposite to each other in a set direction, where the set direction is perpendicular to the width direction. The width of the first sub-portion 42a is the distance between the first side c1 and the second side c2, i.e., the dimension of the shielding portion 42 in the width direction. The width direction may be the same as or intersecting the first direction X. The width W2 of the second sub-portion 42b is the same as explained above and is not further described here.

[0127] In the above arrangement, during the process of static electricity being transferred to the shielding portion 42, since the width W1 of the first sub-portion 42a is greater than the width W2 of the second sub-portion 42b, for example, combined with Figure 2 The first sub-portion 42a overlaps with the first boundary B1 of the opposing substrate 20. When static electricity enters the fan-out line 3 along the first boundary B1, the first sub-portion 42a covering the target routing segment 31 of the fan-out line 3 is closer to the static electricity generation position relative to the second sub-portion 42b, which can quickly attract the charge of the static electricity and accelerate the discharge of static electricity, thereby improving the reliability of the display device.

[0128] In some embodiments, reference Figure 7B The difference between the width W1 of the first sub-portion 42 a and the width W2 of the second sub-portion 42 b ranges from 3 μm to 6 μm.

[0129] For example, the width W1 of the first sub-portion 42a is 23 μm, and the width W2 of the second sub-portion 42b is 20 μm. This is just an example. Specifically, the width W1 of the first sub-portion 42a and the width W2 of the second sub-portion 42b only need to satisfy the above difference range.

[0130] In some embodiments, continue to refer to Figure 7B and Figure 8 The shielding portion 42 includes two second sub-portions 42 b , and the first sub-portion 42 a is connected between the two second sub-portions 42 b .

[0131] It is understood that the shielding portion 42 includes two second sub-portions 42b, one of which is located on the side of the first sub-portion 42a closer to the display area AA, and the other is located on the side of the first sub-portion 42a farther from the display area AA. In other words, the first sub-portion 42a can be connected to any position between the two second sub-portions 42b, that is, the two second sub-portions 42b can have different length dimensions. For example, the length direction is the second direction Y.

[0132] Exemplarily, the shielding portion 42 includes two second sub-portions 42b, and the two second sub-portions 42b have unequal sizes in the length direction. Since the first sub-portion 42a of the shielding portion 42 is wider than the width of the other sub-portions, this arrangement can attract static electricity over a larger range in the length direction to avoid discharge on the target routing segment 31 of the fan-out line 3.

[0133] In some embodiments, reference Figure 7B The midpoint of the first sub-portion 42 a in the length direction of the shielding portion 42 coincides with the midpoint of the shielding portion 42 in the length direction.

[0134] For example, referring to Figure 7B The length direction is the second direction Y, and the midpoint of the first sub-portion 42a in the length direction of the shielding portion 42 coincides with the midpoint of the length direction of the shielding portion 42. That is, the first sub-portion 42a is equidistant from one end of the two second sub-portions 42b that is away from the first sub-portion 42a.

[0135] In some embodiments, reference Figure 8 The fan-out line 3 includes a first sub-fan-out line 301 and a second sub-fan-out line 302 connected to each other. The first sub-fan-out line 301 is closer to the display area AA than the second sub-fan-out line 302. The second sub-fan-out line 302 extends along the second direction Y, and the extension direction of the first sub-fan-out line 301 intersects with the extension direction of the second sub-fan-out line 302. The distances from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of at least two fan-out lines 3 to the connecting line 41 are not equal. The connecting line 41 is located on the side of the multiple shielding parts 42 close to the display area AA. The distance between the first sub-part 42a of the shielding part 42 and the connecting line 41 is positively correlated with the distance from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3 corresponding to the shielding part 42 to the connecting line 41.

[0136] For example, Figure 8As shown, the extension direction of the first sub-fan-out line 301 intersects with the extension direction of the second sub-fan-out line 302, that is, the first sub-fan-out line 301 and the second sub-fan-out line 302 can form a certain angle, the vertex of which is the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302. Figure 8 Taking the leftmost fan-out line 3 and the rearmost fan-out line 3 in FIG as an example, the distance d1 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 to the connection line 41 is smaller than the distance d2 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 to the connection line 41. Figure 8 This is merely an example. Here, it is sufficient that the distance d1 between the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 and the connection line 41 is not equal to the distance d2 between the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 and the connection line 41. For example, the distance d1 between the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 and the connection line 41 may also be greater than the distance d2 between the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 and the connection line 41.

[0137] For example, when the connecting line 41 is located on one side of the plurality of shielding portions 42 close to the display area AA, it can be seen from the above description that: Figure 8 The distance d1 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the leftmost fan-out line 3 to the connection line 41 is less than the distance d2 from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the rightmost fan-out line 3 to the connection line 41. Figure 8 The distance between the first sub-portion 42a of the shielding portion 42 corresponding to the leftmost fan-out line 3 and the connecting line 41 is d3, and the distance between the first sub-portion 42a of the shielding portion 42 corresponding to the rightmost fan-out line 3 and the connecting line 41 is d4, where d3<d4. For example, d3=0 μm.

[0138] It should be noted that, since the tip discharge is more likely to accumulate charge at the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3, in order to improve the electrostatic protection capability and better protect the fan-out line 3, the distance between the first sub-part 42a of the shielding part 42 and the connecting line 41 is positively correlated with the distance from the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3 corresponding to the shielding part 42 to the connecting line 41. In other words, combined with Figure 2In the process of static electricity entering the target routing segment 31 of the fan-out line 3 along the first boundary B1 of the opposing substrate 20, the first sub-portion 42a of the shielding portion 42 covering the target routing segment 31 is closer to the location where the charge accumulates. Moreover, since the first sub-portion 42a of the shielding portion 42 is wider than the other sub-portions, it can better attract the charge, thereby avoiding discharge at the intersection of the first sub-fan-out line 301 and the second sub-fan-out line 302 of the fan-out line 3.

[0139] For example, the target routing segment 31 of the fan-out line 3 can be part of the first sub-fan-out line 301 or part of the second sub-fan-out line 302, without limitation. This application provides a detailed description of the target routing segment 31 as part of the second sub-fan-out line 302. The target routing segment 31 as part of the first sub-fan-out line 301 is described with reference to the description of the target routing segment 31 as part of the second sub-fan-out line 302.

[0140] In some embodiments, reference Figure 6B , the width W3 of the connecting line 41 is equal to the width W4 of the shielding portion 42 .

[0141] For example, referring to Figure 6B Setting the width W3 of the connecting line 41 equal to the width W4 of the shielding portion 42 can simplify the process of forming the electrostatic protection structure. Exemplarily, the process of forming the electrostatic protection structure is an etching process.

[0142] In some embodiments, reference Figure 9A and Figure 9B The electrostatic protection structure 4 includes a plurality of shielding portions 42, which are arranged along the first direction X, and each shielding portion 42 covers a target routing segment 31 of a fan-out line 3; the connecting line 41 is arranged to intersect with the plurality of shielding portions 42, and the two ends of each shielding portion 42 are respectively located on both sides of the connecting line 41 in the second direction Y, and the second direction Y is perpendicular to the first direction X.

[0143] For example, referring to Figure 9A and Figure 9B The connecting line 41 is arranged to intersect with multiple shielding parts 42, and the two ends of each shielding part 42 are respectively located on both sides of the connecting line 41 in the second direction Y. That is to say, the connecting line 41 is located in the area where the target routing segment 31 is located, and the two ends of each shielding part 42 are at the edge positions of the area where the target routing segment 31 is located. Since the connecting line 41 is continuous and there is no interruption in the middle, when static electricity flows to the connecting line 41, the connecting line 41 can quickly attract the charge and transfer it along the first direction X, thereby improving the electrostatic protection capability of the electrostatic protection structure.

[0144] In some embodiments, continue to refer to Figure 9A and Figure 9BThe shielding portion 42 includes a first portion 421 and a second portion 422, respectively located on both sides of the connecting line 41 in the second direction Y, and the lengths of the first portion 421 and the second portion 422 are equal; the length of the first portion 421 or the second portion 422 is the dimension of the first portion 421 or the second portion 422 in the length direction of the shielding portion 42.

[0145] For example, referring to Figure 9A and Figure 9B The first part 421 and the second part 422 are located on both sides of the connecting line 41 in the second direction Y, and the lengths of the first part 421 and the second part 422 are equal, that is, the distance between the connecting line 41 and the first part 421 away from the side of the second part 422 is equal to the distance between the connecting line 41 and the second part 422 away from the side of the first part 421.

[0146] It should be noted that the length direction here refers to the extension direction of the first portion 421 or the second portion 422. Figure 9A and Figure 9B The extension direction of the first part 421 or the second part 422 shown in the figure is the second direction Y. This is just an example. The extension direction of the first part 421 or the second part 422 can also be any direction that intersects with the second direction Y and is not perpendicular to the second direction Y.

[0147] In some embodiments, reference Figure 9A and Figure 9B As shown, the width W3 of the connecting line 41 is greater than the width W4 of the shielding portion 42 .

[0148] For example, referring to Figure 9A and Figure 9B Setting the width W3 of the connecting line 41 to be larger than the width W4 of the shielding portion 42 can increase the electrostatic adsorption area and reduce the impedance during the signal transmission process of the connecting line 41.

[0149] In some embodiments, reference Figure 6B 、 Figure 7B 、 Figure 8 、 Figure 9B and Figure 10 The width W4 of the shielding portion 42 is greater than or equal to the width W5 of the target routing segment 31 of the fan-out line 3 .

[0150] For example, when one shielding portion 42 covers one target routing segment 31, Figure 6B 、 Figure 9B As shown, the width W4 of the shielding portion 42 is greater than the width W5 of the target routing segment 31 of the fan-out line 3. Figure 7B 、 Figure 8As shown, the width W1 of the first sub-portion and the width W2 of the second sub-portion of the shielding portion 42 are both greater than the width W5 of the target routing segment 31 of the fan-out line 3 .

[0151] For example, when one shielding portion 42 covers a plurality of target routing segments 31, refer to Figure 10 , a width W4 of the shielding portion 42 is greater than a width W5 of the target routing segment 31 of the fan-out line 3 .

[0152] The above figure only illustrates an example in which the shielding portion width W4 is greater than the width W5 of the target routing segment 31 of the fan-out line 3. In other embodiments, the shielding portion width W4 is equal to the width W5 of the target routing segment 31 of the fan-out line 3. This width setting enables the target routing segment 31 to be completely covered by the shielding portion 42. In other words, the shielding portion 42 can absorb and conduct away static electricity charges above the target routing segment 31, protecting the target routing segment 31 from static electricity.

[0153] In some embodiments, as Figure 10 As shown, the electrostatic protection structure 4 includes a shielding portion 42, which extends along a first direction X and covers at least two target routing segments 31 of at least two fan-out lines 3; the connecting line 41 is located on one side of the shielding portion 42 in a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0154] For example, referring to Figure 10 The shielding portion 42 covers multiple target routing segments 31 of multiple fan-out lines 3. This arrangement can increase the electrostatic adsorption area, improve the electrostatic attraction efficiency, and facilitate the rapid desorption of static electricity.

[0155] In some embodiments, reference Figure 6B Combine Figure 2 The dimension of the shielding portion 42 in the second direction Y is greater than or equal to 400 μm, and the second direction Y is perpendicular to the first direction X.

[0156] Exemplarily, the dimension d5 of the shielding portion 42 in the second direction Y is greater than or equal to 400 μm. The minimum dimension of the shielding portion 42 in the second direction Y is limited here based on the position of the first boundary B1 of the opposing substrate 20. Since the opposing substrate 20 needs to be cut during the preparation process, the first boundary B1 after cutting is located in the area where multiple target wiring segments 31 are located. That is to say, in the process of static electricity entering the display panel 100 along the first boundary B1, the area where the target wiring segments 31 are located are all locations where static electricity may be easily released. Electrostatic protection in this area can ensure that static electricity is effectively adsorbed and discharged. The minimum dimension of the above-mentioned shielding portion 42 in the second direction Y may also be the dimension of the area where the target wiring segment 31 is located in the second direction Y.

[0157] In some embodiments, reference Figure 2 The first boundary B1 of the counter substrate 20 passes through the midpoints of the target routing segments 31 of the fan-out lines 3 in the length direction.

[0158] It should be noted that since the first boundary B1 of the opposing substrate 20 is the boundary where static electricity enters the display panel 100, and the first boundary B1 passes through the midpoints of multiple target routing segments 31 of multiple fan-out lines 3 in the length direction, that is to say, the static electricity release position is set at the midpoint of the target routing segment 31 in the length direction, that is, the static electricity release position is located in the middle position of the electrostatic protection structure 4, which can ensure that all static electricity can be adsorbed by the electrostatic protection structure 4 and transferred to the grounding structure 5, thereby playing a role in protecting the target routing segment 31, improving the electrostatic protection capability of the display panel 100, and thereby improving the service life of the display panel 100.

[0159] Exemplarily, the first boundary B1 of the opposing substrate 20 passes through the midpoint of the multiple target routing segments 31 of the multiple fan-out lines 3 in the length direction. Since the first boundary B1 of the opposing substrate 20 is the cutting position of the opposing substrate 20, that is, the cutting position of the opposing substrate 20 is located at the midpoint of the multiple target routing segments 31 in the length direction, with this arrangement, the electrostatic protection structure 4 can better protect the multiple target routing segments 31 of the multiple fan-out lines 3, and avoid the generation of cutting debris during the cutting process of the opposing substrate 20 to damage the multiple target routing segments 31 of the multiple fan-out lines 3.

[0160] The arrangement of each film layer of the array substrate 10 is described in detail below.

[0161] In some embodiments, reference Figure 6C 、 Figure 6D and Figure 6E ,in, Figure 6E for Figure 5B The cross-sectional structure diagram obtained by making a cross section along the cross-sectional line EE' is as follows: Figure 6E The array substrate 10 further includes a gate conductive layer 101, a gate dielectric layer 102, a source-drain conductive layer 103, a passivation layer 104, and a transparent conductive layer 105, which are stacked in sequence in a direction away from the substrate 1. The first ground electrode 51 is located on the gate conductive layer 101, and the electrostatic protection structure 4 is located on the source-drain conductive layer 103 and / or the transparent conductive layer 105.

[0162] For example, the gate dielectric layer 102 and the passivation layer 104 can be made of silicon oxide SiOx, silicon nitride SiNx, silicon oxynitride SiON, etc., and can be a single-layer, double-layer or multi-layer structure to achieve the effect of blocking water and oxygen and blocking alkaline ions, and can be deposited by a plasma enhanced chemical vapor deposition (PECVD) process.

[0163] For example, the material of the transparent conductive layer 105 may include a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0164] The following takes the ESD protection structure 4 located in the source-drain conductive layer 103 as an example to introduce the specific structure and connection of the ESD protection structure 4 .

[0165] In some embodiments, reference Figure 5A 、 Figure 5B and Figure 6E , Figure 5B for Figure 5A A partial enlarged view of Figure 6E for Figure 5B The cross-sectional structure is shown along section line EE'. The transparent conductive layer 105 includes a first transfer electrode 1051, disposed on at least one of two opposing sides of the plurality of fan-out lines 3 in the first direction X. The electrostatic protection structure 4 is located in the source-drain conductive layer 103. The first transfer electrode 1051 is connected to the first ground electrode 51 via a first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104. The first transfer electrode 1051 is also connected to the connection line 41 of the electrostatic protection structure 4 via a second via G2 penetrating the passivation layer 104.

[0166] For example, referring to Figure 5A , Figure 5A The first transfer electrodes 1051 shown in FIG are located on the transparent conductive layer 105, and the first transfer electrodes 1051 are arranged on two opposite sides of the plurality of fan-out lines 3 in the first direction X. Figure 6E The first transfer electrode 1051 is connected to the first ground electrode 51 through a first via G1 that penetrates the gate dielectric layer 102 and the passivation layer 104, and the first transfer electrode 1051 is connected to the connection line 41 of the electrostatic protection structure 4 through a second via G2 that penetrates the passivation layer 104. In other words, the first transfer electrode 1051 can serve to connect the connection line 41 of the electrostatic protection structure 4 and the first ground electrode 51. It should be noted that the depths of the first via G1 and the second via G2 are different.

[0167] In some embodiments, reference Figure 5A, the plurality of fan-out lines 3 are divided into a plurality of fan-out line groups 310, each fan-out line group 310 includes at least one fan-out line 3; Figure 11A The electrostatic protection structure 4 further includes a shielding connection portion 43 , which is disposed between two adjacent fan-out line groups 310 , and the shielding connection portion 43 is connected to the connection line 41 .

[0168] Exemplarily, each fan-out line group 310 includes at least one fan-out line 3, that is, each fan-out line group 310 may include one fan-out line 3 or multiple fan-out lines 3; Figure 5A As shown, Figure 5A The fan-out line group 310 shown in FIG. 3 includes a plurality of fan-out lines 3 .

[0169] It should be noted that, referring to Figure 11A , a shielding connection portion 43 is provided, the shielding connection portion 43 is connected between two adjacent fan-out line groups 310, and the shielding connection portion 43 is connected to the connecting line 41, as shown Figure 11A As shown, the shielding connection portion 43 is a whole surface, which can increase the electrostatic adsorption area of the electrostatic protection structure 4, so that the static electricity is more distributed in the area between the two adjacent fan-out line groups 310, and at the same time can reduce the static electricity distribution above the target routing segment 31 of the multiple fan-out lines 3, so as to reduce the risk of damage to the target routing segment 31 of the multiple fan-out lines 3.

[0170] In some embodiments, continue to refer to Figure 11A The shielding connection portion 43 is located in the source-drain conductive layer 103 , and the shielding connection portion 43 is provided with a plurality of hollow holes 431 penetrating the shielding connection portion 43 .

[0171] For example, referring to Figure 11A , Figure 11A The shielding connection portion 43 is provided with a plurality of hollow holes 431 , which is provided in order to improve the light transmittance and ensure that the curing of the adhesive layer provided between the array substrate 10 and the counter substrate 20 is not affected.

[0172] In some embodiments, continue to refer to Figure 11C The plurality of hollow holes 431 also penetrate the gate dielectric layer 102 and the passivation layer 104 .

[0173] For example, referring to Figure 11C , Figure 11C The figure shows a cross-sectional structure diagram of the shielding connection portion 43 . A plurality of hollow holes 431 also penetrate the gate dielectric layer 102 and the passivation layer 104 , which can further improve the light transmittance.

[0174] In some embodiments, continue to refer to Figure 11A The dimension of the shielding connection portion 43 in the second direction Y is greater than the length of the shielding portion 42 , and the second direction Y is perpendicular to the first direction X.

[0175] Exemplarily, the dimension of the shielding connection part 43 in the second direction Y is L1, and the length of the shielding part 42 is L2. Setting L1>L2 is mainly to transfer most of the static electricity to the shielding connection part 43 to avoid static electricity accumulation and thereby increase the speed of static electricity release.

[0176] In some embodiments, reference Figure 12 The array substrate 10 also includes a plurality of binding pin groups 110, each binding pin group 110 includes at least one binding pin 111, and each binding pin 111 is connected to a fan-out line 3; the grounding structure 5 includes a second grounding electrode 52, which is arranged on at least one side of the binding pin group 110 in the first direction X, and the second grounding electrode 52 is connected to the shielding connection portion 43.

[0177] For example, referring to Figure 12 Combine Figure 11A The array substrate 10 includes a plurality of binding pin groups 110, and the plurality of binding pin groups 110 are arranged on the side of the fan-out line group 310 away from the display area AA. Each binding pin group 110 is connected to a corresponding fan-out line group 310, and each binding pin group 110 may include one binding pin 111, or may include multiple binding pins 111; when a binding pin group 110 includes one binding pin 111, one binding pin 111 is connected to a corresponding fan-out line 3; when a binding pin group 110 includes multiple binding pins 111, each fan-out line group 310 also includes multiple fan-out lines 3, and the number of binding pins 111 is the same as that of the fan-out lines 3, and one binding pin 111 is connected to a corresponding fan-out line 3.

[0178] Combine Figure 11B , Figure 11B The source-drain conductive layer 103 is provided with a second ground electrode 52, referring to Figure 11A and Figure 12 The second ground electrode 52 is arranged on at least one side of the binding pin group 110 in the first direction X, that is, the second ground electrode 52 can be arranged on any side of the binding pin group 110 in the first direction, or can be arranged on both sides of the binding pin group 110 in the first direction at the same time. Figure 12 The position of the second ground electrode 52 is only an example. Figure 12 It can be seen that among the multiple binding pin groups 110, along the first direction X, the second grounding electrodes 52 of the two outermost binding pin groups 110 are both located on one side of the binding pin group 110, and the second grounding electrode 52 is located on the side adjacent to the shielding connection part 43; except for the two outermost binding pin groups 110, the remaining binding pin groups 110 are provided with second grounding electrodes 52 on both sides in the first direction X.

[0179] It should be noted that the above-mentioned second grounding electrodes 52 are all connected to the corresponding shielding connection parts 43, and can conduct static electricity adsorbed by the shielding connection parts 43 through the second grounding electrodes 52, so that the static electricity can be released along the shortest path, thereby improving the static electricity release efficiency.

[0180] In some embodiments, continue to refer to Figure 12 Two second ground electrodes 52 are provided between two adjacent binding pin groups 110, one of the second ground electrodes 52 is provided close to one of the binding pin groups 110, and the other second ground electrode 52 is provided close to the other binding pin group 110; the two ends of the shielding connection portion 43 in the first direction X are respectively connected to the two second ground electrodes 52.

[0181] For example, referring to Figure 12 Two second ground electrodes 52 are provided between two adjacent binding pin groups 110 , and each second ground electrode 52 overlaps with the adjacent binding pin group 110 .

[0182] It should be noted that the two ends of the shielding connection part 43 in the first direction X are respectively connected to the two second ground electrodes 52. That is to say, in the process of the shielding connection part 43 adsorbing static electricity, the second ground electrode 52 can quickly conduct the static electricity of the shielding connection part 43 close to the target routing segment 31 of the multiple fan-out lines 3, so as to avoid the accumulation of static electricity above the target routing segment 31 of the multiple fan-out lines 3, thereby improving the electrostatic protection capability.

[0183] In some embodiments, continue to refer to Figure 11A The binding pin group 110 includes a ground pin 112; the second ground electrode 52 is located on the side of the ground pin 112 away from the substrate 1, and the second ground electrode 52 and the ground pin 112 overlap in the thickness direction of the substrate 1; the second ground electrode 52 is connected to the ground pin 112.

[0184] For example, continue to refer to Figure 11A The second ground electrode 52 and the ground pin 112 overlap in the thickness direction of the substrate 1 , that is, the ground pin 112 is also located on both sides of the binding pin group 110 in the first direction X.

[0185] For example, in combination Figure 2 A plurality of connection holes 1101 are provided on the binding pin group 110, and the binding pin group 110 is bound and connected to the cover chip film 300 through the plurality of connection holes 1101. As an example, the binding pin group 110 is located in the gate conductive layer 101, and the plurality of connection holes 1101 penetrate the passivation layer 104 and the gate dielectric layer 102.

[0186] In some embodiments, reference Figure 11BThe ground pin 112 is located on the gate conductive layer 101, and the second ground electrode 52 is located on the source-drain conductive layer 103; the transparent conductive layer 105 includes a second transfer electrode 1052, which is arranged on the side of the second ground electrode 52 away from the substrate 1; the second transfer electrode 1052 is connected to the second ground electrode 52 and the ground pin 112 through a third via G3 that penetrates the passivation layer 104, the second ground electrode 52 and the gate dielectric layer 102.

[0187] For example, referring to Figure 11B Combine Figure 11A The second transfer electrode 1052 is connected to the ground pin 112 through the third via G3 that penetrates the passivation layer 104, the second ground electrode 52 and the gate dielectric layer 102. Due to the setting of the third via G3, the side of the second ground electrode 52 is exposed and electrically connected to the second transfer electrode 1052 at the side wall of the third via G3. The second ground electrode 52 is further connected to the ground pin 112 through the second transfer electrode 1052.

[0188] The following describes the specific connection between the electrostatic protection structure 4 , the first ground electrode 51 , and the second ground electrode 52 when the electrostatic protection structure 4 is located in the transparent conductive layer 105 .

[0189] In some embodiments, the first ground electrode 51 is located in the gate conductive layer 101, and the electrostatic protection structure 4 is located in the transparent conductive layer 105. In this case, the first transfer electrode 1051 located in the transparent conductive layer 105 can be directly connected to the connection line 41 of the electrostatic protection structure 4 located in the transparent conductive layer 105. That is, the connection line of the electrostatic protection structure 4 can be connected to the first ground electrode 51 through the first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104 through the first transfer electrode 1051. There is no need to set the second via G2 to achieve the connection between the electrostatic protection structure 4 and the first ground electrode 51, which can achieve the purpose of simplifying the process to a certain extent. Alternatively, the connection line of the electrostatic protection structure 4 is directly connected to the first ground electrode 51 through the first via G1 penetrating the gate dielectric layer 102 and the passivation layer 104. In this case, the connection with the first ground electrode 51 can be achieved without setting the first transfer electrode 1051.

[0190] In other embodiments, the second ground electrode 52 is located in the source-drain conductive layer 103, and the electrostatic protection structure 4 is located in the transparent conductive layer 105. At this time, the shielding connection part 43 included in the electrostatic protection structure 4 is also located in the transparent conductive layer 105. Based on this, the second transfer electrode 1052 located in the transparent conductive layer 105 can be directly contacted and connected with the shielding connection part 43 of the electrostatic protection structure 4, that is, the shielding connection part 43 of the electrostatic protection structure 4 can be connected to the second ground electrode 52 through the third via G3 that penetrates the gate dielectric layer 102 and the passivation layer 104 through the second transfer electrode 1052.

[0191] In some other embodiments, the second ground electrode 52 can be located in the same layer as the electrostatic protection structure 4, and the second ground electrode 51 and the electrostatic protection structure 4 can both be located in the transparent conductive layer 105. In this case, the shielding connection portion 43 included in the electrostatic protection structure 4 is also located in the transparent conductive layer 105. In this case, the second ground electrode 52 located in the transparent conductive layer 105 can be directly connected to the shielding connection portion 43 of the electrostatic protection structure 4. In other words, when the second ground electrode 52 can be located in the same layer as the electrostatic protection structure 4, the second transfer electrode 1052 set in the transparent conductive layer 105 as described above can be omitted, thereby simplifying the process. It should be noted that the "same layer" here means that the same material is formed by the same patterning process.

[0192] For example, when the second ground electrode 52 and the electrostatic protection structure 4 are both located in the transparent conductive layer 105, the ground pin 112 is located in the gate conductive layer 101, and the second ground electrode 52 can be connected to the ground pin 112 through a via that penetrates the passivation layer 104 and the gate dielectric layer 102. In this arrangement, the second ground electrode 52 and the ground pin 112 can be in direct contact without the need for switching through the second switching electrode 1052. Compared to the case where the second ground electrode 52 is located in the source-drain conductive layer 103, the contact area between the second ground electrode 52 and the ground pin 112 is increased.

[0193] The following describes the specific connection between the electrostatic protection structure 4 and the first ground electrode 51 and the second ground electrode 52 when the structure is partially located in the source-drain conductive layer 103 and partially located in the transparent conductive layer 105 .

[0194] In some embodiments, the shielding portion 42 and the connecting line 41 of the electrostatic protection structure 4 are located in the transparent conductive layer 105, and the shielding connecting portion 43 is located in the source-drain conductive layer 103. The shielding connecting portion 43 can be electrically connected to the connecting line 41 through a via penetrating the passivation layer 104. In this case, the specific connection between the connecting line 41 of the electrostatic protection structure 4 and the first ground electrode 51 refers to the description of the electrostatic protection structure 4 being located in the transparent conductive layer 105. The specific connection between the shielding connecting portion 43 of the electrostatic protection structure 4 and the second ground electrode 52 refers to the description of the electrostatic protection structure 4 being located in the source-drain conductive layer 103, and will not be repeated here.

[0195] In other embodiments, the shielding portion 42 and the connecting line 41 in the electrostatic protection structure 4 are located in the source-drain conductive layer 103, and the shielding connecting portion 43 is located in the transparent conductive layer 105. The shielding connecting portion 43 can be electrically connected to the connecting line 41 through a via penetrating the passivation layer 104. In this case, the specific connection between the connecting line 41 of the electrostatic protection structure 4 and the first ground electrode 51 refers to the description of the electrostatic protection structure 4 being located in the source-drain conductive layer 103. The specific connection between the shielding connecting portion 43 of the electrostatic protection structure 4 and the second ground electrode 52 refers to the description of the electrostatic protection structure 4 being located in the transparent conductive layer 105, and will not be repeated here.

[0196] In some embodiments of the present disclosure, the grounding structure 5 includes a first grounding electrode 51 and a second grounding electrode 52, which can be set at the same time, or only one of the first grounding electrode 51 and the second grounding electrode 52 can be set, as long as the electrostatic protection structure 4 and the grounding structure 5 can be electrically connected.

[0197] Some embodiments of the present disclosure provide a display panel 100, such as Figure 2 As shown, the display panel 100 includes the array substrate 10 provided in any of the above embodiments and the counter substrate 20. Therefore, the display panel 100 provided in the present disclosure has all the beneficial effects of the array substrate 10 provided in any of the above embodiments, which will not be described in detail here.

[0198] In some embodiments, as Figure 2 As shown, on both the left and right sides of the display panel 100, the opposing substrate 20 is retracted into the array substrate 10. In other possible embodiments, on both the left and right sides of the display panel 100, the edges of the opposing substrate 20 and the edges of the array substrate 10 may be flush, or the array substrate 10 may be retracted into the opposing substrate 20, which is not limited in this embodiment of the present application.

[0199] In some embodiments, reference Figure 3 The display panel further includes an adhesive structure 50. The adhesive structure 50 is located between the array substrate 10 and the opposing substrate 20. At least part of the orthographic projection of the adhesive structure 50 on the substrate 1 is located in the fan-out area BB, and the orthographic projection of the adhesive structure 50 on the substrate 1 overlaps with the orthographic projection of the opposing substrate 20 on the substrate 1. Exemplarily, the orthographic projection of the adhesive structure 50 on the substrate 1 is located on one side of the orthographic projection of the sealant on the substrate 1. The adhesive structure 50 can protect the fan-out line 3 located in the fan-out area BB. Optionally, the material of the adhesive structure 50 is a UV-curing adhesive.

[0200] In some embodiments, reference Figure 3The display panel 100 further includes an active layer (not shown) disposed between the gate dielectric layer 102 and the source / drain conductive layer 103. The active layer includes an active pattern, and the active pattern is made of silicon. For example, the gate conductive layer 101 includes a gate pattern, and the source / drain conductive layer 103 includes a source / drain pattern. The gate pattern and the source / drain pattern are made of a metal material, such as a single metal material such as aluminum, copper, molybdenum, chromium, or titanium, or an alloy.

[0201] Exemplarily, the material of the active layer includes any one of low-temperature polysilicon, indium gallium zinc oxide, or low-temperature polycrystalline oxide.

[0202] It should be noted that the above materials are only examples and are not limited to this disclosure. Figure 3 In the embodiment, an array substrate having a bottom-gate thin film transistor (TFT) is used as an example for exemplary description. In other embodiments, the array substrate may also use a top-gate TFT.

[0203] In some embodiments, the display panel 100 further includes a pixel electrode pattern and a common electrode pattern, wherein the pixel electrode pattern may be located on a side of the common electrode pattern away from the substrate 1, or the pixel electrode pattern may be located on a side of the common electrode pattern away from the substrate 1, or the pixel electrode pattern and the common electrode pattern are located on the same layer, for example, the pixel electrode pattern and the common electrode pattern are both located on the transparent conductive layer 105, or the pixel electrode pattern and the common electrode pattern may be located on the array substrate of the display panel at the same time, or the pixel electrode pattern may be located on the opposing substrate of the display panel 100, and the common electrode pattern may be located on the opposing substrate 20 of the display panel 100. In an embodiment of the present application, the pixel electrode pattern and the common electrode pattern are both located on the array substrate 10 of the display panel 100.

[0204] Exemplarily, the material of the pixel electrode pattern and the common electrode pattern is a transparent conductive material such as indium tin oxide (ITO), which can reduce the impact on light output.

[0205] Some embodiments of the present disclosure provide a display device 1000, such as Figure 13 As shown, the display device can be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a car computer, a wearable display device, etc. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above-mentioned display device. Figure 13As shown, the display device 1000 includes the display panel 100 provided in any of the above embodiments, and the display panel 100 includes a display side 100a and a non-display side 100b. Therefore, the display device 1000 provided in the present disclosure has all the benefits of the display panel 100 provided in any of the above embodiments, which will not be described in detail here.

[0206] For example, Figure 13 As shown, the display device 1000 in the embodiment of the present disclosure is exemplified by a liquid crystal display device. Figure 13 In some embodiments, the main structure of the liquid crystal display device 1000 includes a frame 500, a cover plate 600, a display panel 100 and other electronic components.

[0207] The frame 500 surrounds a receiving space, and the display panel 100 and other electronic components are disposed in the receiving space. The cover 600 is disposed on the open side of the frame 500 .

[0208] For example, referring to Figure 13 The display panel 100 includes a liquid crystal layer 30 between an array substrate 10 and an opposing substrate 20 . The array substrate 10 and the opposing substrate 20 can be adhered together by a sealing adhesive 40 , thereby confining the liquid crystal layer 30 within the area enclosed by the sealing adhesive 40 .

[0209] In some embodiments, reference Figure 2 The display device 1000 includes a driving circuit board 200, which includes a grounding terminal 201. The grounding terminal 201 is electrically connected to the grounding pin 112 to achieve a connection between the grounding structure 5 and the grounding terminal 201. When static electricity enters the display panel from the outside and reaches the electrostatic protection structure 4, it can be transferred to the grounding terminal 201 in sequence through the electrostatic protection structure 4, the grounding structure 5, and the grounding pin 112 to achieve grounding.

[0210] It should be noted that since the ground pin 112 is located in the gate conductive layer 101, for example, the ground pin 112 can be electrically connected to the cover chip film 300 by penetrating the passivation layer 104 and the gate dielectric layer 102, and the cover chip film 300 is electrically connected to the driving circuit board 200, that is, the ground pin 112 can be connected to the ground terminal 201 in the driving circuit board 200 through the cover chip film 300.

[0211] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0212] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate comprising a display area and a fan-out area located on one side of the display area, characterized in that: The array substrate includes: substrate; A plurality of data lines and a plurality of fan-out lines are provided on the substrate, wherein the plurality of fan-out lines are located in the fan-out area, and each of the fan-out lines is connected to at least one of the data lines; an electrostatic protection structure and a grounding structure provided in the fan-out area, wherein the electrostatic protection structure is located on a side of the plurality of fan-out lines away from the substrate, and the electrostatic protection structure is electrically connected to the grounding structure; In which, the fan-out line includes a target routing segment, and the multiple target routing segments of the multiple fan-out lines are arranged at intervals along a first direction, and the first direction is parallel to the boundary line between the fan-out area and the display area; in the thickness direction of the substrate, the electrostatic protection structure covers the multiple target routing segments of the multiple fan-out lines.

2. The array substrate according to claim 1, wherein: The grounding structure includes a first grounding electrode disposed on at least one of two opposite sides of the plurality of fan-out lines in the first direction; The electrostatic protection structure includes a connecting line and at least one shielding portion connected to each other, wherein the connecting line extends along the first direction and is connected to the first ground electrode; In the thickness direction of the substrate, each of the shielding portions covers at least one target routing segment of at least one of the fan-out lines.

3. The array substrate according to claim 2, wherein: The electrostatic protection structure includes a plurality of shielding portions, which are arranged along the first direction, and each shielding portion correspondingly covers a target routing segment of the fan-out line; The connecting line is located at one side of the plurality of shielding parts in a second direction, and the second direction is perpendicular to the first direction.

4. The array substrate according to claim 3, wherein: The shielding portion includes a first sub-portion and a second sub-portion connected to each other, wherein the width of the first sub-portion is greater than the width of the second sub-portion; The width of the first sub-portion or the second sub-portion is a dimension of the first sub-portion or the second sub-portion in a width direction of the shielding portion.

5. The array substrate according to claim 4, wherein: The shielding portion includes two second sub-portions, and the first sub-portion is connected between the two second sub-portions.

6. The array substrate according to claim 5, wherein: The two second sub-portions have different sizes in the length direction.

7. The array substrate according to claim 5, wherein: A midpoint of the first sub-portion in the length direction of the shielding portion coincides with a midpoint of the shielding portion in the length direction.

8. The array substrate according to any one of claims 4 to 7, wherein: The fan-out line includes a first sub-fan-out line and a second sub-fan-out line connected to each other, the first sub-fan-out line is closer to the display area than the second sub-fan-out line, the second sub-fan-out line extends along the second direction, and the extension direction of the first sub-fan-out line intersects the extension direction of the second sub-fan-out line; The distances from the intersection of the first sub-fan-out line and the second sub-fan-out line of at least two of the fan-out lines to the connecting line are not equal; The connecting line is located on a side of the multiple shielding parts close to the display area, and the distance between the first sub-part of the shielding part and the connecting line is positively correlated with the distance from the intersection of the first sub-fan-out line and the second sub-fan-out line of the fan-out line corresponding to the shielding part to the connecting line.

9. The array substrate according to claim 8, wherein: The difference between the width of the first sub-portion and the width of the second sub-portion ranges from 3 μm to 6 μm.

10. The array substrate according to claim 3, wherein: The width of the connecting line is equal to the width of the shielding portion.

11. The array substrate according to claim 2, wherein: The electrostatic protection structure includes a plurality of shielding portions, which are arranged along the first direction, and each shielding portion correspondingly covers a target routing segment of the fan-out line; The connecting line is arranged to cross the plurality of shielding portions, and two ends of each shielding portion are respectively located on both sides of the connecting line in a second direction, and the second direction is perpendicular to the first direction.

12. The array substrate according to claim 11, wherein: The shielding portion includes a first portion and a second portion respectively located on both sides of the connecting line in the second direction, and the first portion and the second portion are equal in length; The length of the first portion or the second portion is a dimension of the first portion or the second portion in a length direction of the shielding portion.

13. The array substrate according to claim 11 or 12, characterized in that: The width of the connecting line is greater than the width of the shielding portion.

14. The array substrate according to any one of claims 3 to 7, wherein: The shielding portion has a width greater than or equal to a width of a target routing segment of the fan-out line.

15. The array substrate according to claim 2, wherein: The electrostatic protection structure includes a shielding portion, the shielding portion extends along the first direction, and the shielding portion covers at least two target routing segments of at least two fan-out lines; The connecting line is located on one side of the shielding portion in a second direction, and the second direction is perpendicular to the first direction.

16. The array substrate according to any one of claims 2 to 7, characterized in that: A dimension of the shielding portion in a second direction is greater than or equal to 400 μm, and the second direction is perpendicular to the first direction.

17. The array substrate according to any one of claims 2 to 7, wherein: The array substrate further comprises a gate conductive layer, a source-drain conductive layer and a transparent conductive layer stacked in sequence in a direction away from the substrate; Wherein, the first ground electrode is located in the gate conductive layer, and the electrostatic protection structure is located in the source-drain conductive layer and / or the transparent conductive layer.

18. The array substrate according to claim 17, wherein: The array substrate further includes a gate dielectric layer located between the gate conductive layer and the source / drain conductive layer, and a passivation layer located between the source / drain conductive layer and the transparent conductive layer; The transparent conductive layer includes a first switching electrode, which is arranged on at least one of two opposite sides of the plurality of fan-out lines in the first direction; The electrostatic protection structure is located in the source-drain conductive layer; The first transfer electrode is connected to the first ground electrode through a first via hole penetrating the gate dielectric layer and the passivation layer, and the first transfer electrode is connected to the connection line of the electrostatic protection structure through a second via hole penetrating the passivation layer.

19. The array substrate according to claim 18, wherein: The plurality of fan-out lines are divided into a plurality of fan-out line groups, each of the fan-out line groups includes at least one fan-out line; The electrostatic protection structure further includes a shielding connection portion, which is arranged between two adjacent fan-out line groups, and the shielding connection portion is connected to the connection line.

20. The array substrate according to claim 19, wherein: The shielding connection portion is located on the source-drain conductive layer, and the shielding connection portion is provided with a plurality of hollow holes penetrating the shielding connection portion.

21. The array substrate according to claim 20, wherein: The plurality of hollow holes also penetrate the gate dielectric layer and the passivation layer.

22. The array substrate according to any one of claims 19 to 21, wherein: A dimension of the shielding connection portion in a second direction is greater than a length of the shielding portion, and the second direction is perpendicular to the first direction.

23. The array substrate according to any one of claims 19 to 21, characterized in that: The array substrate further comprises a plurality of binding pin groups, each of the binding pin groups comprises at least one binding pin, and each of the binding pins is connected to one of the fan-out lines; The grounding structure includes a second grounding electrode disposed on at least one side of the binding pin group in the first direction, and the second grounding electrode is connected to the shielding connection portion.

24. The array substrate according to claim 23, wherein: Two second grounding electrodes are provided between two adjacent binding pin groups, wherein one of the second grounding electrodes is provided close to one of the binding pin groups, and the other second grounding electrode is provided close to the other binding pin group; Both ends of the shielding connection portion in the first direction are connected to two of the second ground electrodes respectively.

25. The array substrate according to claim 24, wherein: The binding pin group includes a ground pin; The second ground electrode is located on a side of the ground pin away from the substrate, and the second ground electrode and the ground pin overlap in a thickness direction of the substrate; The second ground electrode is connected to the ground pin.

26. The array substrate according to claim 25, wherein: The ground pin is located in the gate conductive layer, and the second ground electrode is located in the source and drain conductive layer; The transparent conductive layer includes a second switching electrode, which is arranged on a side of the second ground electrode away from the substrate; The second transfer electrode is connected to the second ground electrode and the ground pin through a third via hole that penetrates the passivation layer, the second ground electrode, and the gate dielectric layer.

27. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 26; an opposing substrate disposed opposite to the array substrate; The opposing substrate includes a first boundary, the first boundary is located in an area where multiple target routing segments of multiple fan-out lines of the array substrate are located, and the first boundary intersects the multiple target routing segments.

28. The display panel according to claim 27, wherein: The first boundary of the opposing substrate passes through midpoints of the target routing segments of the fan-out lines in the length direction.

29. A display device, characterized in that: include: The display panel according to claim 27 or 28; A driving circuit board is connected to the display panel.

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