Large-size multi-chip superposition process structure of diode

Abstract

The utility model discloses a large-size multi-chip stacking process structure of a diode. The large-size multi-chip stacking process structure comprises a bottom-layer chip, a middle-layer chip and an upper-layer chip which are sequentially arranged from bottom to top, a connecting sheet is arranged on the eighth welding layer of the upper-layer chip, and a through hole is formed in the connecting sheet; the area size of the first copper particle layer is smaller than the area size of the middle layer chip and the area size of the upper layer chip. According to the scheme, the chips are prevented from being damaged due to overlarge thermal stress in the subsequent technological process and reliability process of the multi-chip stacking technological structure, the chips are prevented from losing efficacy, and epoxy resin can flow into the through holes in the connecting pieces in the epoxy sealing process; therefore, the overall structure of the multi-layer stacked chip and the epoxy resin are combined more tightly, and the combination strength is stronger, so that the layering phenomenon during subsequent cutting and conventional use is avoided, the product quality is improved, and the electrical performance of subsequent products is prevented from being reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of diode chip production, in particular to a large-size multi-chip stacking process structure of a transient voltage suppression diode. Background Art

[0002] A transient voltage suppressor (TVS) diode is an overvoltage protection device with bidirectional voltage regulation and bidirectional negative resistance characteristics, similar to a varistor. It is used in various AC and DC power circuits to suppress transient overvoltages. When a surge voltage pulse appears in the protected circuit, the bidirectional breakdown diode quickly undergoes Zener breakdown, changing from a high-resistance state to a low-resistance state, shunting and clamping the surge voltage, thereby protecting the components in the circuit from damage caused by the transient surge voltage.

[0003] Transient voltage suppressor (TVS) diodes are primarily designed for high-power current protection. To handle high-power currents in circuits, multi-chip stacking is often employed in product design. The applicant has discovered that existing TVS diodes, when designed with multiple chips stacked, exhibit at least the following structural issues:

[0004] 1. When using multi-layer chip stacking, the internal stress generated during production varies with the different structures inside the product. Excessive internal stress can easily damage the chip. For example, the pressure of the product during epoxy injection molding is relatively high, which can easily cause chip damage due to internal stress, thereby causing the product's electrical performance to fail.

[0005] 2. The bonding strength of the multi-layer stacking structure is not enough. During slicing and subsequent use, it is easy for the multi-layer chips to delaminate, thus causing the product to fail.

[0006] In view of this, how to solve the problem of excessive internal stress and easy delamination in the multi-layer chip stacking structure of existing transient voltage suppressor diode TVS products, which leads to product electrical performance failure, has become the subject to be studied and solved by this utility model. Utility Model Content

[0007] The purpose of this utility model is to provide a large-size multi-chip stacking process structure for diodes, which is used to solve the problem that existing transient voltage suppression diode TVS products are easily damaged during multi-layer chip stacking production, resulting in electrical performance failure.

[0008] To achieve the above-mentioned purpose, the present invention proposes a large-size multi-chip stacking process structure for diodes, wherein the multi-chip stacking process structure includes a bottom chip, a middle chip, and an upper chip arranged in sequence from bottom to top;

[0009] The bottom chip includes a first copper particle layer, a first welding layer, a second copper particle layer, a second welding layer, a first crystal particle layer, and a third welding layer arranged from bottom to top;

[0010] The intermediate layer chip includes a third copper grain layer, a fourth welding layer, a second crystal grain layer, and a fifth welding layer arranged from bottom to top;

[0011] The upper chip includes a fourth copper grain layer, a sixth welding layer, a third crystal grain layer, a seventh welding layer, a fifth copper grain layer, and an eighth welding layer arranged from top to bottom;

[0012] A connecting piece is provided on the eighth welding layer of the upper chip, and a through hole is opened on the connecting piece;

[0013] The area size of the first copper particle layer is smaller than the area sizes of the middle layer chip and the upper layer chip.

[0014] The relevant contents of this utility model are explained as follows:

[0015] 1. In the above technical solution of the present invention, the problem of excessive internal stress and easy delamination in the multi-layer chip stacking structure of the existing transient voltage suppressor diode TVS products, which leads to failure of the product electrical performance, is solved, and a large-scale multi-chip stacking process structure of the diode is innovatively developed and designed. In the present invention, the problem of chip damage caused by thermal stress during the process and reliability of the large-scale multi-chip stacking process structure of the diode leading to product failure is solved, and the product structure design and internal structure optimization are carried out. The size with the smallest stress value for chip damage is selected for optimization, and the stress comparison of each group is comprehensively analyzed to select the combination with the lowest stress for the overall stacking process structure as the optimal combination, so as to achieve The multi-chip stacking process structure will not damage the chip due to excessive thermal stress during the subsequent process and reliability process, thus avoiding chip failure; and in view of the problem that the multi-layer stacked chips are prone to delamination during subsequent use, through holes are deliberately provided on the connecting pieces of the multi-layer stacked chips. When epoxy sealing is performed, the epoxy resin fills the through holes on the connecting pieces and completely wraps the part of the multi-chip stacking process structure on the frame. Therefore, during the epoxy sealing process, the epoxy resin will flow into the through holes on the connecting pieces, making the overall structure of the multi-layer stacked chip and the epoxy resin more tightly bonded and more strongly bonded, thereby avoiding the delamination phenomenon during subsequent cutting and routine use, improving product quality, and avoiding the degradation of electrical performance of subsequent products.

[0016] 2. In the above technical solution, the first copper particle layer has a thickness of 0.55-0.65 mm, a length of 4-6 mm, and a width of 4-6 mm. This size provides the lowest stress value, further preventing chip damage caused by thermal stress and leading to product failure.

[0017] 3. In the above technical solution, through holes for filling epoxy resin are provided at the connection point between the connecting sheet and the upper chip and in the middle of the connecting sheet. This further enhances the bonding strength between the overall structure of the multi-layer stacked chips and the epoxy resin, further preventing delamination.

[0018] 4. In the above technical solution, the middle part of the connecting piece is a bend, and a double through-hole is provided in the bend. The double through-hole design further improves the bonding strength.

[0019] 5. In the above technical solution, the multi-chip stacking process structure further includes a sealing part and a frame, and the sealing part covers the bottom chip, middle chip, and upper chip above the frame.

[0020] 6. In the above technical solution, the sealing portion comprises epoxy resin, which flows into the through-holes of the connecting sheet and solidifies, so that the epoxy resin is better bonded to the main structure of the multi-chip stacking process structure.

[0021] 7. In the above technical solution, the upper portion of the connecting piece is overlapped on the eighth solder layer of the upper chip, and the upper portion of the connecting piece is overlapped on the frame. This makes the overall structure of the large-scale multi-chip stacking process structure of the diode more stable and reliable.

[0022] 8. In this utility model, unless otherwise expressly specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; they may refer to mechanical connection, direct connection, or indirect connection through an intermediate medium; they may refer to internal communication between two elements or interaction between two elements, unless otherwise expressly specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0023] 9. In the present invention, the terms "upper", "lower", "bottom", "inside", "outside", etc. indicate orientations or positional relationships based on the orientation or positional assembly relationships shown in the accompanying drawings. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on the present application.

[0024] 10. In addition, in the description of the present invention, it should be noted that if words such as "first" and "second" are used in this document to limit components, those skilled in the art should know that the use of words such as "first" and "second" is only for the convenience of describing the present invention and simplifying the description. Unless otherwise stated, the above words have no special meaning.

[0025] Due to the application of the above scheme, the utility model has the following advantages and effects compared with the prior art:

[0026] In the present invention, the problem of excessive internal stress and easy delamination in the multi-layer chip stacking structure of the existing transient voltage suppression diode TVS products, which leads to failure of the product electrical performance, is solved, and a large-scale multi-chip stacking process structure of the diode is innovatively developed and designed. In the present invention, the problem of chip damage caused by thermal stress during the process and reliability of the large-scale multi-chip stacking process structure of the diode leading to product failure is solved, and the product structure design and internal structure optimization are carried out. The size with the smallest stress value for chip damage is selected for optimization, and the stress comparison of each group is comprehensively analyzed to select the combination with the lowest stress for the overall stacking process structure as the optimal combination, so that the multi-chip stacking The process structure will not damage the chip due to excessive thermal stress during the subsequent process and reliability process, thus avoiding chip failure; and in view of the problem that multi-layer stacked chips are prone to delamination during subsequent use, through holes are deliberately provided on the connecting pieces of the multi-layer stacked chips. When epoxy sealing is performed, the epoxy resin fills the through holes on the connecting pieces and completely wraps the part of the multi-chip stacking process structure on the frame. Therefore, during the epoxy sealing process, the epoxy resin will flow into the through holes on the connecting pieces, making the overall structure of the multi-layer stacked chip and the epoxy resin more tightly bonded and more strongly bonded, thereby avoiding the delamination phenomenon during subsequent cutting and routine use, improving product quality, and avoiding the degradation of electrical performance of subsequent products. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a schematic diagram of the overall structure of a large-scale multi-chip stacking process structure of a diode in an embodiment of the present invention;

[0028] Figure 2 In the embodiment of the present invention Figure 1 A partial enlarged schematic diagram.

[0029] The various parts of the above drawings are shown as follows:

[0030] 100. Multi-chip stacking process structure;

[0031] 110. Bottom chip;

[0032] 111, first copper grain layer; 112, first welding layer; 113, second copper grain layer; 114, second welding layer; 115, first crystal grain layer; 116, third welding layer;

[0033] 120, middle layer chip;

[0034] 121, third copper grain layer; 122, fourth welding layer; 123, second crystal grain layer; 124, fifth welding layer;

[0035] 130, upper chip;

[0036] 131, fourth copper grain layer; 132, sixth welding layer; 133, third crystal grain layer; 134, seventh welding layer; 135, fifth copper grain layer; 136, eighth welding layer;

[0037] 140. Connecting piece; 141. Through hole;

[0038] 150, framework;

[0039] 160. Epoxy resin. DETAILED DESCRIPTION

[0040] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0041] The embodiment of the utility model discloses a large-scale multi-chip stacking process structure 100 for diodes, such as Figure 1 、 Figure 2 As shown, the multi-chip stacking process structure 100 includes a bottom chip 110, an intermediate chip 120, and an upper chip 130 arranged in sequence from bottom to top;

[0042] The bottom chip 110 includes a first copper seed layer 111, a first welding layer 112, a second copper seed layer 113, a second welding layer 114, a first crystal seed layer 115, and a third welding layer 116 arranged from bottom to top;

[0043] The intermediate layer chip 120 includes a third copper seed layer 121, a fourth solder layer 122, a second crystal seed layer 123, and a fifth solder layer 124 arranged from bottom to top;

[0044] The upper chip 130 includes, from top to bottom, a fourth copper grain layer 131 , a sixth solder layer 132 , a third crystal grain layer 133 , a seventh solder layer 134 , a fifth copper grain layer 135 , and an eighth solder layer 136 ;

[0045] A connecting piece 140 is provided on the eighth welding layer 136 of the upper chip 130 , and a through hole 141 is opened on the connecting piece 140 ;

[0046] The area size of the first copper seed layer 111 is smaller than the area sizes of the middle layer chip 120 and the upper layer chip 130 .

[0047] In the embodiment of the present invention, the first copper particle layer 111 has a thickness of 0.55 to 0.65 mm, a length of 4 to 6 mm, and a width of 4 to 6 mm. This size provides the lowest stress value, further preventing chip damage caused by thermal stress and resulting in product failure.

[0048] In the embodiment of the present invention, through holes 141 for filling epoxy resin 160 are provided at the connection portion between the connecting sheet 140 and the upper chip 130 and in the middle portion of the connecting sheet 140. This further enhances the bonding strength between the multi-layer stacked chip structure and the epoxy resin 160, further preventing delamination.

[0049] In the embodiment of the present invention, the middle portion of the connecting piece 140 is a bent portion, and the bent portion is provided with double through holes 141. The design of the double through holes 141 further enhances the bonding strength.

[0050] In an embodiment of the present invention, the multi-chip stacking process structure 100 further includes a sealing portion and a frame 150 , and the sealing portion covers the bottom chip 110 , the middle chip 120 , and the upper chip 130 above the frame 150 .

[0051] In the embodiment of the present invention, the sealing portion includes epoxy resin 160 , which flows into the through hole 141 of the connecting piece 140 and solidifies, so that the epoxy resin 160 is better combined with the main structure of the multi-chip stacking process structure 100 .

[0052] In the embodiment of the present invention, the upper portion of the connecting piece 140 is overlapped on the eighth welding layer 136 of the upper chip 130, and the upper portion of the connecting piece 140 is overlapped on the frame 150. This makes the overall structure of the large-scale multi-chip stacking process structure 100 of the diode more stable and reliable.

[0053] Through the implementation of the embodiments of the present invention, the problem of excessive internal stress and easy delamination in the multi-layer chip stacking structure of existing transient voltage suppression diode TVS products, which leads to failure of product electrical performance, is solved, and a large-scale multi-chip stacking process structure 100 of diodes is innovatively developed and designed. In the present invention, the problem of chip damage caused by thermal stress in the process and reliability of the large-scale multi-chip stacking process structure 100 of diodes leading to product failure is solved, and the product structure design and internal structure optimization of the product are carried out. The size with the smallest stress value for chip damage is selected for optimization, and the stress comparison of each group is comprehensively considered to select the combination with the lowest stress for the overall stacking process structure as the optimal combination, so that the multi-chip stacking process structure 100 can be used in the subsequent During the process and reliability process, the chip will not be damaged due to excessive thermal stress, thus avoiding chip failure; and in view of the problem that the multi-layer stacked chip is prone to stratification during subsequent use, a through hole 141 is deliberately provided on the connecting piece 140 of the multi-layer stacked chip. When epoxy sealing is performed, the epoxy resin 160 fills the through hole 141 on the connecting piece 140 and completely wraps the part of the multi-chip stacking process structure 100 on the frame 150, so that during the epoxy sealing process, the epoxy resin 160 will flow into the through hole 141 on the connecting piece 140, so that the overall structure of the multi-layer stacked chip and the epoxy resin 160 are more tightly combined with a stronger bonding force, thereby avoiding the stratification phenomenon during subsequent cutting and routine use, improving product quality, and avoiding the degradation of electrical performance of subsequent products.

[0054] The technical solution of the present invention is further described below with a more specific and detailed embodiment.

[0055] The large-size multi-chip stacking process structure 100 of a diode proposed in this detailed embodiment includes a frame 150, a bottom chip 110, an intermediate chip 120, an upper chip 130, a sealing portion, and a connecting piece 140; the bottom chip 110, the intermediate chip 120, and the upper chip 130 are arranged on the frame 150 from bottom to top, the upper part of the connecting piece 140 is overlapped on the upper chip 130, and the upper part of the connecting piece 140 is overlapped on the frame 150, and the sealing portion covers the bottom chip 110, the intermediate chip 120, and the upper chip 130 above the frame 150.

[0056] In this detailed embodiment, the bottom chip 110 includes, from bottom to top, a first copper grain layer 111, a first solder layer 112, a second copper grain layer 113, a second solder layer 114, a first crystal grain layer 115, and a third solder layer 116. The middle chip 120 includes, from bottom to top, a third copper grain layer 121, a fourth solder layer 122, a second crystal grain layer 123, and a fifth solder layer 124. The upper chip 130 includes, from top to bottom, a fourth copper grain layer 131, a sixth solder layer 132, a third crystal grain layer 133, a seventh solder layer 134, a fifth copper grain layer 135, and an eighth solder layer 136. The area of the first copper grain layer 111 is smaller than that of the middle and upper chips 120 and 130. The first copper grain layer 111 has a thickness of 0.55 to 0.65 mm, a length of 4 to 6 mm, and a width of 4 to 6 mm.

[0057] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those familiar with the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications based on the spirit of the present invention are intended to be included in the scope of protection of the present invention.

Claims

1. A large-scale multi-chip stacking process structure for diodes, characterized by: The multi-chip stacking process structure includes a bottom chip, a middle chip, and an upper chip arranged in sequence from bottom to top; The bottom chip includes a first copper particle layer, a first welding layer, a second copper particle layer, a second welding layer, a first crystal particle layer, and a third welding layer arranged from bottom to top; The intermediate layer chip includes a third copper grain layer, a fourth welding layer, a second crystal grain layer, and a fifth welding layer arranged from bottom to top; The upper chip includes a fourth copper grain layer, a sixth welding layer, a third crystal grain layer, a seventh welding layer, a fifth copper grain layer, and an eighth welding layer arranged from top to bottom; A connecting piece is provided on the eighth welding layer of the upper chip, and a through hole is opened on the connecting piece; The area size of the first copper particle layer is smaller than the area sizes of the middle layer chip and the upper layer chip.

2. The large-scale multi-chip stacking process structure of diodes according to claim 1, characterized in that: The first copper particle layer has a thickness of 0.55 to 0.65 mm, a length of 4 to 6 mm, and a width of 4 to 6 mm.

3. The large-scale multi-chip stacking process structure of diodes according to claim 1, characterized in that: Through holes for filling epoxy resin are provided at the portion where the connecting piece is connected to the upper chip and at the middle portion of the connecting piece.

4. The large-scale multi-chip stacking process structure of diodes according to claim 3, characterized in that: The middle portion of the connecting piece is a bent portion, and the bent portion is provided with double through holes.

5. The large-scale multi-chip stacking process structure of diodes according to claim 3, characterized in that: The multi-chip stacking process structure further includes a sealing portion and a frame, wherein the sealing portion covers the bottom chip, the middle chip, and the upper chip above the frame.

6. The large-scale multi-chip stacking process structure of diodes according to claim 5, characterized in that: The sealing portion includes epoxy resin, and the epoxy resin flows into the through hole of the connecting piece and solidifies.

7. The large-scale multi-chip stacking process structure of diodes according to claim 5, characterized in that: The upper portion of the connecting piece is overlapped on the eighth welding layer of the upper chip, and the upper portion of the connecting piece is overlapped on the frame.

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