Vector network analysis device based on PXIe interface

Abstract

The utility model discloses a vector network analysis device based on a PXIe interface. The output end of a first signal generation unit is connected with the input end of a switch unit; two output ends of the switch unit are correspondingly connected with the input end of the first directional coupler and the input end of the second directional coupler; a straight-through output end of the first directional coupler is connected with a first test port, and two coupling output ends of the first directional coupler are connected with a first input end of the receiving frequency conversion channel unit; the straight-through output end of the second directional coupler is connected with the second test port, and the two coupling output ends of the second directional coupler are connected with the second input end of the receiving frequency conversion channel unit. According to the utility model, a 2-port vector network analysis function is realized in a single PXIe slot, real multi-port measurement can be realized by configuring a plurality of devices, the number of ports of the vector network analyzer does not need to be expanded through a mode of externally arranging a switch matrix, the time cost of measurement is reduced, and index deterioration is avoided.

Description

Technical Field

[0001] The utility model relates to the field of radio frequency microwave network parameter testing, and in particular to a vector network analysis device based on a PXIe interface. Background Art

[0002] A vector network analyzer is a test instrument used to measure the parameters of radio frequency microwave networks. It characterizes the characteristics of the network by measuring the amplitude and phase response of the network. It is an essential test and measurement instrument in the radio frequency microwave field and is widely used in wireless communications, aerospace, automotive, electronics manufacturing and other fields.

[0003] Traditional benchtop vector network analyzers are large and take up a lot of space, making them unsuitable for building miniaturized multi-port test systems and incurring high purchase costs. Benchtop vector network analyzers rely on external switch matrices to expand their port count. When measuring multi-port networks, the switch matrix must be switched to each port sequentially, increasing measurement time and cost. The additional losses and external circuitry can also degrade key vector network analyzer specifications, such as dynamic range and temperature stability. Utility Model Content

[0004] In response to the above-mentioned deficiencies in the prior art, the present invention provides a vector network analysis device based on a PXIe interface, which solves the problem that existing desktop vector network analyzers use an external switch matrix to expand the number of their ports, increase the measurement time cost, and cause the indicators to deteriorate.

[0005] In order to achieve the above-mentioned purpose of the invention, the technical solution adopted by the present invention is:

[0006] A vector network analysis device based on a PXIe interface is provided, comprising a first signal generating unit and a second signal generating unit, wherein the output end of the first signal generating unit is connected to the input end of a switch unit; the two output ends of the switch unit are correspondingly connected to the input end of a first directional coupler and the input end of a second directional coupler; the through output end of the first directional coupler is connected to a first test port, and the two coupled output ends of the first directional coupler are connected to the first input end of a receiving frequency conversion channel unit; the through output end of the second directional coupler is connected to a second test port, and the two coupled output ends of the second directional coupler are connected to the second input end of the receiving frequency conversion channel unit;

[0007] The output end of the second signal generating unit is connected to the local oscillator signal input end of the receiving frequency conversion channel unit;

[0008] The output end of the receiving frequency conversion channel unit is connected to the analog-to-digital conversion unit; the receiving frequency conversion channel unit, the analog-to-digital conversion unit, the first signal generating unit and the second signal generating unit are respectively connected to the FPGA chip; the FPGA chip is connected to the host computer through the PXIe interface.

[0009] Furthermore, the receiving frequency conversion channel unit includes two groups of receiving channels, each group of receiving channels includes a reference signal receiver and a measurement signal receiver; the reference signal receiver and the measurement signal receiver in the same group of receiving channels are correspondingly connected to the two coupled output ends of the first directional coupler; the reference signal receiver and the measurement signal receiver in the other group of receiving channels are correspondingly connected to the two coupled output ends of the second directional coupler.

[0010] Furthermore, the input end of the second signal generating unit is connected to a local oscillator input port, and the output end of the second signal generating unit is connected to a local oscillator output port for connecting to the local oscillator input port of the second signal generating unit in other vector network analysis devices based on the PXIe interface.

[0011] The beneficial effects of the utility model are:

[0012] 1. This device implements 2-port vector network analysis in a single PXIe slot. Multiple devices can be configured to achieve true multi-port measurements, eliminating the need to expand the number of ports on the vector network analyzer through an external switch matrix.

[0013] 2. Multiple devices can be inserted into multiple PXIe slots and controlled and cascaded through the local oscillator input port and local oscillator output port. Up to 16 devices can be configured in a standard 3U PXIe chassis to form a 32-port vector network analysis system. Without introducing an external switch matrix, it can meet the testing needs of different users, reduce user costs, and improve the flexibility of system integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the structural block diagram of the device;

[0015] Figure 2 This is the multi-port cascade block diagram of this device. DETAILED DESCRIPTION

[0016] The specific implementation methods of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific implementation methods. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations conceived using the present invention are protected.

[0017] like Figure 1 As shown, the vector network analysis device based on the PXIe interface includes a first signal generating unit and a second signal generating unit, wherein the output end of the first signal generating unit is connected to the input end of the switch unit; the two output ends of the switch unit are correspondingly connected to the input end of the first directional coupler and the input end of the second directional coupler; the through output end of the first directional coupler is connected to the first test port, and the two coupled output ends of the first directional coupler are connected to the first input end of the receiving frequency conversion channel unit; the through output end of the second directional coupler is connected to the second test port, and the two coupled output ends of the second directional coupler are connected to the second input end of the receiving frequency conversion channel unit; wherein the two coupled ends are respectively a reference port and a measurement port;

[0018] The output end of the second signal generating unit is connected to the local oscillator signal input end of the receiving frequency conversion channel unit;

[0019] The output end of the receiving frequency conversion channel unit is connected to the analog-to-digital conversion unit; the receiving frequency conversion channel unit, the analog-to-digital conversion unit, the first signal generating unit and the second signal generating unit are respectively connected to the FPGA chip; the FPGA chip is connected to the host computer through the PXIe interface.

[0020] The receiving frequency conversion channel unit includes two groups of receiving channels, each group of receiving channels including a reference signal receiver and a measurement signal receiver. The reference signal receiver and the measurement signal receiver in one group of receiving channels are connected to the two coupled output terminals of the first directional coupler, respectively; the reference signal receiver and the measurement signal receiver in the other group of receiving channels are connected to the two coupled output terminals of the second directional coupler, respectively. In this embodiment, both the reference signal receiver and the measurement signal receiver can be down-converted coherent receivers.

[0021] The input end of the second signal generating unit is connected to the local oscillator input port, and the output end of the second signal generating unit is connected to the local oscillator output port for connecting to the local oscillator input port of the second signal generating unit in other vector network analysis devices based on the PXIe interface.

[0022] During implementation, the FPGA chip controls the two signal generation units to output the desired signals. It also controls the receive frequency conversion channel to condition and switch channels. The FPGA chip also performs digital down-conversion processing on the data output by the analog-to-digital conversion unit, including filtering and decimation, and uploads the processed data to a host computer via a PXIe interface. In this embodiment, the FPGA can utilize a Xilinx A-series FPGA chip. The FPGA chip can control other units using existing methods. This section is not innovative in this application and will not be elaborated on.

[0023] The first signal generating unit is mainly used to provide an excitation signal to the device under test. Therefore, any signal generating device that can provide an excitation signal to the device under test in vector network analysis can be selected as the first signal generating unit in this device. In this embodiment, the first signal generating unit can be a frequency synthesizer with an integrated VCO.

[0024] The switch unit is used to switch the excitation signal generated by the first signal generating unit between the first test port and the second test port. In this embodiment, the switch unit can be a single-pole double-throw switch.

[0025] The second signal generation unit primarily provides a local oscillator signal for the receiving frequency conversion unit. This device utilizes this local oscillator signal when implementing a two-port vector network analysis function in a single PXIe slot. When multiple devices are cascaded across multiple PXIe slots, the second signal generation unit includes a switch that switches the signal path from the slave module's second signal generation unit to the external local oscillator signal input port. This allows the master module's local oscillator signal to enter the slave module, replacing the local oscillator signal generated by the slave module's second signal generation unit. In this embodiment, the second signal generation unit can utilize a frequency synthesizer with an integrated VCO.

[0026] The first directional coupler and the second directional coupler are used as isolation devices for separating the reference signal and the measurement signal. In this embodiment, the first directional coupler and the second directional coupler can be a stripline directional coupler or a Wheatstone bridge.

[0027] The receiving frequency conversion channel unit is configured to receive the first reference signal separated by the first directional coupler, receive the second reference signal separated by the second directional coupler, receive the first measurement signal and the second measurement signal from the device under test, and down-convert the received signals to obtain intermediate frequency signals. The first measurement signal corresponds to the first test port, and the second measurement signal corresponds to the second test port.

[0028] In this embodiment, the device is inserted into a standard 3U PXIe chassis, and the operating frequency band, input power, and other settings required for the normal operation of the device under test are set as needed through the software operation interface of the host computer. The PXIe interface of the chassis computer interacts with the FPGA chip of this device. When the device under test is connected to the first test port and the second test port, the normal operation of the device under test starts. The reference signal and the measurement signal are down-converted to intermediate frequency signals by the receiving frequency conversion channel unit. After being processed by the analog-to-digital conversion unit, they are sent to the FPGA chip, and then communicate with the external host computer through the PXIe interface. The final test data is obtained after being processed by the host computer software. In this embodiment, the host computer software can be existing vector network analysis software. This software is not the innovative content of the present utility model and will not be described in detail.

[0029] In one embodiment of the present invention, Figure 2 As shown, if multi-port vector network analysis is required, multiple devices can be inserted into the PXIe chassis according to the required number of ports, with one device acting as the master module and the next-level device acting as a slave module. The slave module at this level acts as the master module at the next level, and the next level acts as a new slave module, and so on, forming a master-slave cascade control mode. The panel of this embodiment has a local oscillator output port and a local oscillator input port, a clock output port and a clock input port, and a control output port and a control input port. The local oscillator output port of the master module is connected to the local oscillator input port of the next-level slave module, the clock output port of the master module is connected to the clock input port of the next-level slave module, and the control output port of the master module is connected to the control input port of the next-level slave module to achieve signal synchronization between the different devices. This combination forms a multi-port vector network analyzer, miniaturizing the system and facilitating flexible configuration based on user needs, reducing costs.

[0030] In summary, the present invention implements a 2-port vector network analysis function in a single PXIe slot. Multiple devices can be configured to achieve true multi-port measurement, eliminating the need to expand the number of ports of the vector network analyzer through an external switch matrix. This reduces the measurement time cost and avoids performance degradation.

Claims

1. A vector network analysis device based on a PXIe interface, characterized in that: The device comprises a first signal generating unit and a second signal generating unit, wherein the output end of the first signal generating unit is connected to the input end of the switch unit; the two output ends of the switch unit are correspondingly connected to the input end of the first directional coupler and the input end of the second directional coupler; the through output end of the first directional coupler is connected to the first test port, and the two coupled output ends of the first directional coupler are connected to the first input end of the receiving frequency conversion channel unit; the through output end of the second directional coupler is connected to the second test port, and the two coupled output ends of the second directional coupler are connected to the second input end of the receiving frequency conversion channel unit; The output end of the second signal generating unit is connected to the local oscillator signal input end of the receiving frequency conversion channel unit; The output end of the receiving frequency conversion channel unit is connected to the analog-to-digital conversion unit; the receiving frequency conversion channel unit, the analog-to-digital conversion unit, the first signal generating unit and the second signal generating unit are respectively connected to the FPGA chip; the FPGA chip is connected to the host computer through the PXIe interface.

2. A vector network analysis device based on a PXIe interface according to claim 1, characterized in that: The receiving frequency conversion channel unit includes two groups of receiving channels, each group of receiving channels includes a reference signal receiver and a measurement signal receiver; the reference signal receiver and the measurement signal receiver in the same group of receiving channels are correspondingly connected to the two coupled output ends of the first directional coupler; the reference signal receiver and the measurement signal receiver in the other group of receiving channels are correspondingly connected to the two coupled output ends of the second directional coupler.

3. The vector network analysis device based on the PXIe interface according to claim 1, characterized in that: The input end of the second signal generating unit is connected to the local oscillator input port, and the output end of the second signal generating unit is connected to the local oscillator output port for connecting to the local oscillator input port of the second signal generating unit in other vector network analysis devices based on the PXIe interface.

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