Multi-impedance coexisting non-equal-interval array PCB framework
By using a non-equal spacing array method with multiple impedance coexistence in PCB design, the line width and via position are adjusted, and the problem of low multi-impedance wiring efficiency in the existing technology is solved, efficient signal transmission and stacking consistency is achieved, and signal requirements such as DDR4 are met.
Patent Information
- Application Number
- CN202422374086.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2034-09-27
AI Technical Summary
When designing PCB layouts, it is difficult for the prior art to achieve multiple impedance coexistence without increasing the stacking structure and stacking number, resulting in waste of space and low wiring efficiency, and cannot meet the signal transmission requirements of high reliability and high performance, especially for signals with strict impedance matching such as DDR4.
A non-equal pitch array PCB design method with multiple impedances coexisting, is adopted to adjust the line width and via position, combine differential pairs and single-ended wiring to achieve mixed wiring of equal pitch and non-equal pitch arrays to meet the matching requirements of different impedances.
Without changing the stacking structure and stacking number, multi-impedance wiring is realized, wiring efficiency is improved, the consistency of stacking design is ensured, cost and resource waste are avoided, and signal transmission requirements of high reliability and high performance are met.
Smart Images
Figure CN223246769U_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of digital signal processing, and in particular relates to a PCB architecture with a non-equidistant array of multiple impedances. Background Art
[0002] PCB layout, a crucial step in integrated circuit design, printed circuit board design, and digital circuit implementation, plays a crucial role in the functionality and performance of circuits and products. Layout methods and techniques, such as stackup, trace width, and trace spacing, directly impact circuit signal integrity, affecting product reliability and electromagnetic compatibility, as reflected in key metrics such as signal speed, bit error rate, eye diagram, and jitter.
[0003] Generally speaking, according to transmission line theory and measured results, the impedance matching requirement for single-ended signals in the digital circuit field is 50Ω, and the impedance matching requirement for differential signals is 100Ω. These two parameters have relatively good transmission effects for most low-speed digital signals and high-speed signals with low requirements, such as RS485 and AURORA. However, for signals with strict impedance matching requirements, such as DDR4, they cannot meet the requirements of relevant standards and cannot achieve the speed and signal indicators of integrated circuit design. Therefore, it is necessary to improve the wiring method to achieve the high reliability and high performance requirements of digital circuits.
[0004] For digital signal arrays with multiple impedances, layout adjustments of trace width and stacking are necessary to meet impedance matching requirements. Conventionally, evenly spaced array routing can be achieved by adjusting the copper thickness or material of the stacking layers. However, this also introduces issues such as varying printed circuit board thickness and limited space for single-impedance signal lines. To address these issues, the present invention proposes a PCB design method for non-evenly spaced arrays with multiple impedances. This method achieves this multi-impedance routing effect by optimizing the signal array's routing spacing. Summary of the Invention
[0005] To solve the above problems, the present application provides a PCB architecture with a non-uniformly spaced array of multiple impedances, including:
[0006] Differential pair routing vs. single-ended routing,
[0007] Differential pair routing includes:
[0008] a first circuit hole, a first via hole connected to the first circuit hole, and a first line connected to the first via hole;
[0009] a second circuit hole, a second via hole connected to the second circuit hole, and a second line connected to the second via hole;
[0010] Single-ended wiring includes:
[0011] a third circuit hole, a third via hole connected to the third circuit hole, and a third line connected to the third via hole;
[0012] The first line, the second line and the third line are parallel to each other, and the second line is located between the first line and the third line;
[0013] The distance between the first line and the second line is a first set width, and the distance between the second line and the third line is a second set width.
[0014] When the distance between the first circuit hole and the second circuit hole is not equal to the first set width, the second via hole and the second circuit are offset so that the distance between the first circuit and the second circuit always maintains the first set width.
[0015] Preferably, the first circuit hole, the second circuit hole and the third circuit hole are located on the same straight line.
[0016] Preferably, the first via hole, the second via hole and the third via hole are located on the same straight line.
[0017] Preferably, the method includes: when the offset distance between the second circuit and the third circuit is smaller than the second set width, offsetting the third via and the third circuit so that the distance between the second circuit and the third circuit always maintains the second set width.
[0018] Preferably, the differential pair wiring is not included on both sides.
[0019] Preferably, the first line, the second line, and the third line have the same line width.
[0020] Preferably, the second set width is not less than three times the line width.
[0021] Advantages of this application include: A PCB design method for multi-impedance, non-uniformly spaced arrays can accomplish multi-impedance routing requirements without changing the stacking structure or number of layers. This ensures consistent stacking design, avoids the cost, size, and resource utilization issues associated with increasing the number of layers, and improves routing efficiency. This method is highly beneficial for PCB design and manufacturing.
[0022] The present invention can be applied to the field of PCB design and manufacturing, especially the field of impedance matching and layout design of digital signal processing circuits. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] Figure 1 The present invention is a differential pair wiring diagram of a PCB design method for a non-equidistant array with multiple impedances.
[0024] Figure 2The present invention provides a signal group wiring diagram for a PCB design method for a non-equidistant array with multiple impedances.
[0025] Figure 3 The present invention is applied to a certain DDR4 integrated circuit. DETAILED DESCRIPTION
[0026] To make the technical solution and its advantages of the present application clearer, the technical solution of the present application will be described in further detail below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only some embodiments of the present application and are only used to explain the present application, not to limit the present application. It should be noted that, for ease of description, only the parts related to the present application are shown in the accompanying drawings, and other related parts can refer to the general design. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other to obtain new embodiments.
[0027] This application takes the single-ended signal matching impedance of 50Ω and the differential signal impedance matching of 100Ω as the benchmark. Under the specified minimum line width constraint, by increasing or decreasing the line width and shifting the via position, the wiring effect of multiple impedances coexisting and equal-spaced and non-equal-spaced arrays can be achieved.
[0028] The single-ended signal matching impedance of 50Ω and the differential signal matching impedance of 100Ω are based on the unified stacking of the entire PCB layout, which stipulates the stacking board, copper thickness, line width, and line spacing indicators;
[0029] The minimum line width constraint is determined based on a comprehensive evaluation of matching impedance, line current, and production manufacturing conditions;
[0030] The increase or decrease of the line width is that when the single-ended matching impedance is greater than 50Ω and the differential matching impedance is greater than 100Ω, the line width wiring needs to be reduced; when the single-ended matching impedance is less than 50Ω and the differential matching impedance is less than 100Ω, the line width wiring needs to be increased;
[0031] The position of the via holes is shifted to the right when the line width needs to be increased and the via spacing needs to be increased. When the line width needs to be reduced, the via spacing needs to be reduced and the via holes are shifted to the left.
[0032] The equi-spaced and non-equi-spaced arrays are composed of a pair of differential signals and a single-ended signal as a signal group. When the impedance matching requirement is 50 / 100Ω, the line spacing within the signal group is two equidistant lines. When the impedance matching is not 50 / 100Ω, the line spacing within the signal group is two unequal lines. At this time, the differential line spacing is kept unchanged and the single-ended line spacing is reduced. If the differential line width is reduced, the single-ended line spacing is increased, thereby ensuring that the PCB design of the non-equidistant array is completed under the condition that the bus spacing remains unchanged.
[0033] In order to describe the present invention in more detail, the technical solution of the present invention is described in detail below with reference to the accompanying drawings and specific implementation methods.
[0034] refer to Figure 1 A differential pair routing diagram shows a PCB design method for unequally spaced arrays with multiple impedances. In this example, the matching impedance requirement is 76Ω. Based on a 100Ω reference, the line width needs to be increased, meaning L1 > L0. To ensure the line spacing remains unchanged, the vias need to be shifted right, meaning y2 > y1 while keeping x1 unchanged.
[0035] refer to Figure 2 A PCB design method for non-uniformly spaced arrays with multiple impedances. Signal group routing diagram. In this example, the matching impedance requirement is 39 / 76Ω. The signal group consists of a differential pair and a single-ended signal. When the impedance is matched at 50 / 100Ω, the signal array routing consists of two equally spaced lines with a spacing of x1. When the impedance is matched at 39 / 76Ω, the differential signal line width is increased, while the differential line spacing remains unchanged (x1). At the same time, the signal group spacing remains unchanged (y). In this case, the single-ended line spacing is reduced (x2).
[0036] refer to Figure 3 The present invention is applied to a certain DDR4 integrated circuit and Table 1 shows certain DDR4 wiring requirements: single-ended impedance matching is 39Ω, line width is 4mil, differential impedance matching is 76Ω, line width is 6mil, the maximum number of vias is 2, and PCB design is completed in the form of L0+L1+L0. The line width of the L1 segment needs to be increased, and the vias are shifted to the right. In the scenario where multiple impedances coexist in the same stack, the DDR4 signal group is designed in a non-uniform spacing manner.
[0037] Table 1 DDR4 wiring requirements
[0038] parameter L0 L1 unit Single-ended impedance 50±10％ 39±10％ Ω Differential impedance 86±10％ 76±10％ Ω Line Width 4.0 6.0 mil Maximum number of PCB vias 2 2
[0039] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.
Claims
1. A PCB architecture with a non-uniformly spaced array of multiple impedances, characterized in that: include: Differential pair routing vs. single-ended routing, Differential pair routing includes: a first circuit hole, a first via hole connected to the first circuit hole, and a first line connected to the first via hole; a second circuit hole, a second via hole connected to the second circuit hole, and a second line connected to the second via hole; Single-ended wiring includes: a third circuit hole, a third via hole connected to the third circuit hole, and a third line connected to the third via hole; The first line, the second line and the third line are parallel to each other, and the second line is located between the first line and the third line; The distance between the first line and the second line is a first set width, and the distance between the second line and the third line is a second set width. When the distance between the first circuit hole and the second circuit hole is not equal to the first set width, the second via hole and the second circuit are offset so that the distance between the first circuit and the second circuit always maintains the first set width.
2. The PCB architecture of the multi-impedance non-uniformly spaced array according to claim 1, wherein: include: The first circuit hole, the second circuit hole and the third circuit hole are located on the same straight line.
3. The PCB architecture of the multi-impedance non-uniformly spaced array according to claim 1, wherein: include: The first via hole, the second via hole and the third via hole are located on the same straight line.
4. The PCB architecture of the multi-impedance coexisting unequally spaced array according to claim 1, wherein: include: When the offset distance between the second circuit and the third circuit is smaller than the second set width, the third via and the third circuit are offset so that the distance between the second circuit and the third circuit always maintains the second set width.
5. The PCB structure of the multi-impedance non-uniformly spaced array according to claim 1, wherein: include: Differential pair routing is not included on both sides of the differential pair routing.
6. The PCB structure of the multi-impedance coexisting non-equidistant array according to claim 1, wherein: The first line, the second line, and the third line have the same line width.
7. The PCB structure of the multi-impedance coexisting non-equidistant array according to claim 1, wherein: The second set width is not less than three times the line width.