Signal shaping module, communication architecture and electronic equipment

Abstract

The utility model provides a signal shaping module, a communication architecture and electronic equipment. The signal shaping module comprises a level judging device, a switching signal generator and a trigger, the input end of the level judging device serves as the input end of the signal shaping module and is used for accessing a bus signal; the first output end of the level judging device is connected to the first input end of the trigger, the second output end of the level judging device is connected to the input end of the switching signal generator, and the output end of the switching signal generator is connected to the second input end of the trigger; the output end of the trigger serves as the output end of the signal shaping module and is used for outputting a shaping signal corresponding to a bus signal, phase jitter of the signal can be eliminated, and a signal with a standard bit width is output.

Description

Technical Field

[0001] The present application relates to the technical field of electronic equipment, and in particular to a signal shaping module, a communication architecture, and an electronic device. Background Art

[0002] A signal originates from the transmitter, travels through the communication channel, and reaches the receiver. During this transmission process, signal distortion may occur, affecting the receiver's ability to accurately interpret the signal. Numerous factors affect the quality of the signal received by the receiver, including transmission rate, electromagnetic interference, and channel quality. The more severe the signal distortion, the higher the bit error rate (BER), and the greater the impact on communication performance.

[0003] How to repair the distorted signal to ensure good communication performance has become a difficult problem that technicians in this field are concerned about. Utility Model Content

[0004] The purpose of this application is to provide a signal shaping module, a communication architecture and an electronic device to at least partially improve the above-mentioned problems.

[0005] In order to achieve the above objectives, the technical solutions adopted in the embodiments of the present application are as follows:

[0006] In a first aspect, an embodiment of the present application provides a signal shaping module, which includes: a level judge, a switch signal generator and a trigger; the input end of the level judge serves as the input end of the signal shaping module, and is used to access the bus signal; the first output end of the level judge is connected to the first input end of the trigger, the second output end of the level judge is connected to the input end of the switch signal generator, and the output end of the switch signal generator is connected to the second input end of the trigger; the output end of the trigger serves as the output end of the signal shaping module, and is used to output the shaped signal corresponding to the bus signal.

[0007] It can eliminate the phase jitter of the signal and output the signal with standard bit width, thus preventing the external bus from affecting the TX signal bit time deviation of the CPU.

[0008] Optionally, the level judge is used to output a high-level logic signal when the level of the bus signal is higher than a preset level threshold, and to output a low-level logic signal when the level of the bus signal is lower than the preset level threshold; the level judge is also used to delay sending a start signal to the switch signal generator for a preset period of time when the level of the bus signal is higher than the preset level threshold for the first time; the switch signal generator is used to output a switch signal to the trigger after receiving the start signal, wherein the period of the switch signal is the same as the standard period of the bus signal; the trigger is used to output a shaped signal corresponding to the bus signal based on the logic signal output by the level judge and the switch signal output by the switch signal generator.

[0009] Optionally, the trigger is used to sample the logic signal output by the level judger on the rising edge of the switching signal, and if the sampling result is a high level, a high-level shaped signal is output; the trigger is also used to sample the logic signal output by the level judger on the falling edge of the switching signal, and if the sampling result is a low level, a low-level shaped signal is output.

[0010] Optionally, the preset duration is less than or equal to twice the phase jitter delay of the bus signal.

[0011] In the second aspect, an embodiment of the present application provides a communication architecture, which includes a CPU, a physical layer port and a first signal shaping module, wherein the physical layer port includes a physical layer receiving end and a physical layer transmitting end, and the first signal shaping module is the above-mentioned signal shaping module; the transmitting end of the CPU is connected to the physical layer receiving end through a transmitting bus, and the receiving end of the CPU is connected to the physical layer transmitting end through a receiving bus, and a synchronization mechanism is implemented between the transmitting end of the CPU and the receiving end of the CPU; the first signal shaping module is deployed on the transmitting bus or the receiving bus.

[0012] Optionally, both the sending bus and the receiving bus are CAN buses.

[0013] Optionally, the first signal shaping module is deployed on the transmitting bus; the input end of the first signal shaping module is connected to the transmitting end of the CPU through the transmitting bus, and the output end of the first signal shaping module is connected to the physical layer receiving end through the transmitting bus.

[0014] Optionally, the first signal shaping module is deployed on the receiving bus; the input end of the first signal shaping module is connected to the physical layer transmitting end through the receiving bus, and the output end of the first signal shaping module is connected to the receiving end of the CPU through the receiving bus.

[0015] Optionally, the communication architecture also includes a second signal shaping module, wherein the second signal shaping module is the above-mentioned signal shaping module; the first signal shaping module is deployed on the transmitting bus, and the second signal shaping module is deployed on the receiving bus; the input end of the first signal shaping module is connected to the transmitting end of the CPU through the transmitting bus, and the output end of the first signal shaping module is connected to the physical layer receiving end through the transmitting bus; the input end of the second signal shaping module is connected to the physical layer transmitting end through the receiving bus, and the output end of the second signal shaping module is connected to the receiving end of the CPU through the receiving bus.

[0016] In a third aspect, an embodiment of the present application provides an electronic device comprising the above-mentioned communication architecture.

[0017] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the following embodiments are given in conjunction with the accompanying drawings for detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 This is one of the communication architecture diagrams provided in the embodiments of the present application.

[0020] Figure 2 A waveform diagram of an ideal situation provided in an embodiment of the present application.

[0021] Figure 3 A waveform diagram of an embodiment of the present application when no synchronization mechanism is adopted.

[0022] Figure 4 A waveform diagram of the embodiment of the present application using a synchronization mechanism.

[0023] Figure 5 This is a schematic diagram of the structure of the signal shaping module provided in an embodiment of the present application.

[0024] Figure 6 A schematic diagram of signal waveform changes provided in an embodiment of the present application.

[0025] Figure 7 This is the second communication architecture diagram provided for an embodiment of the present application.

[0026] Figure 8This is the third communication architecture diagram provided for an embodiment of the present application.

[0027] Figure 9 This is the fourth communication architecture diagram provided for an embodiment of the present application.

[0028] In the figure: 10-CPU; 20-physical layer port; 30-signal shaping module; 31-level judger; 32-switch signal generator; 33-trigger. DETAILED DESCRIPTION

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Generally, the components of the embodiments of the present application described and shown in the drawings herein can be arranged and designed in various different configurations.

[0030] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present application without creative work are within the scope of protection of the present application.

[0031] It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and should not be understood as indicating or implying relative importance.

[0032] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0033] In the description of this application, it should be noted that the terms "upper", "lower", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limitations on this application.

[0034] It should also be noted that, in the description of this application, unless otherwise expressly specified or limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, or electrical connections; direct connections, indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0035] The following describes some embodiments of the present application in detail with reference to the accompanying drawings. In the absence of conflict, the following embodiments and features therein may be combined with each other.

[0036] This application embodiment provides a communication architecture, please refer to Figure 1 , Figure 1 One of the communication architecture diagrams provided for the embodiments of the present application. The communication architecture includes a CPU 10 and a physical layer port 20, wherein the physical layer port 20 includes a physical layer receiving end and a physical layer transmitting end. In the embodiments of the present application, TX represents the transmitting end of the corresponding component, and RX represents the receiving end of the corresponding component, which will not be repeated hereafter. The transmitting end of the CPU 10 is connected to the physical layer receiving end through a transmitting bus (also called a transmitting channel), and the receiving end of the CPU 10 is connected to the physical layer transmitting end through a receiving bus (also called a receiving channel). The CPU 10 and the physical layer port 20 exchange data through the transmitting bus and the receiving bus.

[0037] In the embodiment of the present application, the full English name of the central processing unit is Central Processing Unit, referred to as CPU; the physical layer port is also called the port physical layer, the full English name is Physical, referred to as PHY.

[0038] Please refer to Figure 2 、 Figure 3 as well as Figure 4 , Figure 2 This is a waveform diagram of an ideal case provided in the embodiment of the present application. Figure 3 This is a waveform diagram provided in an embodiment of the present application when no synchronization mechanism is adopted. Figure 4 A waveform diagram of the embodiment of the present application using a synchronization mechanism.

[0039] like Figure 2 As shown, under ideal conditions, the data waveforms on the transmit bus and the data waveforms on the receive bus are both standard waveforms, i.e., waveforms with consistent pulse widths and aligned phases. In the embodiments of the present application, a standard pulse width of 2µs is used as an example for illustration, but this is not intended to be limiting. The standard pulse width can be adjusted according to the protocol.

[0040] However, in actual practice, the receiving bus is often subject to external interference, resulting in signal distortion. Figure 3 As shown, the data waveform on the receiving bus is distorted. The pulse width of the data waveform on the receiving bus cannot be maintained at the standard pulse width, but fluctuates, for example, 1.8us or 2.1us.

[0041] Furthermore, a synchronization mechanism is usually implemented between the sending end of CPU10 and the receiving end of CPU10. The abnormality of the data waveform on the receiving bus will affect the data generated by CPU10 through the sending bus. Figure 4 As shown, under the influence of the abnormal data waveform on the receiving bus, the data waveform on the transmitting bus is also distorted, causing a large deviation from the ideal standard waveform, affecting the communication result.

[0042] In order to overcome the above problems, an embodiment of the present application provides a signal shaping module that can eliminate the phase jitter of the signal, output a signal with a standard bit width, and avoid the external bus affecting the TX signal bit time deviation of the CPU.

[0043] Please refer to Figure 5 , Figure 5 The signal shaping module 30 includes a level determiner 31 , a switch signal generator 32 and a trigger 33 .

[0044] The input end of the level judger 31 serves as the input end of the signal shaping module 30 and is used to access the bus signal.

[0045] A first output of the level determiner 31 is connected to a first input of the trigger 33 . A second output of the level determiner 31 is connected to an input of the switch signal generator 32 . An output of the switch signal generator 32 is connected to a second input of the trigger 33 .

[0046] The output end of the trigger 33 serves as the output end of the signal shaping module 30 , and is used to output a shaped signal corresponding to the bus signal, wherein the shaped signal is a signal of standard bit width.

[0047] The embodiment of the present application provides a signal shaping module that can eliminate phase jitter of a signal and output a signal with a standard bit width.

[0048] Please refer to Figure 6 , Figure 6 Schematic diagram of signal waveform changes provided in an embodiment of the present application. The original signal on the bus is an ideal standard waveform, but under the influence of interference factors, the bus signal is distorted and no longer has the ideal standard waveform. In order to restore the signal on the bus to the ideal standard waveform, it needs to be shaped. The specific process is as follows.

[0049] The level determiner 31 is configured to output a high-level logic signal when the level of the bus signal is higher than a preset level threshold, and output a low-level logic signal when the level of the bus signal is lower than the preset level threshold.

[0050] The preset level threshold is greater than the high-low level boundary of the bus signal. For example, if the preset level threshold is 1.3V and the high-low level boundary is 1V, when the bus signal level is higher than 1V, it is considered to be a high level, and the level determiner 31 needs to output a high-level logic signal when the bus signal level is higher than 1.3V.

[0051] When the level of the bus signal is equal to the preset level threshold, the output logic signal remains in the current state.

[0052] Therefore, the phase of the logic signal output by the level judger 31 cannot be aligned with the original signal, and a significant change occurs. As shown in the figure, the rising edges of the two are separated by a time length of t1.

[0053] The level determiner 31 is further configured to delay sending a start signal to the switch signal generator 32 for a preset time period when the level of the bus signal is higher than a preset level threshold for the first time.

[0054] like Figure 6 As shown, after the first rising edge of the logic signal output by the level determiner 31 occurs, the level determiner 31 delays for a preset time duration t2 and sends a start signal to the switch signal generator 32 .

[0055] The switch signal generator 32 is used to output a switch signal to the trigger 33 after receiving the start signal, wherein the period of the switch signal is the same as the standard period of the bus signal, and the standard pulse widths of the two are consistent.

[0056] It will be appreciated that the standard switch signal is consistent with the bus baud rate.

[0057] The trigger 33 is used to output a shaped signal corresponding to the bus signal according to the logic signal output by the level determiner 31 and the switch signal output by the switch signal generator 32 .

[0058] The trigger 33 is used to sample the logic signal output by the level judge 31 at the rising edge of the switch signal. If the sampling result is a high level, a high-level shaped signal is output; if the sampling result is a low level, a low-level shaped signal is output.

[0059] The trigger 33 is also used to sample the logic signal output by the level judge 31 at the falling edge of the switch signal. If the sampling result is a high level, a high-level shaped signal is output; if the sampling result is a low level, a low-level shaped signal is output.

[0060] When triggered by the switch signal, the trigger 33 samples the logic signal output by the level determiner 31 , thereby ensuring that the shaped signal outputted by the trigger 33 is consistent with the original signal in multiple dimensions such as phase and pulse width.

[0061] Optionally, the preset duration is less than or equal to twice the phase jitter delay of the bus signal.

[0062] This application also provides a communication architecture, please refer to Figure 7 and Figure 8 , Figure 7 The second communication architecture diagram provided in the embodiment of the present application is as follows: Figure 8 This is the third communication architecture diagram provided for an embodiment of the present application.

[0063] The communication architecture includes a CPU 10 , a physical layer port 20 and a first signal shaping module, wherein the physical layer port 20 includes a physical layer receiving end and a physical layer transmitting end, and the first signal shaping module is the above-mentioned signal shaping module 30 .

[0064] The sending end of the CPU 10 is connected to the receiving end of the physical layer through a sending bus, and the receiving end of the CPU 10 is connected to the sending end of the physical layer through a receiving bus, and a synchronization mechanism is implemented between the sending end of the CPU 10 and the receiving end of the CPU 10.

[0065] The first signal shaping module is deployed on the sending bus or the receiving bus.

[0066] Optionally, the transmitting bus and the receiving bus are both CAN buses, where the full name of the Controller Area Network bus is Controller Area Network, or CAN for short.

[0067] Please refer to Figure 7 , the first signal shaping module is deployed on the sending bus; the input end of the first signal shaping module is connected to the sending end of CPU10 through the sending bus, and the output end of the first signal shaping module is connected to the physical layer receiving end through the sending bus.

[0068] Please refer to Figure 8, the first signal shaping module is deployed on the receiving bus; the input end of the first signal shaping module is connected to the physical layer transmitting end through the receiving bus, and the output end of the first signal shaping module is connected to the receiving end of CPU10 through the receiving bus.

[0069] Please refer to Figure 9 , Figure 9 This is a fourth schematic diagram of a communication architecture provided in an embodiment of the present application. The communication architecture further includes a second signal shaping module, wherein the second signal shaping module is the above-mentioned signal shaping module.

[0070] The first signal shaping module is deployed on the sending bus, and the second signal shaping module is deployed on the receiving bus.

[0071] The input end of the first signal shaping module is connected to the transmitting end of the CPU 10 through the transmitting bus, and the output end of the first signal shaping module is connected to the receiving end of the physical layer through the transmitting bus.

[0072] The input end of the second signal shaping module is connected to the physical layer transmitting end through the receiving bus, and the output end of the second signal shaping module is connected to the receiving end of the CPU 10 through the receiving bus.

[0073] In the embodiment of the present application, the preset duration (delay duration) corresponding to the level judge 31 and the parameters of the switching signal of the switching signal generator 32 (including frequency, period, phase and duty cycle, etc.) can be set by the host computer.

[0074] The embodiment of the present application further provides an electronic device including the above-mentioned communication architecture. The electronic device may be a mobile phone, a computer, a server, and the like.

[0075] In summary, the embodiments of the present application provide a signal shaping module, a communication architecture and an electronic device, wherein the signal shaping module includes: a level judge, a switching signal generator and a trigger; the input end of the level judge serves as the input end of the signal shaping module, and is used to access the bus signal; the first output end of the level judge is connected to the first input end of the trigger, the second output end of the level judge is connected to the input end of the switching signal generator, and the output end of the switching signal generator is connected to the second input end of the trigger; the output end of the trigger serves as the output end of the signal shaping module, and is used to output a shaped signal corresponding to the bus signal, which can eliminate the phase jitter of the signal and output a signal with a standard bit width.

[0076] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application.

[0077] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above and that the present application can be implemented in other specific forms without departing from the spirit or essential characteristics of the present application. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the present application is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

Claims

1. A signal shaping module, characterized in that: The signal shaping module includes: a level judge, a switch signal generator and a trigger; The input end of the level judger serves as the input end of the signal shaping module and is used to access the bus signal; The first output terminal of the level judger is connected to the first input terminal of the trigger, the second output terminal of the level judger is connected to the input terminal of the switch signal generator, and the output terminal of the switch signal generator is connected to the second input terminal of the trigger; The output end of the trigger serves as the output end of the signal shaping module, and is used to output a shaped signal corresponding to the bus signal.

2. The signal shaping module according to claim 1, wherein: The level determiner is configured to output a high-level logic signal when the level of the bus signal is higher than a preset level threshold, and output a low-level logic signal when the level of the bus signal is lower than the preset level threshold; The level determiner is further configured to delay sending a start signal to the switch signal generator for a preset time period when the level of the bus signal is higher than the preset level threshold for the first time; The switch signal generator is configured to output a switch signal to the trigger after receiving the start signal, wherein a period of the switch signal is the same as a standard period of the bus signal; The trigger is used to output a shaped signal corresponding to the bus signal according to the logic signal output by the level judger and the switch signal output by the switch signal generator.

3. The signal shaping module according to claim 2, wherein: The trigger is used to sample the logic signal output by the level judgement device at the rising edge of the switch signal, and output a high-level shaping signal if the sampling result is a high level; The trigger is further configured to sample the logic signal output by the level judge at the falling edge of the switch signal, and output a low-level shaped signal if the sampling result is a low level.

4. The signal shaping module according to claim 2, wherein: The preset duration is less than or equal to twice the phase jitter delay of the bus signal.

5. A communication architecture, characterized in that: The communication architecture includes a CPU, a physical layer port, and a first signal shaping module, wherein the physical layer port includes a physical layer receiving end and a physical layer transmitting end, and the first signal shaping module is the signal shaping module according to any one of claims 1 to 4; The transmitting end of the CPU is connected to the receiving end of the physical layer via a transmitting bus, and the receiving end of the CPU is connected to the transmitting end of the physical layer via a receiving bus, and a synchronization mechanism is implemented between the transmitting end of the CPU and the receiving end of the CPU; The first signal shaping module is deployed on the sending bus or the receiving bus.

6. The communication architecture according to claim 5, wherein: The sending bus and the receiving bus are both CAN buses.

7. The communication architecture according to claim 5, wherein: The first signal shaping module is deployed on the sending bus; The input end of the first signal shaping module is connected to the transmitting end of the CPU through a transmitting bus, and the output end of the first signal shaping module is connected to the physical layer receiving end through a transmitting bus.

8. The communication architecture according to claim 5, wherein: The first signal shaping module is deployed on the receiving bus; The input end of the first signal shaping module is connected to the physical layer transmitting end through a receiving bus, and the output end of the first signal shaping module is connected to the receiving end of the CPU through a receiving bus.

9. The communication architecture according to claim 5, wherein: The communication architecture further includes a second signal shaping module, wherein the second signal shaping module is the signal shaping module according to any one of claims 1 to 4; The first signal shaping module is deployed on the sending bus, and the second signal shaping module is deployed on the receiving bus; The input end of the first signal shaping module is connected to the transmitting end of the CPU through a transmitting bus, and the output end of the first signal shaping module is connected to the receiving end of the physical layer through a transmitting bus; The input end of the second signal shaping module is connected to the physical layer transmitting end through a receiving bus, and the output end of the second signal shaping module is connected to the receiving end of the CPU through a receiving bus.

10. An electronic device, characterized in that: The communication architecture comprises any one of claims 5-9.

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