Semiconductor packaging structure

Abstract

Some embodiments of the present application provide a semiconductor package structure, comprising: a first substrate having a first through hole; a second substrate; the passive component is arranged between the first substrate and the second substrate, and an electrode is arranged at the end of the passive component; the welding flux covers the electrode; and a molding compound including an upper molding region disposed between the solder and between the passive component and the first substrate, in which the first via does not overlap the upper molding region of the molding compound in a vertical direction and is offset toward a direction away from the passive component. According to the invention, the first through hole is not overlapped with the upper molding area in the vertical direction, so that the problem of delamination between the passive assembly and the upper molding area is avoided.

Description

Technical Field

[0001] The present application relates to the technical field of power devices, and more specifically, to a semiconductor packaging structure. Background Art

[0002] In the 3D stacked package structure 10 where components such as passive components are connected to the upper and lower substrates, see Figures 1A to 1C , Figure 1A shows a cross-sectional view of a 3D stacked package structure 10, and Figure 1B A partial detailed view of the 3D stacked package structure 10 is shown, and Figure 1C It further shows Figure 1B Partial detail view of . Figures 1A to 1C As can be seen in the 3D stacked package structure 10, the component 13 is disposed between the upper substrate 12 and the lower substrate 11 and is sealed by a molding material 14 such as a molding compound, and the component 13 has an electrode 13e, and the electrode 13e is covered by a solder 16. It should be noted that Figure 1B and Figure 1C Only a portion of the solder 16 is shown. Figure 1B As shown, the upper molded area 14A above the component 13 and the lower molded area 14B below the component 13 are approximately trapezoidal in shape, and the through hole 15t is located on the same vertical line as the component 13, specifically, on the same vertical line as the upper molded area 14A and the lower molded area 14B. After subsequent furnace processing, the through hole 15t will generate corresponding stress, and the stress will be concentrated at the trapezoidal corner C (such as the corner formed by the solder 16 and the component 13), which can easily cause delamination P between the molding material 14 such as the molding compound and the component 13 such as the passive component, such as between the component 13 and the upper molded area 14A and the lower molded area 14B. This will cause the solder 16 such as tin to penetrate the delamination P area, causing functional failure or failure in subsequent reliability testing, thereby causing reliability issues. Furthermore, Figure 1D shows a scan of the 3D stacked package structure 10, and Figure 1E Shown Figure 1A and Figure 1D A scan of region A of the 3D stacked package structure 10 is shown. Figure 1D and Figure 1E It can be clearly seen in FIG. 1 that delamination P occurs between the component 13 and the lower molding area 14B.

[0003] To address the above-mentioned issues, existing technologies generally select the molding material 14, adjust process parameters (clamping force, transfer pressure, etc.), and control the amount of tin in SMT (surface mount technology). However, the improvement of the delamination P condition is limited. All experimental combinations have the phenomenon of delamination P, and for existing 5D / 3D integrated circuits (ICs), molding, substrates, modules, power integration, assembly processes, etc., samples with delamination P after CSA (current sense amplification) usually occur between the molding material 14 and the component 13.

[0004] In summary, the structural design of the upper substrate 12 and the lower substrate 11 causes the stress generated by the reflow process of the corresponding 3D stacked packaging structure 10 to be concentrated on the vertical contact surface between the molding material 14 and the solder 16 (and possible electrodes 13e), causing the delamination P problem. Utility Model Content

[0005] The phenomenon of delamination of the semiconductor package structure caused by the vertical stress on the solder can be solved by arranging the through holes in the substrate away from the upper and lower molding areas surrounded by the solder of the passive component.

[0006] Some embodiments of the present application provide a semiconductor packaging structure, comprising: a first substrate having a first through hole; a second substrate; a passive component arranged between the first substrate and the second substrate, the passive component having an electrode at an end thereof; a solder covering the electrode; and a molding compound comprising an upper molding area arranged between the solder and between the passive component and the first substrate, wherein the first through hole does not overlap with the upper molding area of ​​the molding compound in a vertical direction and is offset in a direction away from the passive component.

[0007] In some embodiments, the solder near the first substrate and the surface of the passive component have a first intersection, and the first through hole does not overlap with the first intersection in a vertical direction.

[0008] In some embodiments, the second substrate has a second through hole, wherein the solder near the second substrate has a second intersection with the surface of the passive component, and the second through hole does not overlap with the second intersection in a vertical direction and is offset in a direction away from the passive component.

[0009] In some embodiments, the first substrate further has a third through hole, and the third through hole vertically overlaps with the first through hole.

[0010] In some embodiments, the first through-hole vertically overlaps with the second through-hole.

[0011] In some embodiments, the first through-hole does not overlap with the passive component in the vertical direction and is disposed outside a lateral extent of the passive component.

[0012] In some embodiments, the second through hole does not overlap with the passive component in the vertical direction and is disposed outside the lateral extent of the passive component.

[0013] In some embodiments, the mold compound further encapsulates the passive components.

[0014] In some embodiments, the upper molding region has a first trapezoidal shape.

[0015] In some embodiments, sidewalls of the first trapezoidal shape are defined by corresponding solders.

[0016] In some embodiments, the first trapezoidal shape tapers in a direction toward the first substrate.

[0017] In some embodiments, the mold compound further includes a lower molding region disposed between the passive component and the second substrate, the lower molding region of the mold compound having a second trapezoidal shape.

[0018] In some embodiments, sidewalls of the second trapezoidal shape are defined by corresponding solders.

[0019] In some embodiments, the second trapezoidal shape tapers in a direction toward the second substrate.

[0020] In some embodiments, the passive component is a capacitive element.

[0021] In some embodiments, the first via is connected to a first metal wire on the corresponding solder.

[0022] In some embodiments, the first metal lines extend beyond the lateral extent of the corresponding solders.

[0023] In some embodiments, no gaps exist between the mold compound and the passive components.

[0024] Other embodiments of the present application provide a semiconductor packaging structure, comprising: a first substrate having a first through hole; a second substrate; a passive component arranged between the first substrate and the second substrate, the passive component having an electrode at an end thereof; a solder covering the electrode; and a molding compound filled between the first substrate and the second substrate and encapsulating the passive component, wherein the molding compound between the passive component and the first substrate and between the solder has a first trapezoidal shape, and the first through hole does not overlap with the first trapezoidal shape in a vertical direction and is offset in a direction away from the passive component.

[0025] In some embodiments, the first through-hole does not overlap with the passive component in the vertical direction and is disposed outside a lateral extent of the passive component.

[0026] In some embodiments, the second substrate has a second through hole, wherein the molding compound between the passive component and the second substrate has a second trapezoidal shape, and the second through hole does not overlap with the second trapezoidal shape in a vertical direction and is offset in a direction away from the passive component.

[0027] The present application prevents the first through hole from directly applying stress to the solder during or after annealing, thereby preventing subsequent delamination of the passive component from the upper molding area, by ensuring that the first through hole does not overlap with the upper molding area in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figures 1A to 1E The semiconductor packaging structure in the prior art is shown.

[0030] Figures 2 to 3 The semiconductor package structure of some embodiments of the present application is shown.

[0031] Figures 4A-1 to 4A-4 、 Figures 4B-1 to 4B-4 、 Figures 5A-1 to 5A-3 as well as Figure 5B-1 to Figure 5B-3 Test diagrams of semiconductor package structures in the prior art and semiconductor package structures in some embodiments of the present application are shown. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field fall within the scope of protection of this application. In addition, when "approximately", "about", "substantial", "basic" and the like are used to describe a numerical value or a numerical range, unless otherwise specified, the term is intended to cover a numerical value within ±10% of the described numerical value. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0033] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are in direct contact, and may also include an embodiment in which an additional component is formed between the first component and the second component so that the first component and the second component may not be in direct contact. Moreover, the present invention may repeatedly refer to numbers and / or letters in various examples. This repetition is merely for simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations discussed.

[0034] In order to alleviate the delamination phenomenon of the semiconductor package structure, some embodiments of the present application provide a semiconductor package structure 100 with better performance. Figure 2 The semiconductor package structure 100 includes: a first substrate 101 having a first through hole 101t; a second substrate 102; a passive component 103 disposed between the first substrate 101 and the second substrate 102, with an electrode 103e at the end of the passive component 103; and a solder 105 covering the electrode 103e. It should be noted that Figure 2Only a portion of the solder 105 is shown, and the overall structure of the semiconductor package structure 100 is similar to the 3D stacked package structure 10 shown in Figure 1, so that the solder 105 covers the corresponding electrode 103e. Further, the semiconductor package structure also includes a molding compound 104, and the molding compound 104 includes an upper molding area 104A arranged between the solder 105 and between the passive component 103 and the first substrate 101, wherein the first through hole 101t does not overlap with the upper molding area 104A of the molding compound 104 in the vertical direction D and is offset in the direction E1 away from the passive component. In the present application, by offsetting the first through hole 101t in the direction E1 and avoiding the upper molding area 104A, the stress of the first through hole 101t can be better dispersed, thereby avoiding delamination between the passive component 103 and the upper molding area 104A, and further avoiding the solder 105 such as tin from penetrating into the delamination. Further, in Figure 2 In the semiconductor package structure 100 shown, the solder 105 near the first substrate 101 has a first intersection n1 with the surface 103t of the passive component 103, and the first through hole 101t does not overlap with the first intersection n1 in the vertical direction D. In some embodiments, the upper molded area 104A has a first trapezoidal shape, and the sidewalls of the first trapezoidal shape are defined by the corresponding solder 105. Further, the first trapezoidal shape tapers in the direction D1 toward the first substrate 101, that is, in the direction D2, the first through hole 101t is not overlapped with the first intersection n1. Figure 2 In the cross-sectional view shown, the width of the first trapezoidal shape gradually decreases in the direction D1.

[0035] In some embodiments, the second substrate 102 has a second through hole 102t. In the embodiment of the present application, the solder 105 near the second substrate 102 has a second intersection n2 with the surface 103s of the passive component 103. The second through hole 102t does not overlap with the second intersection n2 in the vertical direction D and is offset in a direction E1 away from the passive component 103. It should be noted that the first intersection n1 and the second intersection n2 are not aligned with the passive component 103. Figure 2 When the left side is shown relative to the right side, the first through hole 101t and the second through hole 102t are offset toward the direction E2, that is, away from the passive component 103. Similarly, the mold compound 104 also includes a lower mold area 104B disposed between the passive component 103 and the second substrate 102 (and between the corresponding solder 105). The lower mold area 104B of the mold compound 104B has a second trapezoidal shape, and the sidewalls of the second trapezoidal shape are defined by the corresponding solder 105. Further, the second trapezoidal shape tapers in the direction D2 toward the second substrate 102, that is, in the direction D2. Figure 2 In the cross-sectional view shown, the width of the second trapezoidal shape gradually decreases in the direction D2.

[0036] Further Figure 2 As shown, the first substrate 101 further has a third through hole 101v, and the third through hole 101v vertically overlaps with the first through hole 101t, as shown in FIG. Figure 2 As shown, the third through hole 101v vertically overlaps the first through hole 101t, thereby forming a through hole 101vt of the first substrate 101. Further, the through hole 101t is offset from the upper mold area 104A of the mold compound 104 toward the direction E1. Furthermore, the first through hole 101t vertically overlaps the second through hole 102t.

[0037] Next, see Figure 3 , Figure 3 A semiconductor package structure 100' is shown. In this semiconductor package structure 100', the first through-via 101t does not overlap with the passive component 103 in the vertical direction D and is disposed outside the lateral extent of the passive component 103. This can further distribute the stress of the first through-via 101t and others, thereby preventing delamination between the passive component 103 and the upper molding region 104A. Similarly, the second through-via 102t does not overlap with the passive component 103 in the vertical direction D and is disposed outside the lateral extent of the passive component 103.

[0038] like Figure 2 As shown, the mold compound 104 further encapsulates the passive component 103, that is, the mold compound 104 further includes a mold portion 104C disposed around the passive component 103. In some embodiments, the passive component 103 is a capacitor element, and the electrode 103e is made of a metal such as copper.

[0039] See further Figure 2 , the first through hole 101t is connected to the first metal wire 101m1 on the corresponding solder 105. However, as Figure 2 As shown, the first substrate 101 further includes second metal wires 101m2, ..., and an nth metal wire 101mn, which can be connected via corresponding vias. In some embodiments, the first metal wire 101m1 extends beyond the lateral extent of the corresponding solder 105. Similarly, the second substrate 102 also includes metal wires 102m1 ... 102mn, etc., which are connected via corresponding vias, and the metal wire 102m1 closest to the solder 105 also extends beyond the lateral extent of the corresponding solder 105.

[0040] In the above-described embodiment, the mold compound 104 may include a molding compound, and the first substrate 101 and the second substrate 102 may include, but are not limited to, a printed circuit board, an interposer, etc. The first through-via 101 t , the second through-via 102 t , the third through-via 101 v , etc., and the first metal line 101 m 1 , the second metal line 101 m 2 , . . . , the nth metal line 101 m n , and the metal lines 102 m 1 . . . 102 m n , etc. include, but are not limited to, metals or metal alloys, such as copper, silver, gold, etc., or alloys thereof. In addition, the first through hole 101t, the second through hole 102t, the third through hole 101v, etc., as well as the first metal wire 101m1, the second metal wire 101m2,... and the nth metal wire 101mn, etc. are embedded in the dielectric layer 101L of the first substrate 101, and the metal wires 102m1...102mn are embedded in the dielectric layer 102L of the second substrate 102. The first dielectric layer 101L and the second dielectric layer 102L may include but are not limited to polyimide, imide, etc.

[0041] In the semiconductor package structure 100 / 100' provided herein, by offsetting the first through-hole 101t from the upper molding region 104A in a direction away from the passive component 103, delamination between the passive component 103 and the upper molding region 104A is avoided, and the intrusion of solder 105, such as tin, into the delamination is further avoided. Furthermore, in the semiconductor package structure 100 / 100' provided herein, no gap exists between the mold compound 104 (upper molding region 104A) and the passive component 103.

[0042] Continue to refer to Figure 2 Other embodiments of the present application provide a semiconductor packaging structure 100, including: a first substrate 101 having a first through hole 101t; a second substrate 102; a passive component 103, arranged between the first substrate 101 and the second substrate 102, having an electrode 103e at an end of the passive component 103; a solder 105 covering the electrode 103e; and a molding compound 104, filled between the first substrate 101 and the second substrate 102 and encapsulating the passive component 103, the molding compound 104 between the passive component 103 and the first substrate 101 and between the solder 105 (i.e., an upper molding area 104A) having a first trapezoidal shape, the first through hole 101t does not overlap with the first trapezoidal shape in the vertical direction D and is offset in a direction E1 away from the passive component.

[0043] In some embodiments, see Figure 3 , the first through hole 101 t does not overlap with the passive component 103 in the vertical direction D and is disposed outside the lateral extent of the passive component 103 .

[0044] Furthermore, the second substrate 102 has a second through hole 102t, wherein the mold compound 104 (i.e., the lower mold area 104B) between the passive component 103 and the second substrate 102 and the corresponding solder 105 has a second trapezoidal shape, and the second through hole 102t does not overlap with the second trapezoidal shape in the vertical direction D and is offset in a direction E1 away from the passive component 103.

[0045] In summary, by ensuring that the first through-hole 101t does not overlap with the upper molded area 104A in the vertical direction, the present application avoids the problem of the first through-hole 101t directly applying stress to the solder 105 during or after annealing, which could cause subsequent delamination between the passive component 103 and the upper molded area 104A. Furthermore, the method for forming the semiconductor package structure 100 is commonly used in the art and will not be described in detail here.

[0046] Different molding compounds G330, XQ9094, and P3W are used to Figure 1B The 3D stacked package structure 10 shown and Figure 2 The semiconductor package structure 100 shown is measured, and Figures 4A-1 to 4A-4 as well as Figures 4B-1 to 4B-4 Shown respectively Figure 1B The molding materials 14 of the 3D stacked package structure 10 shown are respectively G330, XQ9094, P3W, and P3W scans, and Figure 5A-1 to Figure 5A-2 as well as Figures 5B-1 to 5B-3 Shown respectively Figure 2 Scanning images of the molding compound 104 of the semiconductor package structure 100 using G330, XQ9094, and P3W are shown, and the following Table 1 shows corresponding measurement data.

[0047] Table 1 Figure 1B The 3D stacked package structure 10 shown and Figure 2 The semiconductor package structure 100 is shown in FIG.

[0048]

[0049] In the above Table 1, Pre-con means pre-conditioning test; DOE LEG1-DOE LEG3 mean experimental design 1 to experimental design 3; depth study means depth study; reliability lot means reliability; ton means torr; O / S means open circuit and short circuit (open-short); and G330, XQ9094 and P3W are models of molding compounds commonly used in the art and are clear models in the art.

[0050] Figures 4A-1 to 4B-4 Shown Figure 1BThe molding materials 14 of the 3D stacked package structure 10 shown are respectively G330, XQ9094, P3W, and P3W scans, and Figures 4B-1 to 4B-4 Shown respectively Figures 4A-1 to 4A-4 From the enlarged scanning diagram of the area G1 to the area G4, from Table 1 and Figures 4A-1 to 4B-4 It can be seen that all 3D stacked packaging structures 10 (i.e., structure 1) have a delamination P problem between the upper molding area 14A or the lower molding area 14B of the molding compound 14 and the corresponding component 13, and it can be seen from the depth study in the measurement of the 3D stacked packaging structure 10 that the delamination P phenomenon still exists when different molding compounds and chase depth settings are set.

[0051] Figures 5A-1 to 5B-3 Shown Figure 2 The mold compound 104 of the semiconductor package structure 100 shown in the figure is respectively made of G330, XQ9094, and P3W. Figures 5B-1 to 5B-3 Shown respectively Figures 5A-1 to 5A-3 From the above table 1 and Figures 5A-1 to 5B-3 It can be seen that Figure 2 In the illustrated semiconductor package structure 100 , no delamination problem occurs between the lower molding region 104B (or the upper molding region 104A (not shown)) and the component 103 , that is, no delamination P phenomenon occurs.

[0052] In summary, the present application alters the position of the first through-hole 101t in the first substrate 101 and / or the second through-hole 102t in the second substrate 102 (on a plane perpendicular to the passive component 103) to prevent stress generated after the overheating process during the reflow process from intersecting the solder 105 with the component 103 and the mold compound 104 at the intersections n1 / n2, thereby reducing the risk of delamination. Furthermore, the above results demonstrate that altering the position of the first through-hole 101t in the first substrate 101 and / or the second through-hole 102t in the second substrate 102 to offset the intersections n1 / n2 between the solder 105, the component 103, and the mold compound 104 reduces the delamination rate of the passive component 103 and the mold compound 104 to below 0.1%, thereby improving reliability and enabling the device to effectively pass reliability testing. Compared to the high delamination rate of the semiconductor package structure 10 in the prior art, the semiconductor package structure 100 (new structure) provided in the present application reduces the delamination risk and improves the product yield by avoiding the passive components 103 and the trapezoidal area of ​​the molding compound 104.

[0053] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first substrate having a first through hole; a second substrate; a passive component disposed between the first substrate and the second substrate, wherein an electrode is provided at an end of the passive component; Solder, covering the electrode; as well as a molding compound including an upper molding region disposed between the solder and between the passive component and the first substrate, The first through hole does not overlap with the upper molding area of ​​the molding compound in a vertical direction and is offset in a direction away from the passive component.

2. The semiconductor package structure according to claim 1, wherein: A first intersection is formed between the solder near the first substrate and a surface of the passive component, and the first through hole does not overlap with the first intersection in a vertical direction.

3. The semiconductor package structure according to claim 1, wherein: The second substrate has a second through hole, The solder near the second substrate has a second intersection with the surface of the passive component, and the second through hole does not overlap with the second intersection in a vertical direction and is offset in a direction away from the passive component.

4. The semiconductor package structure according to claim 1, wherein: The first substrate further has a third through hole, and the third through hole vertically overlaps with the first through hole.

5. The semiconductor package structure according to claim 3, wherein: The first through hole vertically overlaps with the second through hole.

6. The semiconductor package structure according to claim 1, wherein: The first through hole does not overlap with the passive component in the vertical direction and is disposed outside the lateral extent of the passive component.

7. The semiconductor package structure according to claim 3, wherein: The second through hole does not overlap with the passive component in the vertical direction and is disposed outside the lateral extent of the passive component.

8. The semiconductor package structure according to claim 1, wherein: The mold compound further encapsulates the passive components.

9. The semiconductor package structure according to claim 1, wherein: The upper molding area has a first trapezoidal shape.

10. The semiconductor package structure according to claim 9, wherein: The first trapezoidal shape tapers in a direction toward the first substrate.

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