Semiconductor packaging structure

Abstract

The utility model provides a semiconductor packaging structure, and the structure comprises a module which comprises a substrate and at least one first electronic element above the substrate. A first package covering the substrate and the at least one first electronic component; a second electronic component disposed adjacent to the module; and the second packaging body wraps the module and the second electronic element, and the bottom surface of the second packaging body is located between the upper surface and the lower surface of the substrate. The substrate and the at least one first electronic element are wrapped by the first packaging body, the module and the second electronic element are wrapped by the second packaging body, the module and the second electronic element do not need to be installed on the core substrate and then subjected to mold sealing, the module and the second electronic element can be directly arranged on the main board, and due to the fact that the thickness of the core substrate does not need to be increased, the manufacturing cost is reduced. Therefore, the original thickness of the first electronic component can be maintained, and the thickness of the whole semiconductor packaging structure is not increased.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a semiconductor packaging structure. Background Art

[0002] In existing module and SoC (System on a Chip) component manufacturing processes, the modules and SoC components are first mounted on a core substrate and then molded. After cutting, they are then mounted on a motherboard. This increases the thickness of the IC (Integrated Circuit) components in the module, making it impossible to maintain the original component thickness due to the increased thickness of the core substrate. This also increases the thickness of the entire semiconductor package structure. Utility Model Content

[0003] The present application proposes a semiconductor packaging structure.

[0004] In a first aspect, the present application provides a semiconductor packaging structure, comprising: a module, including a substrate and at least one first electronic component above the substrate; a first packaging body, covering the substrate and at least one first electronic component; a second electronic component, arranged adjacent to the module; a second packaging body, covering the module and the second electronic component, wherein the bottom surface of the second packaging body is located between the upper surface and the lower surface of the substrate.

[0005] In some optional embodiments, the bottom surface of the second package body has different levels.

[0006] In some optional embodiments, the second electronic component includes an electrical connection element, and the electrical connection element at least partially overlaps with the substrate in a horizontal direction.

[0007] In some optional embodiments, part of the electrical connection element is exposed through the second packaging body.

[0008] In some optional embodiments, the first package body includes first filling particles.

[0009] In some optional embodiments, the first filling particles disposed on the first sidewall and the second sidewall of the first package body have a truncated surface.

[0010] In some optional embodiments, the second encapsulation body includes second filling particles.

[0011] In some optional embodiments, the second filling particles disposed on the third sidewall of the second package body have no cross-section, and the second filling particles disposed on the fourth sidewall have cross-sections.

[0012] In some optional embodiments, a bottom surface of the second package body is lower than a bottom surface of the first package body.

[0013] In some optional embodiments, there is a gap between the second electronic component and the substrate.

[0014] In order to solve the problem that in the existing semiconductor packaging structure, the module and SoC components are first installed on the core substrate for the molding process, and then installed on the main board after cutting is completed, resulting in the thickness of the IC component being unable to maintain the original component thickness due to the increased thickness of the core substrate, and the thickness of the entire packaging structure being thicker, the present application proposes a semiconductor packaging structure, which uses a first packaging body to cover the substrate of the module and at least one electronic component above the substrate, and a second packaging body to cover the module and the second electronic component. There is no need to install the module and the second electronic component on the core substrate for molding. The present application can directly set the module and the second electronic component on the main board. Since there is no need to increase the thickness of the core substrate, the first electronic component can maintain its original thickness. At the same time, the thickness of the entire semiconductor packaging structure will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other features, objects and advantages of the present application will become more apparent upon reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0016] Figure 1 This is a schematic diagram of an existing semiconductor packaging structure;

[0017] Figure 2 It is a structural schematic diagram of placing an existing semiconductor packaging structure on a mainboard;

[0018] Figure 3 It is a simplified structural diagram of placing an existing semiconductor packaging structure on a motherboard;

[0019] Figure 4 is a structural schematic diagram of an embodiment 4a of a semiconductor package structure according to the present application;

[0020] Figure 5 FIG5 is a structural diagram of an embodiment 5a of the present application in which a removable structure is provided on the semiconductor package structure;

[0021] Figure 6 This is a structural diagram of an embodiment 6a of the present application in which the semiconductor package structure is placed on a mainboard;

[0022] Figure 7 is a simplified structural diagram of an embodiment 6a in which the semiconductor package structure of the present application is placed on a mainboard;

[0023] Figures 8-17It is a schematic diagram of the manufacturing steps of an embodiment 4a of the semiconductor packaging structure according to the present application.

[0024] Description of reference numerals / symbols:

[0025] 101-substrate; 102-first electronic component; 103-second electronic component; 104-package; 105-core substrate; 106-bottom pre-coated solder; 107-mainboard; 201-module; 202-first package; 203-second electronic component; 204 second package; 205-mainboard; 206-removable structure; 207-cutting knife; 2011-substrate; 2012-first electronic component; 2021-bottom surface of the first package; 2022-first side wall; 2023-second side wall; 2031-electrical connection element; 2041-bottom surface of the second package; 2042-third side wall; 2043-fourth side wall; 20111-upper surface of substrate; 20112-lower surface of substrate; 2061-metal frame. DETAILED DESCRIPTION

[0026] The following describes the specific embodiments of the present application in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present application and the technical effects produced by the present application through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0027] It should be readily understood that the meanings of “on,” “over,” and “over…” in this application should be interpreted in the broadest sense, such that “on” not only means “directly on something,” but also means “on something” including intermediate components or layers therebetween.

[0028] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component illustrated in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90° or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0029] As used herein, the term "layer" refers to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers thereon, above and / or below. A layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0030] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Further alternatively, the substrate can have semiconductor devices or circuits formed therein.

[0031] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of this application. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in this application without affecting the efficacy and purpose that can be achieved by this application. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of this application. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of this application without substantially changing the technical content.

[0032] It should also be noted that the longitudinal section corresponding to the embodiment of the present application may be a section corresponding to the front view direction, the transverse section may be a section corresponding to the right view direction, and the horizontal section may be a section corresponding to the top view direction.

[0033] In addition, the embodiments and features of the embodiments of the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0034] like Figure 1 、 Figure 2 and Figure 3 As shown, Figure 1 This is a schematic diagram of an existing semiconductor packaging structure. Figure 2 It is a structural diagram of placing an existing semiconductor packaging structure on a motherboard. Figure 3 It is a simplified structural diagram of placing an existing semiconductor packaging structure on a motherboard.

[0035] like Figure 1 、 Figure 2 and Figure 3 The semiconductor package structure shown includes a substrate 101 , a first electronic component 102 , a second electronic component 103 , a package body 104 , a core substrate 105 , a bottom pre-coated solder 106 and a main board 107 .

[0036] In this structure, the first electronic component 102 is arranged on the substrate 101, the second electronic component 103 and the substrate 101 are arranged on the core substrate 105, and a bottom pre-coated solder 106 can be arranged under the core substrate 105, wherein the first electronic component 102 can be an IC component and the second electronic component can be a SoC component.

[0037] Here, the first electronic component 102 is first placed on the substrate 101, and then the substrate 101 and the second electronic component 103 are mounted on the core substrate 105 to form a package body 104. Finally, the semiconductor package structure is mounted on a substrate such as Figure 2 On the main board 107 shown.

[0038] Here, for example, L1 (the thickness from the first electronic component 102 to the substrate 101) can be 2 mm, L2 (the thickness of the core substrate 105) can be 100 μm, and L3 (the thickness of the bottom pre-coated solder 106 under the core substrate 105) can be 45 μm, that is, the thickness of the entire semiconductor packaging structure can be 2.145 mm.

[0039] Here, since the substrate 101 and the second electronic component 103 need to be installed on the core substrate 105 for molding and then installed on the main board 107, the thickness of the first electronic component 102 will not be able to maintain the original component thickness due to the increase in the thickness of the core substrate 105, and the thickness of the entire packaging structure will become thicker.

[0040] like Figure 4 As shown, Figure 4 It is a structural schematic diagram of an embodiment 4a of the semiconductor packaging structure according to the present application.

[0041] like Figure 4As shown, the semiconductor package structure 4a of the present application includes a module 201, a first package body 202, a second electronic component 203, and a second package body 204. The module 201 includes a substrate 2011 and at least one first electronic component 2012 above the substrate 2011. The first package body 202 covers the substrate 2011 and the at least one first electronic component 2012. The second electronic component 203 is disposed adjacent to the module 201. The second package body 204 covers the module 201 and the second electronic component 203. The bottom surface 2041 of the second package body 204 is located between the upper surface 20111 and the lower surface 20112 of the substrate 2011.

[0042] Here, substrate 2011 may include organic and / or inorganic materials. Examples of organic materials include polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Examples of inorganic materials include silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. Substrate 2011 may also be a PCB (Printed Circuit Board).

[0043] The first electronic component 2012 may include an IC component.

[0044] At least one first electronic component 2012 may be disposed above the substrate 2011 and electrically connected to the substrate 2011 .

[0045] The first package body 202 may be formed of various molding compounds. For example, the molding compound may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0046] The second electronic component 203 may include a SoC component, wherein the second electronic component 203 may be disposed adjacent to the module 201 .

[0047] Similarly, the second package body 204 may be formed of various molding compounds. For example, the molding compound may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0048] The material of the first package body 202 and the material of the second package body 204 may be the same or different.

[0049] refer to Figure 5 , Figure 5 FIG5 is a structural diagram of an embodiment 5a in which a removable structure is provided on the semiconductor package structure of the present application.

[0050] In some optional implementations, the bottom surface of the second package body 204 has different levels.

[0051] In some optional implementations, the bottom surface 2041 of the second package body 204 is located between the upper surface 20111 and the lower surface 20112 of the substrate 2011 .

[0052] Here, the substrate 2011 and at least one first electronic component 2012 can be first encapsulated by the first encapsulation body 202. The module 201 (substrate 2011 and at least one first electronic component 2012) and the second electronic component 203 encapsulated by the first encapsulation body 202 are then placed on the removable structure 206. The removable structure 206 forms the second encapsulation body 204, so that the second encapsulation body 204 can encapsulate the module 201 and the second electronic component 203. Furthermore, because the removable structure 206 can be made of a relatively soft adhesive film, it undergoes plastic deformation when subjected to the molding pressure of the second encapsulation body 204, causing the bottom surface 2041 of the second encapsulation body 204 to be formed along the contour of the removable structure 206. Consequently, after the second encapsulation body 204 is cured, the contour features of the removable structure 206 are retained, allowing the bottom surface 2041 of the second encapsulation body 204 to have an irregular contour. This allows the bottom surface of the second encapsulation body 204 to have varying levels.

[0053] refer to Figure 6 and Figure 7 , Figure 5 This is a structural diagram of an embodiment 6a of the present application in which the semiconductor package structure is placed on a mainboard. Figure 7 It is a simplified structural diagram of an embodiment 6a in which the semiconductor packaging structure of the present application is placed on a mainboard.

[0054] like Figure 6 and Figure 7 As shown, the first package body 202 covers the substrate 2011 and at least one first electronic component 2012, and the second package body 204 covers the module 201 and the second electronic component 203. Figure 1-Figure 3 The semiconductor packaging structure shown does not require the module 201 and the second electronic component 203 to be installed on the core substrate for molding, and then the module 201 and the second electronic component 203 are installed on the main board 205. In this way, the module 201 and the second electronic component 203 can be directly set on the main board 205 without increasing the thickness of the core substrate, so that the first electronic component 2012 can maintain its original thickness, and at the same time, the thickness of the entire semiconductor packaging structure will not be increased.

[0055] In some optional embodiments, the second electronic component 203 includes an electrical connection element 2031 , and the electrical connection element 2031 at least partially overlaps with the substrate 2011 in a horizontal direction.

[0056] Here, the electrical connection element 2031 may be, for example, a bump containing solder. The electrical connection element 2031 may be disposed on the bottom surface of the second electronic component 203 and electrically connected to the second electronic component 203 via a copper column.

[0057] Since the electrical connection element 2031 is provided at the bottom of the second electronic component 203, during the process of forming the second package body 204, the irregular contour of the bottom surface 2041 of the second package body 204 can define a space for accommodating the electrical connection element 2031. This can avoid the problem of bridging between different electrical connection elements 2031 and at the same time increase the adhesion between the electrical connection element 2031 and the copper pillar.

[0058] In some optional implementations, a portion of the electrical connection element 2031 is exposed through the second package body 202 .

[0059] Here, the electrical connection element 2031 can directly contact or connect with other elements, such as the mainboard 205 , through the exposed portion of the second package body 202 .

[0060] In some optional embodiments, the first package body 202 may include first filling particles.

[0061] Here, the first filling particles may be in the shape of a sphere or an ellipsoid.

[0062] In some optional embodiments, the first filling particles disposed on the first sidewall 2022 and the second sidewall 2023 of the first package body 202 have a truncated surface.

[0063] It is understandable that the material of the first package body 202 may include first filling particles, and the first side wall 2022 and the second side wall 2023 of the first package body 202 will undergo a cutting process. Therefore, the first filling particles located on the first side wall 2022 and the second side wall 2023 of the first package body 202 will be cut, so that the first filling particles on the first side wall 2022 and the second side wall 2023 of the first package body 202 have a cross-sectional surface, which can be circular or elliptical.

[0064] In some optional embodiments, the second package body 204 may include second filling particles.

[0065] Here, the shape of the second filling particles may be a sphere or an ellipsoid, and the size of the first filling particles may be the same as or different from the size of the second filling particles.

[0066] In some optional embodiments, the second filling particles disposed on the third sidewall 2042 of the second package body 204 have no cross-sections, and the second filling particles disposed on the fourth sidewall 2043 have cross-sections.

[0067] It is understood that the material of the second package body 204 may include second filler particles, and the module 201 and the second electronic component 203 may be covered by the second package body 204 after the first package body 202 is formed. Therefore, the third sidewall 2042 of the second package body 204 directly contacts the second sidewall 2023 of the first package body 202, and the third sidewall 2042 of the second package body 204 does not need to undergo a cutting process. Therefore, the second filler particles located on the third sidewall 2042 of the second package body 204 can maintain their complete shape, and the second filler particles on the third sidewall 2042 of the second package body 204 may not have a cross-section. However, the fourth sidewall 2043 of the second package body 204 still needs to undergo a cutting process. Therefore, the second filler particles located on the fourth sidewall 2043 of the second package body 204 will be cut, resulting in the second filler particles on the fourth sidewall 2043 of the second package body 204 having a cross-section, which may be circular or elliptical.

[0068] In some optional implementations, the bottom surface 2041 of the second package body 204 is lower than the bottom surface 2041 of the first package body 202 .

[0069] Here, the first package body 202 covers the substrate 2011 and at least one first electronic component 2012. The bottom surface 2021 of the first package body can directly contact the upper surface 20111 of the substrate 2011, and the bottom surface 2041 of the second package body 204 will be formed along the contour of the surface of the removable structure 206. Therefore, the bottom surface 2041 of the second package body 204 will be lower than the upper surface 20111 of the substrate 2011 and also lower than the bottom surface 2041 of the first package body 202.

[0070] In some optional implementations, there is a gap between the second electronic component 203 and the substrate 2011 .

[0071] Here, the space between the second electronic component 203 and the substrate 2011 is filled with the second packaging body 204 , thereby enhancing the stability of the second electronic component 203 .

[0072] Above, embodiments 4a, 5a and 6a of the electronic device of the present application are introduced.

[0073] refer to Figures 8-17 , Figures 8-17 It is a schematic diagram of the manufacturing steps of an embodiment 4a of the semiconductor packaging structure according to the present application.

[0074] refer to Figure 8 , providing a module 201 , wherein the module 201 includes a substrate 2011 and at least one first electronic component 2012 above the substrate 2011 .

[0075] Here, substrate 2011 may include organic and / or inorganic materials. Examples of organic materials include polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Examples of inorganic materials include silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc. Substrate 2011 may also be a PCB (Printed Circuit Board).

[0076] The first electronic component 2012 may include an IC component.

[0077] At least one first electronic component 2012 may be disposed above the substrate 2011 and electrically connected to the substrate 2011 .

[0078] refer to Figure 9 , providing a first package body 202.

[0079] The first package body 202 is configured to cover the substrate 2011 and at least one first electronic component 2012 .

[0080] The first package body 202 may be formed of various molding compounds. For example, the molding compound may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0081] refer to Figure 10 , a cutting knife 207 is provided.

[0082] The first package body 202 is cut.

[0083] In some optional embodiments, the first package body 202 may include first filling particles.

[0084] Here, the first filling particles may be in the shape of a sphere or an ellipsoid.

[0085] It can be understood that the material of the first package body 202 may include first filling particles, and the first side wall 2022 and the second side wall 2023 of the first package body 202 are subjected to a cutting process. Therefore, the first filling particles located on the first side wall 2022 and the second side wall 2023 of the first package body 202 will be cut, so that the first filling particles on the first side wall 2022 and the second side wall 2023 of the first package body 202 have a cross-sectional surface, which can be circular or elliptical.

[0086] refer to Figure 11 , providing a removable structure 206 and a second electronic component 203.

[0087] Here, you can Figure 10 The formed structure and the second electronic component 203 are disposed on the removable structure 206 . The second electronic component 203 is disposed adjacent to the module 201 . The second electronic component 203 may include a SoC component.

[0088] The second electronic component 203 may include an electrical connection element 2031 , which at least partially overlaps with the substrate 2011 in a horizontal direction.

[0089] Here, the electrical connection element 2031 may be, for example, a bump containing solder. The electrical connection element 2031 may be disposed on the bottom surface of the second electronic component 203 and electrically connected to the second electronic component 203 via a copper column.

[0090] The removable structure 206 may be an adhesive film.

[0091] The removable structure 206 may include a metal frame 2061 .

[0092] refer to Figure 12 , providing a second package body 204.

[0093] The second package body 204 may cover the module 201 and the second electronic component 203 , wherein a bottom surface 2041 of the second package body 204 is located between the upper surface 20111 and the lower surface 20112 of the substrate 2011 .

[0094] The bottom surfaces of the second package body 204 have different levels. The bottom surface 2041 of the second package body 204 is lower than the bottom surface 2041 of the first package body 202 .

[0095] The second package body 204 may be formed of various molding compounds. For example, the molding compound may include epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0096] The material of the first package body 202 and the material of the second package body 204 may be the same or different.

[0097] Here, the first package body 202 covers the substrate 2011 and at least one first electronic component 2012. The bottom surface 2021 of the first package body can directly contact the upper surface 20111 of the substrate 2011, and the bottom surface 2041 of the second package body 204 will be formed along the contour of the surface of the removable structure 206. Therefore, the bottom surface 2041 of the second package body 204 will be lower than the upper surface 20111 of the substrate 2011 and also lower than the bottom surface 2041 of the first package body 202.

[0098] Here, the substrate 2011 and at least one first electronic component 2012 can be first covered by the first package 202, and then the module 201 (substrate 2011 and at least one first electronic component 2012) and the second electronic component 203 covered by the first package 202 are placed on the removable structure 206. The removable structure 206 is used to form the second package 204, so that the second package 204 can cover the module 201 and the second electronic component 203. In addition, since the removable structure 206 can use a relatively soft adhesive film, it will undergo plastic deformation when it is subjected to the molding pressure of the second package 204, causing the bottom surface 2041 of the second package 204 to follow the removable structure 206. 6. Thus, after the second package body 204 is cured, the contour features of the surface of the removable structure 206 will be retained. The bottom surface 2041 of the second package body 204 can form an irregular contour, thereby enabling the bottom surface of the second package body 204 to have different levels. In addition, an electrical connection element 2031 is provided at the bottom of the second electronic component 203. During the formation of the second package body 204, the irregular contour of the bottom surface 2041 of the second package body 204 can define a space for accommodating the electrical connection element 2031. Thus, bridging problems between different electrical connection elements 2031 can be avoided, and at the same time, the adhesion between the electrical connection element 2031 and the copper pillar can be increased.

[0099] In some optional implementations, there is a gap between the second electronic component 203 and the substrate 2011 .

[0100] Here, the space between the second electronic component 203 and the substrate 2011 is filled with the second packaging body 204 , thereby enhancing the stability of the second electronic component 203 .

[0101] refer to Figure 13 , for laser marking.

[0102] refer to Figure 14 , a cutting knife 207 is provided.

[0103] The second package body 204 is cut.

[0104] The second package body 204 may include second filling particles.

[0105] Here, the shape of the second filling particles may be a sphere or an ellipsoid, and the size of the first filling particles may be the same as or different from the size of the second filling particles.

[0106] It is understood that the material of the second package body 204 may include second filler particles, and the module 201 and the second electronic component 203 may be covered by the second package body 204 after the first package body 202 is formed. Therefore, the third sidewall 2042 of the second package body 204 directly contacts the second sidewall 2023 of the first package body 202, and the third sidewall 2042 of the second package body 204 does not need to undergo a cutting process. Therefore, the second filler particles located on the third sidewall 2042 of the second package body 204 can maintain their complete shape, and the second filler particles on the third sidewall 2042 of the second package body 204 may not have a cross-section. However, the fourth sidewall 2043 of the second package body 204 still needs to undergo a cutting process. Therefore, the second filler particles located on the fourth sidewall 2043 of the second package body 204 will be cut, resulting in the second filler particles on the fourth sidewall 2043 of the second package body 204 having a cross-section, which may be circular or elliptical.

[0107] refer to Figure 15 ,exist Figure 14 A removable structure 206 is disposed on the formed structure (the first package body 202 and the second package body 204 ) and then flipped over.

[0108] refer to Figure 16 , remove the removable structure 206.

[0109] refer to Figure 17 , forming a semiconductor packaging structure 4a.

[0110] In this way, the first package body 202 covers the substrate 2011 and at least one first electronic component 2012, and the second package body 204 covers the module 201 and the second electronic component 203. There is no need to install the module 201 and the second electronic component 203 on the core substrate for molding, and then install the module 201 and the second electronic component 203 on the main board 205. In this way, the module 201 and the second electronic component 203 can be directly set on the main board 205 without increasing the thickness of the core substrate, so that the first electronic component 2012 can maintain its original thickness, and at the same time, the thickness of the entire semiconductor packaging structure will not be increased.

[0111] Although the present application has been described and illustrated with reference to specific embodiments of the present application, these descriptions and illustrations do not limit the present application. It will be clearly understood by those skilled in the art that various changes may be made and equivalent elements may be substituted within the embodiments without departing from the true spirit and scope of the present application as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present application and the actual implementation. There may be other embodiments of the present application that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present application. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present application. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present application.

Claims

1. A semiconductor packaging structure, characterized in that: include: A module includes a substrate and at least one first electronic component above the substrate; a first package body, covering the substrate and at least one of the first electronic components; a second electronic component disposed adjacent to the module; The second package body covers the module and the second electronic component, wherein the bottom surface of the second package body is located between the upper surface and the lower surface of the substrate.

2. The semiconductor package structure according to claim 1, wherein: The bottom surfaces of the second package body have different levels.

3. The semiconductor package structure according to claim 1, wherein: The second electronic component includes an electrical connection element, and the electrical connection element at least partially overlaps with the substrate in a horizontal direction.

4. The semiconductor package structure according to claim 3, wherein: A portion of the electrical connection element is exposed through the second package body.

5. The semiconductor package structure according to claim 1, wherein: The first package body includes first filling particles.

6. The semiconductor package structure according to claim 5, wherein: The first filling particles disposed on the first sidewall and the second sidewall of the first package body have a truncated surface.

7. The semiconductor package structure according to claim 1, wherein: The second encapsulation body includes second filling particles.

8. The semiconductor package structure according to claim 7, wherein: The second filling particles disposed on the third sidewall of the second package body have no cross-section, and the second filling particles disposed on the fourth sidewall of the second package body have cross-sections.

9. The semiconductor package structure according to claim 1, wherein: A bottom surface of the second package body is lower than a bottom surface of the first package body.

10. The semiconductor package structure according to claim 1, wherein: There is a gap between the second electronic component and the substrate.

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