Display device, chip and analog-to-digital converter

Abstract

The utility model discloses a display device, a chip and an analog-to-digital converter, the operation of the analog-to-digital converter comprises a sampling stage and a subsequent conversion stage, the analog-to-digital converter comprises a sampling and holding circuit for sampling and holding an input analog signal to obtain a voltage sampling signal; a digital-to-analog converter generating a first analog voltage and a second analog voltage; the comparison circuit is used for respectively comparing the first analog voltage and the second analog voltage with a voltage sampling signal so as to obtain a comparison signal; the logic control circuit is used for carrying out successive approximation control on the digital-to-analog converter according to the comparison signals in a conversion stage, so that the comparison circuit outputs the comparison signals successively and outputs digital signals corresponding to the input analog signals according to the plurality of comparison signals; the logic control circuit also controls the first analog voltage and the second analog voltage to be equal to the input analog signal in the sampling stage, and calibrates the offset voltage of the comparison circuit, thereby improving the nonlinear offset of the analog-to-digital converter.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and in particular to a display device, a chip, and an analog-to-digital converter. Background Art

[0002] An analog-to-digital converter (ADC) converts continuous analog signals into discrete digital signals that can be processed by computers. It is a key component in the interface between analog and digital systems and has long been widely used in radar, communications, measurement and control, medical treatment, instrumentation, imaging, and audio. The rapid development of digital signal processing technology and the communications industry is driving the development of ADCs towards higher speed, higher precision, and lower power consumption.

[0003] Successive Approximation Register Analog to Digital Converter

[0004] A SAR ADC (Special Analog Converter or SAR ADC) uses a binary search method to continuously generate new analog voltages to approximate the original analog input signal through its integrated digital-to-analog converter (DAC). The DAC's corresponding digital input is then used as the ADC's output. Compared to other ADC types, SAR ADCs offer advantages such as medium speed, medium accuracy, low power consumption, and low cost, making them suitable for a wide range of applications.

[0005] A SAR ADC primarily consists of a DAC, a comparator, and SAR logic control circuitry. SAR ADCs are categorized as either single-ended or differential inputs based on the input signal type. The DAC structure within the SAR ADC can be categorized as resistor divider, current summation, or charge redistribution. The charge redistribution structure is the most commonly used, and it can be further categorized as either a serial DAC or a parallel DAC based on the conversion process. Parallel DACs are typically constructed using binary-weighted capacitors, resistors, or MOS current sources and can convert all bits simultaneously. A serial DAC can only convert one bit of analog output at a time, requiring a conversion time of NT, where N is the number of bits and T is the time required to convert one bit of output. The offset error of a single-ended input SAR ADC using a serial DAC primarily comes from the comparator's offset voltage. The comparator's input common mode varies with the input signal, causing the comparator's offset to be dependent on the input signal, resulting in nonlinear comparator offset.

[0006] Therefore, a new analog-to-digital converter is needed to improve its nonlinear offset. Utility Model Content

[0007] In view of the above problems, an object of the present invention is to provide a display device, a chip, and an analog-to-digital converter, thereby improving the nonlinear offset of the analog-to-digital converter.

[0008] According to one aspect of the present invention, an analog-to-digital converter is provided, the operation of which includes a sampling phase and a subsequent conversion phase, wherein the analog-to-digital converter includes a sampling and holding circuit for sampling and holding an input analog signal to obtain a voltage sampling signal; a digital-to-analog converter for generating a first analog voltage and a second analog voltage; a comparison circuit for comparing the first analog voltage and the second analog voltage with the voltage sampling signal, respectively, to obtain a comparison signal; and a logic control circuit for performing successive approximation control on the digital-to-analog converter according to the comparison signal during the conversion phase, so that the comparison circuit successively outputs comparison signals and outputs digital signals corresponding to the input analog signal according to multiple comparison signals, wherein the logic control circuit is further used to control the first analog voltage and the second analog voltage to be equal to the input analog signal during the sampling phase, and to calibrate the offset voltage of the comparison circuit.

[0009] Optionally, the digital-to-analog converter is a serial digital-to-analog converter.

[0010] Optionally, the digital-to-analog converter includes a first reference voltage switch, connected between a first reference voltage and the first analog voltage; a second reference voltage switch, connected between a second reference voltage and the second analog voltage; a first sampling switch, connected between the input analog signal and the first analog voltage; a second sampling switch, connected between the input analog signal and the second analog voltage; a charge redistribution switch, connected between the first analog voltage and the second analog voltage; a first storage capacitor, connected between the first analog voltage and the ground terminal; and a second storage capacitor, connected between the second analog voltage and the ground terminal.

[0011] Optionally, in the sampling phase, the first sampling switch and the second sampling switch are turned on, and the first reference voltage switch, the second reference voltage switch, and the charge redistribution switch are turned off; in the conversion phase, the first sampling switch and the second sampling switch are turned off, and one or two of the first reference voltage switch, the second reference voltage switch, and the charge redistribution switch are selectively turned on.

[0012] Optionally, the comparison circuit includes a first operational amplifier having a positive input terminal receiving the first analog voltage and a negative input terminal receiving the voltage sampling signal; a second operational amplifier having a positive input terminal receiving the second analog voltage and a negative input terminal receiving the voltage sampling signal, a positive output terminal connected to the positive output terminal of the first operational amplifier, and a negative output terminal connected to the negative output terminal of the first operational amplifier; a first offset storage capacitor having a first terminal connected to the positive output terminal of the first operational amplifier; a second offset storage capacitor having a first terminal connected to the negative output terminal of the first operational amplifier; a third operational amplifier having a positive input terminal connected to the second terminal of the first offset storage capacitor and a negative input terminal connected to the second terminal of the second offset storage capacitor; a first offset cancellation switch connected between the positive input terminal and the negative output terminal of the third operational amplifier; a second offset cancellation switch connected between the negative input terminal and the positive output terminal of the third operational amplifier; and a latch having a positive input terminal connected to the negative output terminal of the third operational amplifier, a negative input terminal connected to the positive output terminal of the third operational amplifier, and an output terminal providing a first comparison signal and a second comparison signal, wherein the comparison signal is a differential signal of the first comparison signal and the second comparison signal.

[0013] Optionally, the latch selectively operates in a reset state or a latched state according to a state control signal provided by the logic control circuit.

[0014] Optionally, the first operational amplifier selectively short-circuits its two output terminals according to the state of the latch; the second operational amplifier selectively short-circuits its two output terminals according to the state of the latch; and the third operational amplifier selectively short-circuits its two output terminals according to the state of the latch, wherein, when the latch is in the latched state, the two output terminals of each of the first to third operational amplifiers are short-circuited, and when the latch is in the reset state, the connection between the two output terminals of each of the first to third operational amplifiers is disconnected.

[0015] Optionally, the comparison circuit further includes an XNOR gate, two input terminals of which receive the first comparison signal and the second comparison signal respectively, and an output terminal of which provides a feedback signal to the first to third operational amplifiers, wherein the feedback signal represents the state of the latch.

[0016] Optionally, the first operational amplifier and the second operational amplifier have the same structure, both including a first operational amplifier unit and a second operational amplifier unit. The structure of the third operational amplifier is the same as that of the first operational amplifier unit. The first operational amplifier unit includes a first transistor connected between the first output terminal and the second output terminal, and its control terminal is connected to receive the feedback signal; a second transistor, a third transistor and a fourth transistor are connected in sequence between the power supply voltage and the ground terminal, the control terminal of the second transistor is connected to the second output terminal, the control terminal of the third transistor is connected to the first input terminal, the control terminal of the fourth transistor is connected to the first bias terminal, and the intermediate node between the second transistor and the third transistor is the first output terminal; a fifth transistor and a sixth transistor are connected in sequence between the power supply voltage and the intermediate node between the third transistor and the fourth transistor, the control terminal of the fifth transistor is connected to the first output terminal, the control terminal of the sixth transistor is connected to the second input terminal, and the intermediate node between the fifth transistor and the sixth transistor is the second output terminal; a seventh transistor is connected between the power supply voltage and the first output terminal. The control terminal of the seventh transistor is connected to the first output terminal; the eighth transistor is connected between the power supply voltage and the second output terminal, and the control terminal of the eighth transistor is connected to the second output terminal. The second operational amplifier unit includes a ninth transistor, a tenth transistor, and an eleventh transistor, which are connected in sequence between the power supply voltage and the ground terminal, the control terminal of the ninth transistor is connected to the second bias terminal, the control terminal of the tenth transistor is connected to the second input terminal, and the control terminal of the eleventh transistor is connected to the intermediate node between the tenth transistor and the eleventh transistor; the twelfth transistor and the thirteenth transistor are connected in sequence between the intermediate node between the ninth transistor and the tenth transistor and the ground terminal, the control terminal of the twelfth transistor is connected to the first input terminal, and the control terminal of the thirteenth transistor is connected to the intermediate node between the twelfth transistor and the thirteenth transistor; the fourteenth transistor is connected between the first output terminal and the ground terminal, and its control terminal is connected to the control terminal of the eleventh transistor; the fifteenth transistor is connected between the second output terminal and the ground terminal, and its control terminal is connected to the control terminal of the thirteenth transistor.

[0017] Optionally, the latch includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor, which are sequentially connected between the power supply voltage and the ground terminal, the control terminals of the sixteenth transistor and the seventeenth transistor are connected to the second output terminal, the control terminal of the eighteenth transistor is connected to the first input terminal, the control terminal of the nineteenth transistor receives a clock signal, and the intermediate node between the sixteenth transistor and the seventeenth transistor is the first output terminal; the twentieth transistor, the twenty-first transistor, and the twenty-second transistor are sequentially connected between the power supply voltage and the intermediate node between the eighteenth transistor and the nineteenth transistor, and the control terminals of the twentieth transistor and the twenty-first transistor are connected to the first input terminal. The output terminal, the control terminal of the twenty-second transistor is connected to the second input terminal, and the intermediate node between the twentieth transistor and the twenty-first transistor is the second output terminal; the twenty-third transistor is connected between the power supply voltage and the first output terminal, and the control terminal receives the clock signal; the twenty-fourth transistor is connected between the power supply voltage and the second output terminal, and the control terminal receives the clock signal; the twenty-fifth transistor is connected between the power supply voltage and the intermediate node between the seventeenth transistor and the eighteenth transistor, and the control terminal receives the clock signal; the twenty-sixth transistor is connected between the power supply voltage and the intermediate node between the twenty-first transistor and the twenty-second transistor, and the control terminal receives the clock signal.

[0018] According to a second aspect of the present invention, a chip is provided, comprising the analog-to-digital converter as described above.

[0019] According to a third aspect of the present invention, a display device is provided, comprising a display panel for displaying an image; a driving circuit for controlling the display state of the display panel; an analog-to-digital converter as described above for converting a received analog signal into a digital signal; and a processing unit for processing the digital signal and providing it to the driving circuit.

[0020] The display device, chip, and analog-to-digital converter provided by the present invention enable the application of a SAR ADC using a serial DAC to rail-to-rail (full-swing) input applications through a four-input comparison circuit. By employing a first and second operational amplifier connected in parallel as the first-stage amplifier circuit of the comparison circuit, the parasitic capacitance mismatch between the two capacitors in the digital-to-analog converter is reduced, thereby improving the error of the analog-to-digital converter when using a serial DAC. The serial DAC can both generate the required analog voltage and participate in the sampling process, ensuring that the voltages at the four input terminals of the comparison circuit are equal during the sampling phase, thereby providing conditions for offset cancellation of the comparison circuit. After each ADC sampling and offset cancellation operation, the offset eliminated is the offset amount when the input signal of the comparison circuit is an analog input signal, thereby improving the nonlinear offset of the comparison circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic structural diagram of a SAR ADC is shown;

[0023] Figure 2 A circuit diagram of a serial DAC is shown;

[0024] Figure 3 Shows the use of Figure 2 Schematic diagram of the structure of the SAR DAC of the serial DAC shown;

[0025] Figure 4 Shown Figure 2 The conversion sequence of the serial DAC shown;

[0026] Figure 5 A schematic structural diagram of an analog-to-digital converter according to an embodiment of the present utility model is shown;

[0027] Figure 6 A schematic structural diagram of a sample-and-hold circuit according to an embodiment of the present utility model is shown;

[0028] Figure 7 A schematic structural diagram of a digital-to-analog converter according to an embodiment of the present invention is shown;

[0029] Figure 8 FIG. 2 shows a schematic structural diagram of a comparison circuit according to an embodiment of the present utility model;

[0030] Figure 9 FIG2 shows a circuit diagram of an operational amplifier AMP1 / AMP2 according to an embodiment of the present invention;

[0031] Figure 10 FIG2 shows a circuit diagram of an operational amplifier AMP3 according to an embodiment of the present utility model;

[0032] Figure 11 A circuit diagram of a latch according to an embodiment of the present utility model is shown;

[0033] Figure 12 A timing diagram of an analog-to-digital converter according to an embodiment of the present utility model is shown. DETAILED DESCRIPTION

[0034] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements or modules are represented by identical or similar reference numerals. For clarity, the various parts in the accompanying drawings are not drawn to scale.

[0035] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element or circuit is said to be "connected" between two nodes, it can be directly coupled or connected to the other element or there can be intermediate elements. The connection between the elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0036] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0037] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0038] Figure 1 A schematic diagram of the structure of a SAR ADC is shown. Figure 1SAR ADC 100 is a single-ended input SAR ADC. It includes a digital-to-analog converter (DAC) 110, a sample-and-hold circuit 120, a comparator COMP, and a SAR logic control circuit 130. The sample-and-hold circuit 120 samples and holds the input analog signal Vin, with its output connected to the positive input of the comparator COMP. The negative input of the comparator COMP receives the analog voltage provided by the DAC 110. The comparator COMP compares the input analog signal Vin with the analog voltage and provides the comparison result to the SAR logic control circuit 130. The SAR logic control circuit 130 generates a logic control signal based on the comparison result of the comparator COMP. The logic control signal is an N-bit binary number. The DAC 110 receives a reference voltage VREF and a logic control signal provided by the SAR logic control circuit 130. Based on the reference voltage VREF and the logic control signal, it generates an analog voltage to approximate the input analog signal Vin. When the input analog signal Vin is approximately equal to the analog voltage, the logic control signal corresponding to the analog voltage is used as the output signal of the SAR DAC 100.

[0039] The operating principle of the SAR ADC 100 is as follows: the MSB of the N-bit binary code initially output by the SAR logic control circuit 130 is 1, and the remaining bits are 0. The digital-to-analog converter 110 generates an analog voltage of 0.5 VREF based on the initial code. The comparator COMP compares the analog voltage of 0.5 VREF with the input analog signal Vin. If the comparator COMP outputs a high level, the MSB of the N-bit binary code finally outputted by the SAR DAC 100 is 1; otherwise, it is 0. The next MSB-1 of the N-bit binary code next outputted by the digital-to-analog converter 110 is set to 1, and the remaining bits are 0. This is combined with the known MSB bit to form a digital code, which is then inputted into the digital-to-analog converter 110 again. The comparator COMP then compares the input analog signal Vin with the analog voltage of the digital-to-analog converter 110. If the comparator COMP outputs a high level, the MSB-1 of the N-bit binary code finally outputted by the SAR DAC 100 is 1; otherwise, it is set to 0, and this continues until the final SAR DAC output is 1. All the digits of the N-digit binary number 100 are determined.

[0040] Figure 2 A schematic diagram of a serial DAC circuit is shown. Figure 2The serial DAC includes a reference voltage source that provides a reference voltage VREF, capacitors C1-C2, and switches S1-S4. When switch S1 is turned on, capacitors C1 and C2 are connected in parallel, redistributing the charge on capacitors C1 and C2 so that the voltage on capacitor C1 is equal to the voltage on capacitor C2. If the i-th binary digit of the logic control signal it receives is 1, switch S2 is turned on, charging capacitor C1 to the reference voltage VREF. If the i-th binary digit of the logic control signal it receives is 0, switch S3 is turned on, discharging capacitor C1 to 0. Switch S4 discharges capacitor C2 at the beginning of digital-to-analog conversion. Bit conversion generally starts from the least significant bit (LSB) and ends at the most significant bit (MSB). Taking C1=C2 and the binary digits to be converted as b0=1, b1=1, b2=0, and b3=1 as an example, the conversion process is to first turn on switch S4 to make Vc2=0, then perform the conversion of b3, that is, turn on switch S2 to make Vc1=VREF, turn on switch S1 to make Vc1=Vc2=0.5VREF, then perform the conversion of b2, that is, turn on switch S3 to make Vc1=0, turn on switch S1 to make Vc1=Vc2=0.25VREF, then perform the conversion of b1, that is, turn on switch S2 to make Vc1=VREF, turn on switch S1 to make Vc1=Vc2=5 / 8VREF, and finally perform the conversion of b0, that is, turn on switch S2 to make Vc1=VREF, turn on switch S1 to make Vc1=Vc2=5 / 16VREF. The whole process requires turning on the switches 9 times in sequence to complete the conversion.

[0041] Although serial DACs offer a simple structure and minimal area requirements, their performance is significantly impacted by various error sources, limiting their widespread adoption in practical applications. For example, when critical capacitors such as C1 and C2 need to be matched within the least significant bit (LSB) accuracy, the presence of parasitic capacitance significantly increases the matching difficulty, thus impacting the DAC's overall performance. For example, when the switch's turn-on and turn-off phases introduce additional charge transfer during the charge redistribution process, this charge injection effect caused by the switch's parasitic capacitance directly affects the DAC's output voltage. Furthermore, the switch's on-resistance and switching speed also limit the DAC's conversion rate and accuracy. For example, when driven by a high-speed clock signal, the clock signal may couple into the capacitor array through the switch's parasitic capacitance, causing unwanted charge perturbations and, consequently, clock feedthrough error. This error can disrupt the DAC's linearity and reduce its output accuracy.

[0042] Figure 3 Shows the use of Figure 2 The structural diagram of the SAR ADC of the serial DAC shown; Figure 4 Shown Figure 2 The conversion sequence of the serial DAC is shown.

[0043] See also Figure 3 The data storage register, DAC control register, and timing and control logic circuit of the SAR ADC 200 together constitute the SAR logic control circuit of the SAR ADC 200 .

[0044] See also Figure 4 SAR ADC 200 first determines the value of the highest bit aN-1 of the binary digit it finally outputs, and then determines the value of the middle bits aN-2-a1 in sequence until the value of the lowest bit a0 is determined. Taking the value of the i-th (i>1) bit of the binary digit finally output by SAR DAC 200 as an example, the i-1 binary digits already determined in the data storage register are added by 1, and 1 is used as the i-th binary digit, thereby forming a digital code with i binary digits in the DAC control register. The digital code is then converted into an analog voltage by a digital-to-analog converter, and the analog voltage is compared with the input analog signal Vin to determine the value of the i-th bit, which is then stored in the data storage register. Figure 4 It can be seen that the N-bit SAR ADC 200 requires at least N(N+1) clock cycles to complete one conversion.

[0045] Since the input common mode of the comparator COMP changes with the input signal, it may cause nonlinear error in the offset of the comparator COMP. Figure 1 and Figure 3 The offset error of the single-ended input SAR ADC shown in Figure 1 is mainly due to the offset voltage of the comparator COMP. Therefore, Figure 1 and Figure 3 The offset error of the single-ended input SAR ADC shown in the figure also exhibits nonlinearity. Existing technologies employ various approaches to eliminate SAR ADC offset errors. One approach uses chopping technology, which quantizes the same input signal twice by switching the two inputs of a comparator circuit, ultimately outputting the average of the two results. This approach requires twice the conversion time, further reducing the SAR ADC's conversion speed. Another approach uses a comparator circuit with a cascaded output offset memory (OOS) and input offset memory (IOS). This approach is generally suitable for applications where the comparator input common mode is independent of the sampled signal size and does not change during the comparison process, such as in some SAR ADCs with fully differential inputs.

[0046] If Figure 3When the SAR ADC 200 shown is applied to a single-ended rail-to-rail (full-rail) input, the comparator must be optimized to enable it to operate normally under the rail-to-rail input. When the existing rail-to-rail input comparator structure is applied to a SAR ADC using a parallel DAC, as the input signal range increases, the input common mode of the comparator is also expanded to the rail-to-rail range, thereby exacerbating the nonlinear error of the offset voltage.

[0047] Therefore, a new analog-to-digital converter is needed to solve the above problems.

[0048] Figure 5 The figure shows a structural diagram of an analog-to-digital converter according to an embodiment of the present utility model.

[0049] See also Figure 5 ADC 300 is a single-ended input SAR ADC. ADC 300 includes a sample-and-hold circuit 310, a digital-to-analog converter 320, a comparison circuit 330, and a logic control circuit 340. Sample-and-hold circuit 310, digital-to-analog converter 320, and comparison circuit 330 are controlled by logic control circuit 340.

[0050] The operation of the analog-to-digital converter 300 includes a sampling phase and a subsequent conversion phase. The sample-and-hold circuit 310 is used to sample the input analog signal VIN and hold it to obtain a voltage sampling signal VIN_SAH. The voltage value of the voltage sampling signal VIN_SAH is equal to the voltage value of the input analog signal VIN.

[0051] The digital-to-analog converter 320 is, for example, a serial DAC. It is used to generate analog voltages DA1_VRH and DA2_VRL. During the sampling phase, the digital-to-analog converter 320 samples the input analog signal VIN and outputs analog voltages DA1_VRH and DA2_VRL equal to the voltage of the input analog signal VIN. Furthermore, during the conversion phase, the digital-to-analog converter 320, under the control of the logic control circuit 340, performs a successive approximation operation to successively generate analog voltages DA1_VRH and DA2_VRL, where the voltages of the analog voltages DA1_VRH and DA2_VRL are equal.

[0052] Comparison circuit 330 has first to fourth input terminals, which receive analog voltage DA2_VRL, analog voltage DA1_VRH, voltage sampling signal VIN_SAH, and voltage sampling signal VIN_SAH, respectively, and outputs comparison signal ADC_OUT. Comparison circuit 330 compares analog voltage DA1_VRH and analog voltage DA2_VRL generated successively by digital-to-analog converter 320 with voltage sampling signal VIN_SAH, and sequentially outputs comparison signal ADC_OUT.

[0053] During the conversion phase, logic control circuit 340 is configured to perform a successive approximation operation on digital-to-analog converter 320 based on comparison signal ADC_OUT, and output a digital signal DATA[N-1,0] corresponding to input analog signal VIN based on multiple comparison signals ADC_OUT. Furthermore, during the sampling phase, logic control circuit 340 controls digital-to-analog converter 320 to generate analog voltages DA1_VRH and DA2_VRL equal to the voltage of input analog signal VIN, and to calibrate the offset voltage of comparison circuit 330. Logic control circuit 340 calibrates the offset voltage of comparison circuit 330 during a period from the start of the sampling phase to the end of the sampling phase.

[0054] Specifically, the logic control circuit 340 receives the start signal and the clock signal CLK, and generates a valid offset cancellation signal OFFSET in a cycle from the beginning to the end of the sampling phase according to the start signal and the clock signal CLK, and generates a valid sampling control signal EN_SAM and a state control signal CMPCTR for controlling the comparison circuit 330 to be in a reset state during the sampling phase.

[0055] The logic control circuit 340 also receives the comparison signal ADC_OUT during the conversion phase and sequentially generates intermediate digital signals corresponding to each bit of the digital signal DATA[N-1,0]. The logic control circuit 340 outputs a logic control signal based on the intermediate digital signal to control the digital-to-analog converter 320 to sequentially generate the corresponding analog voltages DA1_VRH and DA2_VRL, and outputs a state control signal CMPCTR to control the comparison circuit 330 to sequentially generate the comparison signal ADC_OUT.

[0056] The order of generating the intermediate digital signals corresponding to each bit of the digital signal DATA[N-1,0] is from the most significant bit to the least significant bit. Specifically, the logic control circuit 340 first generates the intermediate digital signal 1 corresponding to the most significant bit (MSB) of the digital signal DATA[N-1,0] during the conversion phase, and then controls the digital-to-analog converter 320 to generate the corresponding analog voltage DA1_VRH and analog voltage DA2_VRL. The comparison circuit 330 then compares them with the voltage sampling signal VIN_SAH to obtain the comparison signal ADC_OUT. The value corresponding to the most significant bit (MSB) is then determined based on the comparison signal ADC_OUT. For example, if the comparison signal ADC_OUT is at a high level, the MSB If the value of the second-highest bit MSB-1 is 1, otherwise it is 0. Then, the logic control circuit 340 generates an intermediate digital signal corresponding to the second-highest bit MSB-1. Assuming that the previously determined MSB is 1, the intermediate digital signal corresponding to MSB-1 is 11. Assuming that the previously determined MSB is 0, the intermediate digital signal corresponding to MSB-1 is 01. Then, the value of the second-highest bit MSB-1 is determined by the digital-to-analog converter 320 and the comparison circuit 330, and then the intermediate digital signal corresponding to the second-highest bit MSB-2 is generated, until each bit of the digital signal DATA[N-1,0] output by the analog-to-digital converter 300 is determined.

[0057] Figure 6 The figure shows a schematic structural diagram of a sample-and-hold circuit according to an embodiment of the present utility model.

[0058] See also Figure 6 The sample-and-hold circuit 310 includes a sampling switch S11 and a storage capacitor C11. The sampling switch S11 is connected between the input analog signal VIN and the voltage sampling signal VIN_SAH, and the storage capacitor C11 is connected between the voltage sampling signal VIN_SAH and the ground terminal. The sampling switch S11 is turned on and off by the sampling control signal EN_SAM. During the sampling phase, the sampling switch S11 is turned on, and the sample-and-hold circuit 310 samples the input analog signal VIN and stores it in the storage capacitor C11. During the conversion phase, the sampling switch S11 is turned off, and the voltage sampling signal VIN_SAH maintains the voltage value during the sampling phase through the storage capacitor C11.

[0059] Figure 7 The figure shows a structural diagram of a digital-to-analog converter according to an embodiment of the present utility model.

[0060] See also Figure 7The digital-to-analog converter 320 includes a conversion circuit 321. The conversion circuit 321 includes a reference voltage switch SL, a reference voltage switch SH, sampling switches S12-S13, a charge redistribution switch SR, and storage capacitors C12-C13. The reference voltage switch SL is connected between the reference voltage VRL and the analog voltage DA2_VRL, the reference voltage switch SH is connected between the reference voltage VRH and the analog voltage DA1_VRH, the sampling switch S12 is connected between the input analog signal VIN and the analog voltage DA2_VRL, the sampling switch S13 is connected between the input analog signal VIN and the analog voltage DA1_VRH, the charge redistribution switch SR is connected between the analog voltage DA2_VRL and the analog voltage DA1_VRH, the storage capacitor C12 is connected between the analog voltage DA2_VRL and the ground, and the storage capacitor C13 is connected between the analog voltage DA1_VRH and the ground. The reference voltage VRH is greater than the reference voltage VRL. The on / off state of the sampling switches S12 and S13 is controlled by the sampling control signal EN_SAM.

[0061] During the sampling phase, the reference voltage switches SL and SH are off, the charge redistribution switch SR and sampling switches S12-S13 are on, and the storage capacitors C12-C13 store the sampled input analog signal VIN. The analog voltages DA1_VRH and DA2_VRL are both equal to the input analog signal VIN. During the conversion phase, the sampling switches S12-S13 are off, and one or two of the reference voltage switches SL, SH, and charge redistribution switch SR are turned on.

[0062] The reference voltage switches SL and SH, as well as the charge redistribution switch SR, are turned on and off by logic control signals. These logic control signals include control signals RDIST, VRCTR, and PRECHG. The digital-to-analog converter 320 also includes a decoding circuit 322 for decoding the control signals RDIST, PRECHG, and VRCTR into switch control signals RST, CHGVH, and CHGVL to respectively control the charge redistribution switch SR and the reference voltage switches SH and SL.

[0063] The control signal RDIST is used to control the on and off of the charge redistribution switch SR (for example, when RDIST = 1, the charge redistribution switch SR is off, and when RDIST = 0, the charge redistribution switch SR is off). The control signal PRECHG is used to control the simultaneous changes of the reference voltage switches SH and SL based on the control signal RDIST (for example, when RDIST = 1, if PRECHG = 1, the reference voltage switches SH and SL are simultaneously on; when RDIST = 0, if PRECHG = 0, the reference voltage switches SH and SL are simultaneously off). The control signal VRCTR is used to sequentially output the values ​​of the intermediate digital signal from the most significant bit (MSB) to the second least significant bit (LSB-1) to control the on-state of one of the reference voltage switches SH and SL based on the control signals RDIST and PRECHG (for example, when VRCTR = 1, if RDIST = 1 and PRECHG = 0, the reference voltage switch SH is on; when VRCTR = 0, if RDIST = 1 and PRECHG = 0, the reference voltage switch SL is on).

[0064] Figure 8 FIG. 4 shows a schematic structural diagram of a comparison circuit according to an embodiment of the present utility model.

[0065] See also Figure 8 Comparison circuit 330 includes operational amplifiers AMP1-AMP3, offset storage capacitors C14-C15, offset cancellation switches S14-S15, a latch 331, a NOT gate 332, and an XOR gate 333. The first-stage amplifier circuit of comparison circuit 330 is composed of operational amplifiers AMP1-AMP2, with operational amplifiers AMP1 and AMP2 connected in parallel. The second-stage amplifier circuit of comparison circuit 330 is composed of operational amplifier AMP3. Latch 331 employs a strong arm structure. By providing operational amplifiers AMP1 and AMP2 connected in parallel, the parasitic capacitances of storage capacitors C12 and C13 are matched, thereby reducing the error of digital-to-analog converter 320 and thus reducing the error of analog-to-digital converter 300.

[0066] The positive and negative input terminals of the operational amplifier AMP1 receive an analog voltage DA1_VRH and a voltage sampling signal VIN_SAH, respectively. The positive and negative input terminals of the operational amplifier AMP2 receive an analog voltage DA2_VRL and a voltage sampling signal VIN_SAH, respectively. The positive output terminals of the operational amplifiers AMP1 and AMP2 are connected and provide an analog signal VIP at their common node. The negative output terminals of the operational amplifiers AMP1 and AMP2 are connected and provide an analog signal VIN at their common node. An offset storage capacitor C14 is connected between the positive output terminal of the operational amplifier AMP1 and the positive input terminal of the operational amplifier AMP3. An offset storage capacitor C15 is connected between the negative output terminal of the operational amplifier AMP1 and the negative input terminal of the operational amplifier AMP3. An offset cancellation switch S14 is connected between the positive input and negative output terminal of the operational amplifier AMP3. An offset cancellation switch S15 is connected between the negative input and positive output terminal of the operational amplifier AMP3. The on / off state of the offset cancellation switches S14 and S15 is controlled by the offset cancellation signal OFFSET. The positive input of latch 331 is connected to the negative output of operational amplifier AMP3. Latch 331 also receives a state control signal CMPCTR from a NOT gate 332 and outputs a comparison signal ADC_OUTP and a comparison signal ADC_OUTN. Comparison signal ADC_OUT is the differential signal of comparison signals ADC_OUTP and ADC_OUTN. XENOR gate 333 receives comparison signals ADC_OUTP and ADC_OUTN at its two inputs, respectively, and provides a feedback signal KICKBACK at its output, which indicates the operating state of latch 331. Feedback signal KICKBACK controls the selective shorting of the two outputs of operational amplifiers AMP1-AMP3. When the latch 331 is in the latched state, the feedback signal KICKBACK controls the two output terminals of the operational amplifiers AMP1-AMP3 to be short-circuited. When the latch 331 is in the reset state, the feedback signal KICKBACK controls the two output terminals of the operational amplifiers AMP1-AMP3 to be disconnected.

[0067] During the offset voltage calibration phase of comparator circuit 330, the voltages at both input terminals of operational amplifier AMP1 and AMP2 are equal to the input analog signal VIN, and the voltages at both input terminals of operational amplifier AMP2 are equal to the input analog signal VIN. This amplifies the offset voltages of operational amplifiers AMP1 and AMP2 and stores them in offset storage capacitors C14 and C15. During the conversion phase, the offset voltages generated by operational amplifiers AMP1 and AMP2 offset the voltages stored on offset storage capacitors C14 and C15, thereby canceling the offsets of operational amplifiers AMP1 and AMP2. Offset cancellation switches S14 and S15 are turned on, connecting operational amplifier AMP3 in a unity-gain negative feedback configuration. This reverse-amplifies the offset voltage of operational amplifier AMP3 to its input terminals, thereby canceling the offset voltage of operational amplifier AMP3. The offset voltage of latch 331 is negligible by setting the gain of operational amplifiers AMP1-AMP3 to 0.5LSB. At this point, latch 331 is reset by state control signal CMPCTR, outputting high-level comparison signals ADC_OUTP and ADC_OUTN. This causes feedback signal KICKBACK from XOR gate 333 to be high, disconnecting the output terminals of operational amplifiers AMP1-AMP3. Compared to comparator circuits with cascaded output offset storage (OOS) and input offset storage (IOS), comparator circuit 330 eliminates the need for a redundant reference voltage and the switching associated with that reference voltage during offset voltage calibration.

[0068] During the conversion phase, the comparison circuit 330 compares the analog voltages DA1_VRH and DA2_VRL generated successively by the DAC 320 with the voltage sampling signal VIN_SAH, and outputs comparison signals ADC_OUTP and ADC_OUTN successively.

[0069] Specifically, during any comparison of the comparison circuit 330, after the first two stages of the amplifier circuit of the comparison circuit 330 amplify the difference between the analog voltage DA1_VRH / analog voltage DA2_VRL and the input analog signal VIN, the latch 331 is controlled by the state control signal CMPCTR to switch from the reset state to the latch state, so as to output the comparison signal ADC_OUTP and the comparison signal ADC_OUTN according to the difference between its positive and negative input terminals, and generate a low-level feedback signal KICKBACK according to the comparison signal ADC_OUTP and the comparison signal ADC_OUTN, so that the two output terminals of each of the operational amplifiers AMP1-AMP3 are short-circuited, thereby reducing the feedback noise from the output to the input.

[0070] Figure 9FIG. 4 shows a circuit diagram of operational amplifiers AMP1 - AMP2 according to an embodiment of the present invention.

[0071] See also Figure 9 The operational amplifier AMP1 / AMP2 is a fully differential operational amplifier structure shared by a PMOS differential pair and an NMOS differential pair. The operational amplifier AMP1 / AMP2 includes a first operational amplifier unit 330_1 and a second operational amplifier unit 330_2.

[0072] The first operational amplifier unit 330_1 includes transistors MN1-MN3 and MP1-MP5. Among them, the transistor MP1 is connected between the output terminals VON1 and VOP1, and its control terminal receives the feedback signal KICKBACK. When the feedback signal KICKBACK is at a low level, the transistor MP1 is turned on to short-circuit the two output terminals of the operational amplifier AMP1 / AMP2, and when the feedback signal KICKBACK is at a high level, the transistor MP1 is turned off to control the connection between the two output terminals of the operational amplifier AMP1 / AMP2 to be disconnected; the transistors MP3, MN1 and MN3 are connected between the power supply voltage AVDD and the ground terminal AVSS in sequence, and the transistor MP4 and the transistor MN2 are connected in sequence. Between the power supply voltage AVDD and the midpoint between the transistors MN1 and MN3, the transistor MP2 is connected between the power supply voltage AVDD and the midpoint between the transistors MP3 and MN1, i.e., the output terminal VON1, the transistor MP5 is connected between the power supply voltage AVDD and the midpoint between the transistors MP4 and MN2, i.e., the output terminal VOP1, the control terminals of the transistors MP2 and MP4 are connected to the output terminal VON1, the control terminals of the transistors MP3 and MP5 are connected to the output terminal VOP1, the control terminals of the transistors MN1 and MN2 are connected to the input terminals VIP1 and VIN1, respectively, and the control terminal of the transistor MN3 is connected to the bias terminal VBN.

[0073] The second operational amplifier unit 330_2 includes transistors MN4-MN7 and MP6-MP8. Transistors MP6, MP7, and MN5 are sequentially connected between the power supply voltage AVDD and the ground terminal AVSS. Transistors MP8 and MN6 are sequentially connected between the midpoint between transistors MP6 and MP7 and the ground terminal AVSS. Transistor MN4 is connected between the output terminal VON1 and the ground terminal AVSS. Transistor MN7 is connected between the output terminal VOP1 and the ground terminal AVSS. The control terminals of transistors MN4 and MN5 are connected to the midpoint between transistors MP7 and MN5. The control terminals of transistors MN6 and MN7 are connected to the midpoint between transistors MP8 and MN6. The control terminals of transistors MP7 and MP8 are connected to the input terminals VIN1 and VIP1, respectively. The control terminal of transistor MP6 is connected to the bias terminal VBP. When transistors MN3 and MP6 are turned on, operational amplifiers AMP1 / AMP2 are activated.

[0074] Figure 10 FIG. 4 shows a circuit diagram of an operational amplifier AMP3 according to an embodiment of the present utility model.

[0075] See also Figure 10 , operational amplifier AMP3 is a fully differential operational amplifier structure using an NMOS differential pair. Figure 10 The structure of the operational amplifier AMP3 shown is similar to Figure 9 The structures of the first operational amplifier units 330_1 of the operational amplifiers AMP1 / AMP2 are the same and are not described again here.

[0076] Figure 11 A circuit diagram of a latch according to an embodiment of the present utility model is shown.

[0077] See also Figure 11 The latch 311 includes transistors MP14, MN14, MN11, and MN13 sequentially connected between the power supply voltage AVDD and the ground terminal AVSS; transistors MP15, MN15, and MN12 sequentially connected between the power supply voltage AVDD and the intermediate node between the transistors MN11 and MN13; transistor MP13 connected between the power supply voltage AVDD and the output terminal VON2; transistor MP11 connected between the power supply voltage AVDD and the intermediate node between MN14 and MN11; transistor MP16 connected between the power supply voltage AVDD and the output terminal VOP2; and transistor MP12 connected between the power supply voltage AVDD and the intermediate node between the transistors MN15 and MN12. Control terminals of the transistors MP14 and MN14 are connected to the output terminal VOP2; control terminals of the transistors MP15 and MN15 are connected to the output terminal VON2; control terminals of the transistors MP11-MP13, MP16, and MN13 receive the clock signal CLK1; and control terminals of the transistors MN11 and MN12 are connected to the input terminals VIP2 and VIN2, respectively.

[0078] Latch 311 switches between a reset state and a latched state under the control of state control signal CMPCTR. Specifically, when state control signal CMPCTR is high, latch 311 enters a reset state, causing VON2 and VOP2 to go high. When state control signal CMPCTR is low, latch 311 enters a latched state, causing VON2 and VOP2 to go high. Clock signal CLK1 is the inverted signal of state control signal CMPCTR.

[0079] Figure 12 A timing diagram of an analog-to-digital converter according to an embodiment of the present utility model is shown.

[0080] See also Figure 12The period from the start to the end of the sampling phase is the offset voltage calibration phase for the comparator circuit 330. During the sampling phase, the sampling control signal EN_SAM is high, the sample-and-hold circuit 310 samples and holds the input analog signal VIN, and the digital-to-analog converter 320 samples the input analog signal VIN and outputs analog voltages DA1_VRH and DA2_VRL equal to the voltage of the input analog signal VIN. During the offset voltage calibration phase, the voltages at the four input terminals of the comparator circuit 330 are all equal to the input analog signal VIN, the offset cancellation signal OFFSET is active (high), and the state control signal CMPCTR is also high, controlling the comparator circuit 330 to enter a reset state, thereby enabling the comparator circuit 330 to perform offset cancellation.

[0081] After switching from the sampling phase to the conversion phase, the offset cancellation signal OFFSET and the sampling control signal EN_SAM are both in an invalid state (low level), and the state control signal CMPCTR remains at a high level. After the conversion phase begins, the conversion of the most significant bit (MSB) is performed first. Specifically, the logic control circuit 340 first generates an intermediate digital signal 1 corresponding to the most significant bit (MSB) of the digital signal DATA[N-1,0]. In the first clock cycle, it outputs high-level control signals RDIST and PRECHG and a low-level control signal VRCTR, turning off the charge redistribution switch SR and turning on the reference voltage switches SH and SL, charging the storage capacitors C12 and C13 to the reference voltages VRL and VRH, respectively. In the second clock cycle, the logic control circuit 340 outputs low-level control signals RDIST, PRECHG, and VRCTR, turning on the charge redistribution switch SR and turning off the reference voltage switches SH and SL, resulting in a value equal to ( The analog voltage DA1_VRH and the analog voltage DA2_VRL of (1 / 2) / 2 are obtained by the comparison circuit 330, and the first two amplifier stages of the comparison circuit 330 amplify the difference between the analog voltage DA1_VRH / analog voltage DA2_VRL and the voltage sampling signal VIN_SAH. In the third clock cycle, the state control signal CMPCTR switches from the high level of the previous two clock cycles to the low level, causing the latch 331 to enter the latched state, that is, obtaining the comparison signal ADC_OUT according to the difference between its input signals. At the same time, the exclusive-OR gate 333 outputs a low-level feedback signal KICKBACK according to the comparison signal ADC_OUT, short-circuiting the two output terminals of each of the operational amplifiers AMP1-AMP3, thereby reducing the feedback noise from the output to the input.

[0082] Then, the conversion of the second-highest bit MSB-1 is performed. Specifically, after receiving the comparison signal ADC_OUT, the logic control circuit 340 obtains the value of the MSB and generates an intermediate digital signal i1 corresponding to the second-highest bit MSB-1. Taking the MSB as 1 as an example, the intermediate digital signal corresponding to the second-highest bit MSB-1 is 11. In the fourth clock cycle, it outputs high-level control signals RDIST and PRECHG and low-level control signal VRCTR, so that the charge redistribution switch SR is turned off, and the reference voltage switches SH and SL are turned on at the same time, charging the storage capacitors C12 and C13 to the reference voltages VRL and V RH; In the fifth clock cycle, the logic control circuit 340 outputs low-level control signals RDIST, PRECHG, and VRCTR, so that the charge redistribution switch SR is turned on and the reference voltage switches SH and SL are turned off at the same time, obtaining an analog voltage DA1_VRH and an analog voltage DA2_VRL equal to (VRH+VRL) / 2; In the sixth clock cycle, the logic control circuit 340 outputs high-level control signals RDIST and VRCTR (if the previous MSB is 0, VRCTR is low here), as well as a low-level control signal PRECHG, so that the charge redistribution switch S R is turned off, the reference voltage switch SH is turned on, and the reference voltage switch SL is turned off (if the previous MSB is 0, the reference voltage switch SH is turned off and the reference voltage switch SL is turned on); in the seventh clock cycle, the logic control circuit 340 outputs the low-level control signals RDIST, VRCTR, and PRECHG, so that the charge redistribution switch SR is turned on, and the reference voltage switches SH and SL are turned off at the same time, obtaining an analog voltage DA1_VRH and an analog voltage DA2_VRL equal to (2*VRH+VRL) / 4 (if the previous MSB is 0, the analog voltage DA1_VRH and analog voltage DA2_VRL obtained here are equal to Voltage DA2_VRL equals (VRH + 2*VRL) / 4). Simultaneously, the state control signal CMPCTR switches from low to high, causing latch 331 to enter a reset state and output high-level comparison signals ADC_OUTP and ADC_OUTN. XOR gate 333 outputs a high-level feedback signal KICKBACK, disconnecting the output terminals of operational amplifiers AMP1-AMP3. The first two amplifier stages of comparator circuit 330 amplify the difference between analog voltages DA1_VRH and DA2_VRL and the voltage sampling signal VIN_SAH. In the eighth clock cycle, the state control signal CMPCTR switches from high to low, causing latch 331 to enter a latched state and generate comparison signal ADC_OUT based on the difference between the input signals. Simultaneously, XOR gate 333 outputs a low-level feedback signal KICKBACK based on comparison signal ADC_OUT, short-circuiting the output terminals of operational amplifiers AMP1-AMP3 and reducing feedback noise from the output to the input.Then, the MSB-2-LSB conversion is completed successively until the digital signal DATA[N-1,0] corresponding to the input analog signal VIN is obtained.

[0083] From the timing diagram, it can be seen that starting from the conversion of the second most significant bit MSB-1, the latch 311 is in the reset state only during the cycle when the DAC 320 performs the last charge redistribution, and is in the latched state at the rest of the time.

[0084] The analog-to-digital converter provided by the present invention, through a four-input comparison circuit, enables the SAR ADC using a serial DAC to be applied to rail-to-rail (full-swing) input applications. By using the first and second operational amplifiers connected in parallel as the first-stage amplification circuit of the comparison circuit, the parasitic capacitance mismatch between the two capacitors in the digital-to-analog converter is reduced, thereby improving the error of the analog-to-digital converter when using a serial DAC. The serial DAC can both generate the required analog voltage and participate in the sampling process, ensuring that the voltages at the four input terminals of the comparison circuit are equal during the sampling phase, thereby providing conditions for offset cancellation of the comparison circuit. After each ADC sampling and offset cancellation, the offset eliminated is the offset amount when the input signal of the comparison circuit is an analog input signal, thereby improving the nonlinear offset of the comparison circuit.

[0085] Furthermore, the present invention also provides a chip, comprising the analog-to-digital converter as described above.

[0086] Furthermore, the present invention also provides a display device, which includes: a display panel for displaying an image; a driving circuit for controlling the display state of the display panel; and an analog-to-digital converter for converting a received analog signal into a digital signal; and a processing unit for providing the digital signal provided by the analog-to-digital converter to the driving circuit.

[0087] While the embodiments of the present invention are described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. An analog-to-digital converter, wherein the operation of the analog-to-digital converter includes a sampling phase and a subsequent conversion phase, characterized in that: The analog-to-digital converter comprises: The sampling and holding circuit is used to sample and hold the input analog signal to obtain a voltage sampling signal; a digital-to-analog converter, configured to generate a first analog voltage and a second analog voltage; a comparison circuit, configured to compare the first analog voltage and the second analog voltage with the voltage sampling signal respectively to obtain a comparison signal; and a logic control circuit configured to perform successive approximation control on the digital-to-analog converter according to the comparison signal during the conversion phase, so that the comparison circuit successively outputs comparison signals and outputs a digital signal corresponding to the input analog signal according to a plurality of comparison signals; The logic control circuit is further configured to control the first analog voltage and the second analog voltage to be equal to the input analog signal during the sampling phase, and to calibrate the offset voltage of the comparison circuit.

2. The analog-to-digital converter according to claim 1, wherein The digital-to-analog converter is a serial digital-to-analog converter.

3. The analog-to-digital converter according to claim 2, wherein: The digital-to-analog converter comprises: A first reference voltage switch connected between a first reference voltage and the first analog voltage; a second reference voltage switch connected between a second reference voltage and the second analog voltage; A first sampling switch is connected between the input analog signal and the first analog voltage; a second sampling switch connected between the input analog signal and the second analog voltage; a charge redistribution switch connected between the first analog voltage and the second analog voltage; a first storage capacitor connected between the first analog voltage and a ground terminal; The second storage capacitor is connected between the second analog voltage and the ground terminal.

4. The analog-to-digital converter according to claim 3, wherein: During the sampling phase, the first sampling switch and the second sampling switch are turned on, and the first reference voltage switch, the second reference voltage switch and the charge redistribution switch are turned off; During the conversion phase, the first sampling switch and the second sampling switch are turned off, and one or two of the first reference voltage switch, the second reference voltage switch, and the charge redistribution switch are selectively turned on.

5. The analog-to-digital converter according to claim 1, wherein: The comparison circuit comprises: a first operational amplifier, wherein the positive input terminal receives the first analog voltage, and the negative input terminal receives the voltage sampling signal; a second operational amplifier, having a positive input terminal receiving the second analog voltage, a negative input terminal receiving the voltage sampling signal, a positive output terminal connected to the positive output terminal of the first operational amplifier, and a negative output terminal connected to the negative output terminal of the first operational amplifier; a first offset storage capacitor, a first end of which is connected to the positive output end of the first operational amplifier; a second offset storage capacitor, a first end of which is connected to the negative output terminal of the first operational amplifier; a third operational amplifier, having a positive input terminal connected to the second end of the first offset storage capacitor and a negative input terminal connected to the second end of the second offset storage capacitor; a first offset cancellation switch connected between the positive input terminal and the negative output terminal of the third operational amplifier; a second offset cancellation switch connected between the negative input terminal and the positive output terminal of the third operational amplifier; A latch, wherein the positive input terminal is connected to the negative output terminal of the third operational amplifier, the negative input terminal is connected to the positive output terminal of the third operational amplifier, and the output terminal provides a first comparison signal and a second comparison signal, wherein the comparison signal is a differential signal of the first comparison signal and the second comparison signal.

6. The analog-to-digital converter according to claim 5, wherein: The latch selectively operates in a reset state or a latched state according to a state control signal provided by the logic control circuit.

7. The analog-to-digital converter according to claim 6, wherein: The first operational amplifier selectively short-circuits two output terminals according to the state of the latch; The second operational amplifier selectively short-circuits two output terminals according to the state of the latch; The third operational amplifier selectively short-circuits its two output terminals according to the state of the latch, Wherein, when the latch is in a latched state, the two output terminals of each of the first to third operational amplifiers are short-circuited, and when the latch is in a reset state, the connection between the two output terminals of each of the first to third operational amplifiers is disconnected.

8. The analog-to-digital converter according to claim 7, wherein: The comparison circuit further includes: The XNOR gate has two input terminals receiving a first comparison signal and a second comparison signal respectively, and an output terminal providing a feedback signal to the first to third operational amplifiers, wherein the feedback signal represents the state of the latch.

9. The analog-to-digital converter according to claim 8, wherein: The first operational amplifier and the second operational amplifier have the same structure, both including a first operational amplifier unit and a second operational amplifier unit. The structure of the third operational amplifier is the same as that of the first operational amplifier unit, and the first operational amplifier unit includes: A first transistor is connected between the first output terminal and the second output terminal, and a control terminal thereof is connected to receive the feedback signal; A second transistor, a third transistor, and a fourth transistor are sequentially connected between a power supply voltage and a ground terminal, a control terminal of the second transistor is connected to the second output terminal, a control terminal of the third transistor is connected to the first input terminal, a control terminal of the fourth transistor is connected to the first bias terminal, and an intermediate node between the second transistor and the third transistor is the first output terminal; a fifth transistor and a sixth transistor, connected sequentially between a power supply voltage and an intermediate node between the third transistor and the fourth transistor, wherein a control terminal of the fifth transistor is connected to the first output terminal, a control terminal of the sixth transistor is connected to the second input terminal, and an intermediate node between the fifth transistor and the sixth transistor serves as the second output terminal; a seventh transistor, connected between a power supply voltage and the first output terminal, with a control terminal connected to the first output terminal; an eighth transistor connected between the power supply voltage and the second output terminal, with a control terminal connected to the second output terminal, The second operational amplifier unit includes: a ninth transistor, a tenth transistor, and an eleventh transistor, connected sequentially between a power supply voltage and a ground terminal, a control terminal of the ninth transistor connected to the second bias terminal, a control terminal of the tenth transistor connected to the second input terminal, and a control terminal of the eleventh transistor connected to an intermediate node between the tenth transistor and the eleventh transistor; a twelfth transistor and a thirteenth transistor, connected in sequence between a middle node between the ninth transistor and the tenth transistor and the ground terminal, a control terminal of the twelfth transistor being connected to the first input terminal, and a control terminal of the thirteenth transistor being connected to a middle node between the twelfth transistor and the thirteenth transistor; a fourteenth transistor connected between the first output terminal and the ground terminal, and having a control terminal connected to the control terminal of the eleventh transistor; The fifteenth transistor is connected between the second output terminal and the ground terminal, and has a control terminal connected to the control terminal of the thirteenth transistor.

10. The analog-to-digital converter according to claim 6, wherein: The latch comprises: a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor, connected sequentially between a power supply voltage and a ground terminal, wherein control terminals of the sixteenth transistor and the seventeenth transistor are connected to the second output terminal, the control terminal of the eighteenth transistor is connected to the first input terminal, the control terminal of the nineteenth transistor receives a clock signal, and an intermediate node between the sixteenth transistor and the seventeenth transistor is a first output terminal; a 20th transistor, a 21st transistor, and a 22nd transistor, connected sequentially between a power supply voltage and an intermediate node between the 18th transistor and the 19th transistor, wherein control terminals of the 20th transistor and the 21st transistor are connected to the first output terminal, a control terminal of the 22nd transistor is connected to the second input terminal, and an intermediate node between the 20th transistor and the 21st transistor is the second output terminal; A twenty-third transistor is connected between a power supply voltage and the first output terminal, and a control terminal thereof receives the clock signal; A twenty-fourth transistor is connected between a power supply voltage and the second output terminal, and a control terminal thereof receives the clock signal; A twenty-fifth transistor is connected between a power supply voltage and an intermediate node between the seventeenth transistor and the eighteenth transistor, and has a control terminal receiving the clock signal; The twenty-sixth transistor is connected between a power supply voltage and an intermediate node between the twenty-first transistor and the twenty-second transistor, and has a control terminal receiving the clock signal.

11. A chip, characterized in that: The method comprises an analog-to-digital converter according to any one of claims 1 to 10.

12. A display device, characterized in that: include: A display panel for displaying images; a driving circuit, configured to control the display state of the display panel; The analog-to-digital converter according to any one of claims 1 to 10, configured to convert a received analog signal into a digital signal; The processing unit is used for processing the digital signal and providing the processed digital signal to the driving circuit.

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