Probe card and probe head for circuit probe test system

Abstract

A probe card and a probe head for a circuit probe test system are provided. The probe card includes a substrate portion, a guide plate having a plurality of openings, and a plurality of probe pins extending through the openings, the probe pins include at least one first probe pin configured to transfer power between the substrate portion and the device under test, at least one second probe pin configured to electrically couple the device under test to ground, and at least two third probe pins configured to transfer loopback test signals between contact areas on the device under test. The low dielectric constant material may be located between the third probe pin and the guide plate to prevent direct contact between the third probe pin and the relatively high dielectric constant material of the guide plate, which may improve signal integrity of the loopback test signal.

Description

Technical Field

[0001] The embodiments of the utility model relate to a probe card and a probe head for a circuit probe testing system. Background Art

[0002] The semiconductor industry has experienced continued growth due to the ever-increasing integration density of various electronic components such as transistors, diodes, resistors, capacitors, etc. In large part, these increases in integration density come from the continued reduction in minimum feature size, which allows more components to be packed into a given area. Summary of the Invention

[0003] Some embodiments of the present invention provide a probe card for a circuit probe testing system. The probe card includes a substrate portion, a guide plate, and a plurality of probe pins. The guide plate is located below the substrate portion, and the guide plate includes a plurality of openings passing through the guide plate. The plurality of probe pins extend through the openings in the guide plate, wherein the plurality of probe pins include at least one first probe pin configured to transmit power between the substrate portion and a device under test (DUT), at least one second probe pin configured to electrically couple the DUT to ground, and at least two third probe pins configured to transmit loopback test signals between a plurality of contact areas on the DUT, wherein a low dielectric constant material layer is located between the at least two third probe pins and the guide plate, the dielectric constant of the low dielectric constant material layer being less than the dielectric constant of the guide plate.

[0004] In one embodiment, the low dielectric constant material layer is located within the openings in the guide plate through which each of the at least two third probe pins extends, and the low dielectric constant material layer is not present within the openings in the guide plate through which each of the at least one first probe pin and each of the at least one second probe pin extend.

[0005] In one embodiment, the low-k dielectric constant material layer is located on a portion of an upper surface of the guide plate surrounding the openings in the guide plate through which the at least two third probe pins extend, and each of the at least two third probe pins includes a feature that protrudes radially outward from the at least two third probe pins and contacts the low-k dielectric constant material layer located on the upper surface of the guide plate.

[0006] In one embodiment, the guide plate includes a lower guide plate and an upper guide plate, the upper guide plate includes a plurality of openings passing through the upper guide plate and is located between the substrate portion and the lower guide plate, wherein the low dielectric constant material layer is located between the at least two third probe pins and the upper guide plate.

[0007] In one embodiment, the at least two third probe pins extend through the openings in the upper guide plate and contact the substrate portion, and a conductive trace on and / or in the probe card electrically couples the at least two third probe pins to provide a loopback signal path.

[0008] In one embodiment, the present invention further includes a conductive trace located on a lower surface of the upper guide plate, the conductive trace electrically coupling the at least two third probe pins to provide a loopback signal path, wherein the low dielectric constant material layer is located between the conductive trace and the surface of the guide plate.

[0009] In one embodiment, an adhesion layer is further included within the openings in the guide plate through which each of the at least two third probe pins extends, the adhesion layer comprising at least a conductive material, wherein the adhesion layer is located within the openings in the guide plate through which each of the at least one first probe pin and each of the at least one second probe pin extends, wherein a continuous section of the adhesion layer is located on a surface of the guide plate and electrically couples the at least two second probe pins.

[0010] In one embodiment, the low-k material layer is located between the guide plate and the at least one first probe pin, and the low-k material layer is located on a portion of each of the at least two third probe pins adjacent to the guide plate.

[0011] Some embodiments of the present invention provide a probe head for a circuit probe testing system. The probe head includes a guide plate, a low-k material layer, a conductive trace, and a plurality of probe pins. The guide plate includes a plurality of openings extending through the guide plate. The low-k material layer is located on a surface of the guide plate and extends between a pair of openings in the openings. The dielectric constant of the low-k material layer is less than the dielectric constant of the guide plate. The conductive trace is located on the low-k material layer. The plurality of probe pins extend through the openings in the guide plate, wherein a pair of probe pins are electrically connected by the conductive trace to form a loopback signal path.

[0012] In one embodiment, an adhesion layer is further included between the low dielectric constant material layer and the surface of the guide plate and located above the surface of the guide plate, the adhesion layer comprising a conductive material, wherein the adhesion layer electrically couples at least two of the probe pins extending through the openings in the guide plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The following detailed description, taken in conjunction with the accompanying drawings, will provide a better understanding of the concepts of the embodiments of the present invention. It should be noted that, in accordance with standard industry practice, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of various features may be arbitrarily enlarged or reduced for clarity of illustration.

[0014] Figure 1 is a vertical cross-sectional view of a portion of a circuit probe test system according to various embodiments of the present invention, which can be used to perform circuit probe testing, such as loopback testing, on a device-under-test (DUT).

[0015] Figure 2 It is a vertical cross-sectional view of a portion of a circuit probe testing system according to another embodiment of the present invention.

[0016] Figure 3 It is a vertical cross-sectional view of a portion of a circuit probe testing system according to yet another embodiment of the present invention.

[0017] Figure 4A It is a vertical cross-sectional view of a portion of a circuit probe testing system according to yet another embodiment of the present invention.

[0018] Figure 4B 1 is a vertical cross-sectional view of a probe pin according to various embodiments of the present invention.

[0019] Figure 4C is a vertical cross-sectional view of a probe pin including an adhesive layer formed over a portion of the probe pin according to various embodiments of the present invention.

[0020] Figure 4D is a vertical cross-sectional view of a probe pin including an adhesion layer formed on a portion of the probe pin and a low dielectric constant material layer formed on the adhesion layer according to various embodiments of the present invention.

[0021] Figure 5 It is a vertical cross-sectional view of a portion of a circuit probe testing system according to yet another embodiment of the present invention.

[0022] Figure 6 is a flowchart showing a method of manufacturing a probe card for a circuit probe test system according to various embodiments of the present invention.

[0023] Figure 7 is a flow chart showing a method of manufacturing probe pins for a circuit probe test system according to various embodiments of the present invention.

[0024] Description of reference numerals:

[0025] 100: Circuit Probe Test System

[0026] 101: Device under test

[0027] 102: Lower support member

[0028] 103a: Probe pin / first probe pin / power probe pin

[0029] 103b: Probe pin / Second probe pin / Ground probe pin

[0030] 103c, 103c1, 103c2: Probe pin / third probe pin / loopback probe pin

[0031] 104: Contact area

[0032] 1041: First contact area

[0033] 1042: Second contact area

[0034] 105: Printed Circuit Board

[0035] 106: Interconnection layer

[0036] 107: Interconnection Structure

[0037] 108: Conductive traces

[0038] 109: Ring / Ring Part / Features

[0039] 110: Probe head

[0040] 111: Guide plate / upper guide plate

[0041] 111a: Upper

[0042] 111b: Lower part

[0043] 112: Guide plate / lower guide plate

[0044] 112a: Upper

[0045] 112b: lower part

[0046] 113: Spacer

[0047] 1141: Continuous section / first continuous section

[0048] 1142: Continuous section / Second continuous section

[0049] 1143: Continuous section / third continuous section

[0050] 115: Opening

[0051] 116: Low dielectric constant material layer

[0052] 117: Probe Card

[0053] 118: Gap area / gap section

[0054] 119: substrate part

[0055] 150: System controller

[0056] 200: Method

[0057] 201,203: Step 210: Method

[0058] 211,212,213: Steps

[0059] P: Loopback signal path

[0060] hd1: horizontal direction DETAILED DESCRIPTION

[0061] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present invention. The following describes specific examples of components and configurations to simplify the description of the embodiments of the present invention. Of course, these specific examples are only exemplary and are not intended to limit the embodiments of the present invention. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present invention may repeat reference symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations described.

[0062] In addition, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature shown in the accompanying drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. The device may be rotated 90 degrees or at other orientations, and the spatially relative terms used herein should be interpreted accordingly. Unless expressly stated otherwise, each element having the same reference symbol is assumed to be of the same material composition and have a thickness within the same thickness range.

[0063] Embodiments of the present invention relate to a circuit probe testing system for performing circuit probe testing of electronic devices such as semiconductor integrated circuit devices and a method for manufacturing the same.

[0064] Circuit probe testing is a crucial tool in the manufacturing process of electronic devices, such as semiconductor integrated circuits (ICs). A circuit probe test system, also known as a wafer prober, is a specialized system used to test and verify the designed functionality of electronic circuits. Circuit probe testing can identify faulty or defective devices (e.g., semiconductor ICs) relatively early in the production process (e.g., before wafer dicing or packaging), thereby further reducing costs.

[0065] Circuit probe test system generally includes a probe card with a probe head, and the probe head includes a plurality of probe pins that can be contacted with the contact pads on the device under test. The probe card can also include a substrate portion, which includes a printed circuit board (PCB) that can be used as an interface between the circuit probe test system and the device under test (device under test, DUT). The circuit probe test system transmits an electrical test signal to the device under test through the probe pins of the substrate portion and the probe head, and detects the electrical response signal from the device under test received by the probe pins and the substrate portion. Each probe pin includes an elongated structure with a length of 1 mm or longer (for example, between 4 mm and 7 mm). The probe head generally also includes a probe head fixture (probe head fixture), which includes one or more ceramic guide plates (guide plates), and the guide plate has an opening through which the probe pins extend. The probe head fixture is used to keep the probe pins correctly aligned during the test while still allowing the probe pins to have a certain degree of elastic deformation capability.

[0066] One type of test that can be performed using an in-circuit probe test system is a "loopback" test. Loopback testing can be used to test the communication functionality of a device under test, such as the functionality of the device's transmitter (Tx) and / or receiver (Rx) components for different communication protocols (e.g., USB, PCIe, etc.). A probe head can be used to route signals between different contact pads / bumps on the device under test to test the device's communication functionality. An important parameter when performing in-circuit probe testing is the signal integrity (SI) of the electronic signals transmitted between the in-circuit probe test system and the device under test.

[0067] The above-mentioned circuit probe test system is generally characterized by relatively poor SI performance, including during the circuit probe loopback test. This may be partly attributed to the design of the probe head in the relevant circuit probe test system. In the relevant circuit probe test system, the probe pins may contact the ceramic material of the guide plate used to keep the probe pins properly aligned during the test. However, during the high-frequency loopback test, the direct contact between the probe pins and the relatively high dielectric constant material of the guide plate may significantly degrade the signal transmitted by the probe pins. In addition, during the loopback test, the loopback signal typically traverses a relatively long signal path, which includes the length of the probe pins that transmit the signal from the device under test to the substrate portion of the probe card, the length of the conductive path within the substrate portion of the probe card, and the length of the probe pins that transmit the signal from the substrate portion back to the device under test. This long loopback signal path may further degrade the signal integrity (SI) of the loopback signal.

[0068] Therefore, it is necessary to improve the circuit probe test system to provide improved signal integrity (SI) for the loopback test of the device under test (DUT). Various embodiments of the present invention include a probe card for a circuit probe test system and a manufacturing method thereof. The probe card may include a substrate portion, a probe head including a guide plate, and a plurality of probe pins, wherein the guide plate is located below the substrate portion and has a plurality of openings passing through the guide plate, and the probe pins extend through the openings of the guide plate. The plurality of probe pins may include at least one first probe pin configured to transmit power between the substrate portion and the device under test, at least one second probe pin configured to electrically couple the device under test to ground, and at least two third probe pins configured to transmit loopback test signals between a plurality of contact areas on the device under test. A low dielectric constant material (i.e., low-k material) layer may be located between the third probe pin and the guide plate. The low-k material layer may prevent direct contact between the third probe pin and the guide plate, wherein the guide plate may be composed of ceramic or other high dielectric constant (high-k) materials. Including the low-k material layer can suppress degradation of the loopback test signal due to contact between the third probe pin and the high-k material of the guide plate, thereby improving signal integrity (SI) of the loopback test signal.

[0069] In some embodiments, a layer of low-k material may be provided as a coating on the guide plate, such as within the opening through which the third probe pin extends and on other portions of the guide plate where the third probe pin may contact the guide plate.

[0070] Additionally or alternatively, a layer of low-k material may be applied to the third probe pin at a location adjacent to the guide plate in the assembled probe head.

[0071] In some embodiments, a conductive trace can be provided on a guide plate of the probe head. The conductive trace can be electrically coupled to a pair of third probe pins and extend between them, and can be used to shorten the loopback signal path. In other words, instead of routing the loopback signal path through the substrate portion of the probe card as in a related circuit probe test system, the loopback signal path can be routed through a conductive trace located on the guide plate of the probe head to reduce the loopback signal path length. The reduction in the loopback signal path length can further improve the signal integrity (SI) of the loopback test signal. A low-k material layer can be located between the conductive trace and the surface of the guide plate on which the conductive trace is located.

[0072] In some embodiments, an adhesion layer may be disposed over portions of the guide plate and / or the third probe pin, and a low-k material layer may be formed over the adhesion layer. The adhesion layer may comprise a metal or metal alloy material. The adhesion layer may facilitate adhesion of the low-k material layer to the guide plate and / or the third probe pin, and may also provide enhanced shielding between the third probe pin and / or the conductive trace and the high-k material of the guide plate.

[0073] In some embodiments, a conductive layer can be formed in an opening in the guide plate through which the first probe pin and / or the second probe pin extend. The conductive layer can electrically couple the plurality of second probe pins extending through the guide plate, thereby electrically shorting the plurality of ground connections to the device under test (DUT). Alternatively or additionally, the conductive layer can electrically couple the plurality of first probe pins extending through the guide plate, thereby electrically shorting the plurality of power connections to the device under test. This can help to balance current peaks and can achieve more efficient thermal management in the circuit probe test system. In various embodiments, the conductive layer can be composed of the same material as the adhesion layer, and the conductive layer can be formed (e.g., deposited) simultaneously with the adhesion layer.

[0074] Figure 1 1 is a vertical cross-sectional view of a portion of a circuit probe test system 100 according to various embodiments of the present invention, which can be used to perform circuit probe testing, such as loopback testing, on a device under test (DUT) 101. In some embodiments, the DUT 101 can include a semiconductor substrate (e.g., a silicon wafer) having circuit components formed on and / or within the semiconductor substrate. Other structures suitable for the DUT 101 are also within the intended scope of the present invention, such as semiconductor integrated circuit (IC) dies and / or semiconductor IC packaging structures. The DUT 101 can be located on a lower support member 102, such as a wafer holder.

[0075] Reference again Figure 1 The circuit probe test system 100 includes a probe card 117 including a substrate portion 119 and a probe head 110. The circuit probe test system 100 may also include a system controller 150, which may be coupled to an actuator system (not shown) configured to move the probe card 117 relative to the lower support member 102 in one or more horizontal directions hd1 to align the probe head 110 over a selected area of ​​the device under test 101. Alternatively or additionally, the lower support member 102 may be moved to align the probe head 110 over the selected area of ​​the device under test 101. In some embodiments, the system controller 150 of the circuit probe test system 100 may be operably coupled to an optical detection system that may be used to align the probe head 110 over the selected area of ​​the device under test 101 using optical pattern recognition. In some embodiments, the probe head 110 of the circuit probe test system 100 may form the distal end of a robotic arm.

[0076] The probe head 110 may include a plurality of probe pins 103a, 103b, 103c (including 103c1 and 103c2), which may also be referred to as probing needles. Figure 1 In the illustrated embodiment, the probe head 110 further includes a pair of guide plates, including an upper guide plate 111 and a lower guide plate 112. A spacer 113 may be located between the upper guide plate 111 and the lower guide plate 112. The upper guide plate 111 and the lower guide plate 112 may be formed from a suitable structural material, such as a ceramic material, an engineering plastic material, or the like. Other materials suitable for the upper guide plate 111 and the lower guide plate 112 are also within the contemplated scope of the present invention. The upper guide plate 111 and the lower guide plate 112 may each include a plurality of openings 115 extending through the respective guide plates 111, 112. The probe pins 103a to 103c may extend through the openings 115 in the upper guide plate 111 and the lower guide plate 112. The probe pins 103 a - 103 c may include a collar 109 or similar feature that protrudes radially outward from the body of the probe pins 103 a - 103 c to prevent the probe pins 103 a - 103 c from fully passing through the openings 115 in the upper guide plate 111 .

[0077] In some embodiments, the substrate portion 119 of the probe card 117 may include a printed circuit board (PCB) 105, which may include circuit components that may be used to perform circuit probe testing of the device under test 101. Figure 1In an embodiment, the interconnect layer 106 may be located above the lower surface of the printed circuit board 105. The interconnect layer 106 may include a dielectric matrix material having a conductive interconnect structure 107 extending therethrough. In some embodiments, the interconnect layer 106 may include a multilayer organic (MLO) structure including multiple layers of dielectric polymer material with metal interconnect structures embedded therein. In an embodiment where the probe pins 103a, 103b, 103c are inserted through the upper guide plate 111 and the lower guide plate 112, at least some of the probe pins 103a, 103b, 103c may contact the interconnect structure 107 on the lower surface of the interconnect layer 106, and the interconnect structure 107 may electrically connect the probe pins 103a, 103b, 103c to the printed circuit board 105. Figure 1 In the illustrated embodiment, the probe pins 103a, 103b, 103c can "float" relative to the substrate portion 119, meaning that the probe pins 103a, 103b, 103c are not bonded or otherwise secured to the substrate portion 119. In other embodiments, the probe pins 103a, 103b, 103c can be bonded to electrical contacts on the interconnect layer 106, or in embodiments where the interconnect layer 106 is omitted, the probe pins 103a, 103b, 103c can be bonded directly to the printed circuit board 105 via solder connections.

[0078] During an in-circuit probe test, such as a loopback test, the system controller 150 can move the probe head 110 in a vertically downward direction relative to the device under test 101 so that the lower portions of the probe pins 103a, 103b, and 103c contact contact areas (e.g., contact pads, metal bumps, etc.) formed on the device under test 101. The upper portions of the probe pins 103a, 103b, and 103c can contact the interconnect structure 107 on the lower surface of the substrate portion 119. The system controller 150 can control the probe card 117 to transmit an electronic test signal to the device under test 101 through a first set of one or more probe pins 103a, 103b, and 103c, and receive a response signal transmitted back from the device under test 101 through a second set of one or more probe pins 103a, 103b, and 103c. In some embodiments, the transmitted test signal and the transmitted response signal form a loopback. The detected response signal from the device under test 101 can be analyzed and used to determine whether the device under test 101 has any functional defects. Based on the in-circuit probe testing, the plurality of devices under test 101 may be sorted so that defective devices under test 101 or parts thereof are not used in subsequent manufacturing, distribution, and / or commercialization processes.

[0079] Reference again Figure 1, the probe pins 103a, 103b, 103c1 and 103c2 can be composed of a conductive material, such as a copper-palladium alloy. Other suitable conductive materials are also within the intended scope of the present invention. During circuit probe testing, such as loopback testing, each of the probe pins 103a, 103b, 103c1 and 103c2 can provide a continuous conductive path along their length between the substrate portion 119 of the probe card 117 and the contact area 104 (e.g., contact pads, metal bumps, etc.) on the device under test 101. Figure 1 In some embodiments, each of the probe pins 103a, 103b, 103c can have the same length dimension. In some embodiments, the length dimension of the probe pins 103a, 103b, 103c1, and 103c2 can be between about 4 mm and about 7 mm, although larger or smaller length dimensions can also be used.

[0080] The plurality of probe pins may include at least one first probe pin 103a, which may be used to transmit power between the substrate portion 119 of the probe card 117 and the device under test (DUT) 101. The at least one first probe pin 103a may also be referred to as a "power probe pin" 103a. The plurality of probe pins may also include at least one second probe pin 103b, which may be used to connect the device under test 101 to a ground voltage. The at least one second probe pin 103b may also be referred to as a "ground probe pin" 103b.

[0081] The plurality of probe pins may further include at least two third probe pins 103c (including 103c1 and 103c2). The third probe pins 103c1 and 103c2 may be used to transmit electrical signals between corresponding contact areas 104 (e.g., 1041 and 1042) formed on the device under test 101 via a loopback signal path P during a loopback test of the device under test 101. The third probe pins 103c1 and 103c2 (collectively referred to as third probe pins 103c) may also be referred to as "loopback probe pins" 103c. Figure 1 As shown in the figure, the loopback signal path P can extend from the first contact area 1041 on the device under test 101 through the third loopback probe pin 103c1, along the conductive trace 108 located on and / or in the substrate portion 119 of the probe card 117 to reach another third loopback probe pin 103c2, and then extend through the third loopback probe pin 103c2 to the second contact area 1042 on the device under test 101.

[0082] exist Figure 1In the illustrated embodiment, the conductive traces 108 may be formed from interconnect structures in the interconnect layer 106 of the substrate portion 119 of the probe card 117. However, in other embodiments, the conductive traces 108 may be located in different portions of the probe head 110, such as on and / or within the printed circuit board 105, or on and / or within the upper guide plate 111 and / or the lower guide plate 112, as described in further detail below.

[0083] In addition to the above-mentioned power probe pin 103a, ground probe pin 103b and loopback probe pin 103c, the probe head 110 may also include additional probe pins that can be configured to perform other functions, such as one or more probe pins for transmitting input-output (I / O) signals between the substrate portion 119 of the probe card 117 and the device under test 101.

[0084] Reference again Figure 1 , the adhesion layer 114 may be formed on portions of the upper guide plate 111 and the lower guide plate 112. The adhesion layer 114 may include a metal material, such as copper, chromium, titanium, aluminum, nickel, tungsten, platinum, gold, etc., including alloys and combinations thereof. In some embodiments, the adhesion layer 114 may be formed in openings 115 passing through the upper guide plate 111 and the lower guide plate 112, and may extend along the side surfaces of the openings 115. In some embodiments, the adhesion layer 114 may be formed in all openings 115 passing through the upper guide plate 111 and the lower guide plate 112. Alternatively, the adhesion layer 114 may be formed only in portions of the openings 115 passing through the upper guide plate 111 and the lower guide plate 112. For example, the adhesion layer 114 may be formed only in the opening 115 through which the third probe pin 103c extends in the assembled probe head 110. In other embodiments, such as Figure 1 As shown, an adhesion layer 114 may be formed within each of the openings 115 through which the first probe pin 103 a , the second probe pin 103 b , and the third probe pin 103 c extend in the assembled probe head 110 .

[0085] In some embodiments, the adhesive layer 114 may also be formed on a portion of the upper surface of the upper guide plate 111 and / or a portion of the upper surface of the lower guide plate 112. In some embodiments, the adhesive layer 114 on the upper surface of the upper guide plate 111 and / or the lower guide plate 112 may be formed in continuous sections 1141 and 1142 extending between a plurality of openings 115 passing through the upper guide plate 111 and / or the lower guide plate 112. A gap region 118 may separate the continuous section 1141 from the continuous section 1142.

[0086] exist Figure 1In the illustrated embodiment, the first continuous section 1141 of the adhesive layer 114 can extend over the upper surface of the upper guide plate 111 between the plurality of openings 115 through which the first probe pins 103a extend. Similarly, the first continuous section 1141 of the adhesive layer 114 can extend over the upper surface of the lower guide plate 112 between the plurality of openings 115 through which the first probe pins 103a extend. In some embodiments, each first continuous section 1141 on the upper guide plate 111 and the lower guide plate 112 can extend between all of the openings 115 through which the first probe pins 103a extend.

[0087] Reference again Figure 1 The second continuous section 1142 of the adhesive layer 114 may extend over the upper surface of the upper guide plate 111 between the plurality of openings 115 through which the second probe pins 103b and the third probe pins 103c extend, and the second continuous section 1142 of the adhesive layer 114 may extend over the upper surface of the lower guide plate 112 between the plurality of openings 115 through which the second probe pins 103b and the third probe pins 103c extend. In some embodiments, each second continuous section 1142 on the upper guide plate 111 and the lower guide plate 112 may extend between all of the openings 115 through which the second probe pins 103b and the third probe pins 103c extend.

[0088] Various alternative configurations of the adhesive layer 114 on the upper surfaces of the upper guide plate 111 and / or the lower guide plate 112 are also within the contemplated scope of the present invention. For example, the adhesive layer 114 may include at least three continuous sections, wherein a first continuous section may extend between the plurality of openings 115 through which the first probe pins 103a extend, a second continuous section may extend between the plurality of openings 115 through which the second probe pins 103b extend, and a third continuous section may extend between the plurality of openings 115 through which the third probe pins 103c extend. Alternatively, the first continuous section may extend between the plurality of openings 115 through which the first probe pins 103a and the third probe pins 103c extend, and the second continuous section may extend between the plurality of openings 115 through which the second probe pins 103b extend.

[0089] The adhesion layer 114 can be deposited on the upper guide plate 111 and / or the lower guide plate 112 using a suitable deposition process, such as physical vapor deposition (PVD) (e.g., sputtering), electrochemical deposition (e.g., electroplating), and / or a printing process (e.g., a metal 3D printing process). Other suitable deposition processes are also within the contemplation of the present invention. In some embodiments, the adhesion layer 114 can be deposited on the upper guide plate 111 and / or the lower guide plate 112 in a desired pattern of continuous segments and gaps 118. Alternatively, a continuous coating of conductive material can be deposited on the upper guide plate 111 and / or the lower guide plate 112, and selected portions of the coating can be subsequently removed using a suitable technique (e.g., etching through a photolithographically patterned mask, a lift-off process, a laser ablation process, etc.) to provide the desired pattern of continuous segments and gaps 118 of the adhesion layer 114.

[0090] Reference again Figure 1 , a low dielectric constant material (i.e., low-k material) layer 116 may be formed on the adhesion layer 114 in portions of the upper guide plate 111 and the lower guide plate 112. The low dielectric constant material layer 116 may be composed of a material having a lower dielectric constant than the material of the upper guide plate 111 and the lower guide plate 112. For example, the upper guide plate 111 and the lower guide plate 112 may be composed of a ceramic material and may have a dielectric constant (k) greater than 8. The low dielectric constant material layer 116 may be composed of an insulating material having a dielectric constant (k) less than 8 (e.g., 7 or less, including less than 3.6). Materials suitable for the low dielectric constant material layer 116 may include, but are not limited to, diamond-like carbon (DLC) and / or pure silica zeolite. Other materials suitable for the low dielectric constant material layer 116 are also within the intended scope of the present invention.

[0091] refer to Figure 1 , the low dielectric constant material layer 116 may be located within the openings 115 in the upper guide plate 111 and the lower guide plate 112 through which the third probe pins 103c1 and 103c2 extend in the assembled probe head 110. The low dielectric constant material layer 116 may also be formed on portions of the upper surfaces of the upper guide plate 111 and the lower guide plate 112 surrounding the openings 115 through which the third probe pins 103c1 and 103c2 extend. Figure 1 In the embodiment shown, the low dielectric constant material layer 116 may form a continuous section over the upper surfaces of the upper guide plate 111 and the lower guide plate 112 extending between the openings 115 through which the third probe pins 103c1 and 103c2 extend. Figure 1As shown, the side surface and collar 109 of each of the third probe pins 103c1 and 103c2 can contact and / or be adjacent to the low-k material layer 116 in the assembled probe head. Thus, the low-k material layer 116 can be located between the third probe pins 103c1 and 103c2 and the upper and lower guide plates 111 and 112. Direct contact between the third probe pins 103c1 and 103c2 and the relatively high-k material of the upper and lower guide plates 111 and 112 can be avoided. This can provide improved signal integrity (SI) for the loopback test signal transmitted through the third probe pins 103c1 and 103c2.

[0092] In various embodiments, the low-k material layer 116 may be formed over the adhesion layer 114 such that the adhesion layer 114 is located between the low-k material layer 116 and the respective upper and lower guide plates 111 and 112. The adhesion layer 114 may promote adhesion of the low-k material layer 116 to the upper and lower guide plates 111 and 112, and may also provide enhanced shielding between the third probe pins 103 c and the high-k material of the upper and lower guide plates 111 and 112. In other embodiments, the low-k material layer 116 may be formed directly on the upper and lower guide plates 111 and 112.

[0093] In some embodiments, in addition to or in place of the third probe pins 103c1 and 103c2, a low-k material layer 116 may be located between the upper guide plate 111 and / or the lower guide plate 112 and other probe pins of the probe card 117. For example, the low-k material layer 116 may be located between the first probe pin 103a and / or the second probe pin 103b and the guide plates 111 and 112, e.g., within openings 115 in the guide plates 111 and 112 through which the respective probe pins 103a and 103b extend.

[0094] The low dielectric constant material layer 116 can be deposited using a suitable deposition process, such as physical vapor deposition (PVD) (e.g., sputtering). Other suitable deposition processes are also within the contemplation of the present invention. In some embodiments, the low dielectric constant material layer 116 can be deposited on the upper guide plate 111 and / or the lower guide plate 112 in a desired pattern. Alternatively, a continuous coating of low dielectric constant (k) material can be deposited on the upper guide plate 111 and / or the lower guide plate 112, and selected portions of the coating can be subsequently removed via a suitable technique (e.g., etching through a photolithographically patterned mask, a lift-off process, a laser ablation process, etc.) to provide the desired pattern of the low dielectric constant material layer 116.

[0095] Reference again Figure 1In various embodiments, the first continuous section 1141 of the adhesion layer 114 can electrically couple the plurality of first carbon pins 103a, thereby electrically shorting the plurality of power connections to the device under test 101. In some embodiments, all of the first carbon pins 103a in the probe head 110 can be electrically coupled via the first continuous section 1141 of the adhesion layer 114. Alternatively or additionally, the second continuous section 1142 of the adhesion layer 114 can electrically couple the plurality of second probe pins 103b, thereby electrically shorting the plurality of ground connections to the device under test 101. In some embodiments, all of the second probe pins 103b in the probe head 110 can be electrically coupled via the second continuous section 1142 of the adhesion layer 114. The low-k dielectric constant material layer 116 surrounding each of the third probe pins 103c1 and 103c2 can prevent the third probe pins 103c1 and 103c2 from being electrically connected to (i.e., electrically shorted to) the second probe pins 103b via the second continuous section 1142 of the adhesion layer 114. Electrically shorting the plurality of first carbon needle pins 103 a and / or the plurality of second probe pins 103 b within the probe head 110 may help balance current peaks and may enable more efficient thermal management in the in-circuit probe test system.

[0096] Figure 2 FIG. 1 is a vertical cross-sectional view of a portion of a circuit probe testing system 100 according to another embodiment of the present invention. Figure 2 The circuit probe test system 100 shown in FIG. 1 may be similar to the circuit probe test system 100 shown in FIG. Figure 1 The circuit probe testing system 100 is described. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Figure 2 The circuit probe test system 100 with Figure 1 The circuit probe test system 100 is different in that the length of the third probe pins 103c1 and 103c2 (i.e., loopback probe pins 103c1 and 103c2) can be smaller than the length of the first probe pin 103a and the second probe pin 103b. In some embodiments, the length of the first probe pin 103a and the second probe pin 103b can be between 4 mm and 7 mm, while the length of the third probe pins 103c1 and 103c2 can be less than 4 mm, for example, less than 2 mm, including 1 mm or less.

[0097] Figure 2 The circuit probe test system 100 with Figure 1The circuit probe test system 100 is also different in that the loopback signal path P may not be routed through the substrate portion 119 of the probe card 117, but may be routed through the conductive traces 108 located on and / or in the upper guide plate 111 and / or the lower guide plate 112 of the probe head 110. Figure 2 In the illustrated embodiment, the loopback signal path P can extend from the first contact area 1041 on the device under test 101 through the third loopback probe pin 103c1, along the conductive trace 108 located on the lower surface of the upper guide plate 111 and electrically connected to the third loopback probe pin 103c1, to another third loopback probe pin 103c2, and then extend through the third loopback probe pin 103c2 to the second contact area 1042 on the device under test 101. Therefore, Figure 2 The loopback signal path P shown in FIG can be compared to Figure 1 The loopback signal path in the illustrated embodiment is short. The relatively short length of the loopback signal path P can help improve signal integrity SI during circuit probe loopback testing.

[0098] exist Figure 2 In the illustrated embodiment, the conductive traces 108 are shown on the lower surface of the upper guide plate 111. However, in other embodiments, the conductive traces 108 may be located in another portion of the probe head 110, such as on the upper surface of the upper guide plate 111 or on the surface of the lower guide plate 112. Figure 2 , only a single conductive trace 108 is shown, but the probe head 110 may include multiple conductive traces 108 that can be electrically coupled to the third probe pins 103 c and extend between the third probe pins 103 c. Each conductive trace 108 can be used to electrically connect multiple contact areas 104 of the device under test 101 in series and / or in parallel during circuit probe loopback testing.

[0099] As referenced above Figure 1 In the depicted embodiment, an adhesive layer 114 may be formed within each opening 115 extending through the upper guide plate 111 and the lower guide plate 112. A first continuous section 1141 and a second continuous section 1142 of the adhesive layer 114 may be located on the upper surface of the upper guide plate 111 and the upper surface of the lower guide plate 112. Additionally, a third continuous section 1143 may be located on the lower surface of the upper guide plate 111. In some embodiments, the continuous sections 1141, 1142, and 1143 of the adhesive layer 114 may electrically couple the plurality of first probe pins 103a and / or the plurality of second probe pins 103b.

[0100] The low-k material layer 116 can be positioned within the opening 115 in the lower guide plate 112 through which the third probe pin 103c extends in the assembled probe head 110. The low-k material layer 116 can also be formed on a portion of the upper surface of the lower guide plate 112 surrounding the opening 115 through which the third probe pin 103c extends. The low-k material layer 116 can also be formed on a third continuous section 1143 of the adhesion layer 114 on the lower surface of the upper guide plate 111. The adhesion layer 114 can promote adhesion of the low-k material layer 116 and can also provide enhanced shielding between the third probe pins 103c1 and 103c2 and the conductive trace 108 and the high-k material of the upper and lower guide plates 111 and 112.

[0101] The conductive traces 108 may be formed on the low dielectric constant material layer 116 on the lower surface of the upper guide plate 111. The conductive traces may include metal materials such as copper, gold, nickel, tungsten, cobalt, molybdenum, ruthenium, etc., including alloys and combinations thereof. The conductive traces 108 may be formed using a suitable deposition technique as described above. Figure 2 In the illustrated embodiment, an upper surface of the third probe pin 103 c may contact a lower surface of the conductive trace 108 .

[0102] Reference again Figure 2 , the third probe pins 103c1 and 103c2 may extend through the openings 115 in the lower guide plate 112 but not through the upper guide plate 111. Therefore, the portion of the upper guide plate 111 above the third probe pins 103c1 and 103c2 may be made thicker to provide increased mechanical strength.

[0103] Figure 3 FIG. 2 is a vertical cross-sectional view of a circuit probe testing system 100 according to yet another embodiment of the present invention. Figure 3 The circuit probe test system 100 shown in FIG. 1 may be similar to the circuit probe test system 100 shown in FIG. Figure 2 The circuit probe testing system 100 is described. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Figure 3 The circuit probe test system 100 with Figure 2 The circuit probe test system 100 is different in that the upper guide plate 111 comprises a two-piece construction, including an upper portion 111a and a lower portion 111b. In some embodiments, Figure 3 The circuit probe test system 100 can also be considered as having a two-piece construction of the lower guide plate 112, including an upper portion 111b (112a) and a lower portion 112b. In other words, the lower portion 111b of the upper guide plate 111 can be referred to as the upper portion of the lower guide plate 112. For simplicity, the middle portion will be referred to herein as the lower portion 111b of the upper guide plate 111.

[0104] The spacer 113 may be located between the upper portion 111a and the lower portion 111b of the upper guide plate 111. An opening 115 may extend through the upper portion 111a and the lower portion 111b of the upper guide plate 111. The first probe pin 103a and the second probe pin 103b may extend through the openings 115 in the upper portion 111a and the lower portion 111b of the upper guide plate 111. An adhesive layer 114 may be located within each opening 115 in the upper portion 111a and the lower portion 111b of the upper guide plate 111.

[0105] In some embodiments, the adhesive layer 114 may be formed within the openings 115 extending through the upper portion 111a and the lower portion 111b of the upper guide plate 111, and within the openings 115 extending through the lower guide plate 112. A first continuous section 1141 and a second continuous section 1142 of the adhesive layer 114 may be located on the upper surfaces of the upper portion 111a and the lower portion 111b of the upper guide plate 111, as well as on the upper surface of the lower guide plate 112. Additionally, a third continuous section 1143 may be located on the lower surface of the lower portion 111b of the upper guide plate 111. In some embodiments, the continuous sections 1141, 1142, and 1143 of the adhesive layer 114 may electrically couple the plurality of first probe pins 103a and / or the plurality of second probe pins 103b.

[0106] The low-k material layer 116 may be located within the openings 115 in the lower guide plate 112 through which the third probe pins 103c1 and 103c2 extend in the assembled probe head 110. The low-k material layer 116 may also be formed on a portion of the upper surface of the lower guide plate 112 surrounding the openings 115 through which the third probe pins 103c1 and 103c2 extend. The low-k material layer 116 may also be formed on the third continuous section 1143 of the adhesive layer 114 on the lower surface of the lower portion 111b of the upper guide plate 111.

[0107] Figure 3 The loopback signal path P in the embodiment of the present invention can be similar to the above reference Figure 2 The loopback signal path P is described. That is, the loopback signal path P can extend from the first contact area 1041 on the device under test 101 through the third loopback probe pin 103c1, along the conductive trace 108 located on the lower surface of the lower portion 111b of the upper guide plate 111, to another third loopback probe pin 103c2, and then extend through the third loopback probe pin 103c2 to the second contact area 1042 on the device under test 101. Therefore, the third loopback probe pin 103c may not extend through the upper portion 111a or the lower portion 111b of the upper guide plate 111.

[0108] Figure 4AFIG. 2 is a vertical cross-sectional view of a circuit probe testing system 100 according to yet another embodiment of the present invention. Figure 4A The circuit probe test system 100 shown in FIG. 1 may be similar to the circuit probe test system 100 shown in FIG. Figure 3 The circuit probe testing system 100 is described. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Figure 4A The circuit probe test system 100 with Figure 3 The circuit probe test system 100 is different in that the adhesion layer 114 and the low dielectric constant material layer 116 can be provided on the third loopback probe pins 103c1 and 103c2 (see Figure 4D The adhesion layer 114 and the low-k material layer 116 on the third loopback probe pins 103c1 and 103c2 may be made of the same or similar materials as the adhesion layer 114 and the low-k material layer 116 formed on the upper guide plate 111 and the lower guide plate 112 of the probe head 110. The adhesion layer 114 and the low-k material layer 116 may be formed on the third loopback probe pins 103c1 and 103c2 in addition to or in place of the adhesion layer 114 and the low-k material layer 116 formed on the upper guide plate 111 and the lower guide plate 112.

[0109] refer to Figure 4A The adhesion layer 114 and the low-k material layer 116 may be formed on portions of the third loopback probe pins 103c1 and 103c2 in the assembled probe head 110 that are adjacent to the relatively high-k material of the lower guide plate 112 and / or the upper guide plate 111. Thus, the adhesion layer 114 and the low-k material layer 116 may be located between the conductive material of the third loopback probe pins 103c1 and 103c2 and the high-k material of the lower guide plate 112 and / or the upper guide plate 111.

[0110] In other embodiments, the adhesion layer 114 and the low dielectric constant (k) material layer 116 may be formed on portions of additional probe pins (eg, the first probe pin 103 a and / or the second probe pin 103 b ) of the circuit probe testing system 100 .

[0111] Figures 4B to 4D is the third probe pin 103c (ie, Figure 4A 1 and 103c2 in the third probe pins 103c1 and 103c2) sequential vertical cross-sectional view showing the process of forming an adhesion layer 114 and a low dielectric constant (k) material layer 116 on a portion of the third probe pin 103c. Figure 4BThe third probe pin 103c may include an elongated structure comprising a conductive material. The third probe pin 103c may also include a collar portion 109 comprising a conductive material, which may be used to secure the third probe pin 103c within an opening 115 passing through the upper guide plate 111 and the lower guide plate 112 of the probe head 110. Figure 4C , an adhesion layer 114 may be formed over a portion of the third probe pin 103c by a suitable deposition process as described above. Figure 4D , a low dielectric constant (k) material layer 116 may be formed over the adhesion layer 114 using a suitable deposition process as described above. The adhesion layer 114 and the low dielectric constant material layer 116 may be formed over one or more regions of the third probe pin 103c that may be adjacent to or in contact with the relatively high dielectric constant material of the lower guide plate 112 and / or the upper guide plate 111. In some embodiments, the adhesion layer 114 may be omitted, and the low dielectric constant material layer 116 may be formed directly over one or more portions of the third probe pin 103c. However, providing the adhesion layer 114 between the third probe pin 103c and the low dielectric constant material layer 116 may promote adhesion of the low dielectric constant material layer 116 to the third probe pin 103c, and may also provide enhanced shielding between the third probe pin 103c and the high dielectric constant material of the lower guide plate 112 and / or the upper guide plate 111.

[0112] It should be understood that the third probe pin 103c including the low dielectric constant material layer 116 located on one or more portions of the third probe pin 103c may also be used for Figure 1 or Figure 2 In the circuit probe test system 100 shown. Figure 1 In the case of the circuit probe test system 100 shown, when the third probe pin 103c is assembled in the probe head 110, the third probe pin 103c may include a low dielectric constant material layer 116 and optionally an adhesion layer 114, which is located above the third probe pin 103c adjacent to the upper guide plate 111 and the lower guide plate 112.

[0113] Figure 5 FIG. 2 is a vertical cross-sectional view of a circuit probe testing system 100 according to yet another embodiment of the present invention. Figure 5 The circuit probe test system 100 shown in FIG. 1 may be similar to the circuit probe test system 100 shown in FIG. Figure 3 The circuit probe testing system 100 is described. Therefore, for the sake of brevity, repeated discussion of the same elements is omitted. Figure 5 The circuit probe test system 100 with Figure 3The circuit probe test system 100 differs in that the lower guide plate 112 also includes a two-piece construction, including an upper portion 112a and a lower portion 112b. A spacer 113 may be located between the upper portion 112a and the lower portion 112b of the lower guide plate 112. An opening 115 may extend through the upper portion 112a and the lower portion 112b of the lower guide plate 112. The first probe pin 103a and the second probe pin 103b may extend through the openings 115 in the upper portion 112a and the lower portion 112b of the lower guide plate 112. An adhesive layer 114 may be located within each opening 115 in the upper portion 112a and the lower portion 112b of the lower guide plate 112.

[0114] In some embodiments, the adhesive layer 114 may be formed within the opening 115 extending through the upper portion 111a and the lower portion 111b of the upper guide plate 111, and within the opening 115 extending through the upper portion 112a and the lower portion 112b of the lower guide plate 112. The first continuous section 1141 and the second continuous section 1142 of the adhesive layer 114 may be located on the upper surfaces of the upper portion 111a and the lower portion 111b of the upper guide plate 111, and on the upper surfaces of the upper portion 112a and the lower portion 112b of the lower guide plate 112. Additionally, the third continuous section 1143 may be located on the lower surface of the upper portion 112a of the lower guide plate 112. In some embodiments, the first continuous section 1141, the second continuous section 1142, and / or the third continuous section 1143 of the adhesive layer 114 may electrically couple the plurality of first probe pins 103a and / or the plurality of second probe pins 103b.

[0115] The low-k material layer 116 may be located within the openings 115 in the lower portion 112b of the lower guide plate 112 through which the third probe pins 103c1 and 103c2 extend in the assembled probe head 110. The low-k material layer 116 may also be formed on a portion of the upper surface of the lower portion 112b of the lower guide plate 112 surrounding the openings 115 through which the third probe pins 103c1 and 103c2 extend. The low-k material layer 116 may also be formed on the third continuous section 1143 of the adhesive layer 114 on the lower surface of the upper portion 112a of the lower guide plate 112.

[0116] The loopback signal path P may extend from the first contact area 1041 on the device under test 101 through the third loopback probe pin 103c1, along the conductive trace 108 located on the lower surface of the upper portion 112a of the lower guide plate 112, to another third loopback probe pin 103c2, and then extend through the third loopback probe pin 103c2 to the second contact area 1042 on the device under test 101. Therefore, the third loopback probe pins 103c1 and 103c2 may extend through the lower portion 112b of the lower guide plate 112, but may not extend through the upper portion 112a of the lower guide plate 112, the lower portion 111b of the upper guide plate 111, or the upper portion 111a of the upper guide plate 111.

[0117] Figure 6 1 to 4A, 5, and 6, in step 201 of method 200, a low-k material layer 116 may be formed within openings 115 extending through guide plates 111 and 112, wherein the low-k material layer 116 has a dielectric constant less than that of the guide plates 111 and 112. Referring to Figures 1 to 4A, 5 and 6, in step 203 of method 200, the guide plates 111 and 112 can be assembled into a probe card 117, which includes a substrate portion 119, guide plates 111 and 112 arranged below the substrate portion 119, and a plurality of probe pins 103c1 and 103c2 extending through openings 115 in the guide plates 111 and 112, wherein a low dielectric constant material layer 116 is located between the probe pins 103c1 and 103c2 and the guide plates 111 and 112.

[0118] Figure 7 is a flow chart showing a method 210 for manufacturing probe pins 103a, 103b, 103c1, and 103c2 for a circuit probe test system 100 according to various embodiments of the present invention. Referring to Figures 4B to 4D and 7, in step 211 of method 210, an optional adhesion layer 114 may be formed on a portion of the probe pins 103a, 103b, 103c1, and 103c2 using a suitable deposition process, such as physical vapor deposition (PVD) (e.g., sputtering), electrochemical deposition (e.g., electroplating), and / or a printing process (e.g., a metal 3D printing process). Other suitable deposition processes are also within the intended scope of the present invention. The adhesion layer 114 may be formed on a portion of the probe pins 103a, 103b, 103c1, and 103c2 and the collar 109, as Figure 4C shown.

[0119] 4D and 7 , in step 212 of method 210, a layer of low-k dielectric constant material 116 can be formed on portions of probe pins 103a, 103b, 103c1, and 103c2, which can include collar 109, that are located adjacent to the relatively high-k dielectric constant material of lower guide plate 112 and / or upper guide plate 111 in the assembled probe head 110. Thus, an optional adhesion layer 114 and a layer of low-k dielectric constant material 116 can be located between the conductive material of probe pins 103a, 103b, 103c1, and 103c2 and the high-k dielectric constant material of lower guide plate 112 and / or upper guide plate 111. The layer of low-k dielectric constant material 116 can be formed on the portions of probe pins 103a, 103b, 103c1, and 103c2 using a suitable deposition process, such as physical vapor deposition (PVD) (e.g., sputtering). Other suitable deposition processes are also contemplated by the present invention.

[0120] 4B to 4D and 7 , in step 213 of method 210 , the guide plates 111 , 112 may be assembled into a probe card 117 , the probe card 117 including a substrate portion 119 , guide plates 111 , 112 disposed below the substrate portion 119 , and a plurality of probe pins 103 a , 103 b , 103 c 1 , and 103 c 2 extending through openings 115 in the guide plates 111 , 112 , wherein a low dielectric constant material layer 116 is located between the probe pins 103 a , 103 b , 103 c 1 , and 103 c 2 and the guide plates 111 , 112 .

[0121] The adhesion layer 114 and the low-k material layer 116 may be formed on one or more regions of the third probe pins 103c1 and 103c2 that may be adjacent to or in contact with the relatively high-k material of the lower guide plate 112 and / or the upper guide plate 111. In some embodiments, the adhesion layer 114 may be omitted, and the low-k material layer 116 may be formed directly on one or more portions of the third probe pins 103c1 and 103c2. However, providing an adhesion layer 114 between the probe pins 103a, 103b, 103c1 and 103c2 and the low dielectric constant material layer 116 can promote adhesion of the low dielectric constant material layer 116 to the probe pins 103a, 103b, 103c1 and 103c2, and can also provide enhanced shielding between the probe pins 103a, 103b, 103c1 and 103c2 and the high dielectric constant material of the lower guide plate 112 and / or the upper guide plate 111.

[0122] With reference to all drawings and in accordance with various embodiments of the present invention, a probe card 117 for a circuit probe testing system 100 includes a base portion 119, an upper guide plate 111, and a lower guide plate 112, and a plurality of probe pins 103a, 103b, 103c1, and 103c2, wherein the guide plates 111, 112 are located below the base portion 119 and include a plurality of openings 115 passing through the guide plates 111, 112, wherein the plurality of probe pins 103a, 103b, 103c1, and 103c2 extend through the openings 115 in the guide plates 111, 112. 1 and 103c2 include at least one first probe pin 103a configured to transmit power between a substrate portion 119 and a device under test (DUT) 101, at least one second probe pin 103b configured to electrically couple the DUT 101 to ground, and at least two third probe pins 103c1 and 103c2 configured to transmit a loopback test signal between a plurality of contact areas 104 on the DUT 101, wherein a low dielectric constant material layer 116 is located between the at least two third probe pins 103c and the guide plates 111 and 112, and the dielectric constant of the low dielectric constant material layer 116 is less than the dielectric constant of the guide plates 111 and 112.

[0123] In some embodiments, the guide plates 111 , 112 include a ceramic material having a dielectric constant greater than 8.

[0124] In some embodiments, the low dielectric constant material layer 116 includes at least one of diamond-like carbon and pure silica zeolite.

[0125] In some embodiments, the low dielectric constant material layer 116 is located within the opening 115 in the guide plates 111, 112 through which each of the at least two third probe pins 103c1 and 103c2 extends, and the low dielectric constant material layer 116 is not present within the opening 115 in the guide plates 111, 112 through which each first probe pin 103a and each second probe pin 103b extends.

[0126] In some embodiments, a low dielectric constant material layer 116 is located on a portion of the upper surface of the guide plates 111, 112 surrounding the opening 115 in the guide plates 111, 112 through which the at least two third probe pins 103c1 and 103c2 extend, and each of the at least two third probe pins 103c1 and 103c2 includes a feature 109 that protrudes radially outward from the third probe pins 103c1 and 103c2 and contacts the low dielectric constant material layer 116 located on the upper surface of the guide plates 111, 112.

[0127] In some embodiments, the guide plates 111, 112 include a lower guide plate 112 and an upper guide plate 111, the upper guide plate 111 includes a plurality of openings 115 passing through the upper guide plate 111 and is located between the substrate portion 119 and the lower guide plate 112, wherein the low dielectric constant material layer 116 is located between the at least two third probe pins 103c1 and 103c2 and the upper guide plate 111.

[0128] In some embodiments, the at least two third probe pins 103c1 and 103c2 extend through the opening 115 in the upper guide plate 111 and contact the substrate portion 119, and the conductive traces 108 located on and / or in the probe card 117 electrically couple the at least two third probe pins 103c1 and 103c2 to provide a loopback signal path P.

[0129] In some embodiments, the probe card 117 also includes a conductive trace 108 located on the surface of the guide plates 111 and 112, which electrically couples the at least two third probe pins 103c1 and 103c2 to provide a loopback signal path P, wherein the low dielectric constant material layer 116 is located between the conductive trace 108 and the surface of the guide plates 111 and 112.

[0130] In some embodiments, the probe card 117 further includes an adhesive layer 114 located between the low-k material layer 116 and the surfaces of the guide plates 111 and 112 , where the adhesive layer 114 includes a conductive material.

[0131] In some embodiments, the conductive traces 108 are located on the lower surface of the upper guide plate 111 .

[0132] In some embodiments, the lower guide plate 112 includes an upper portion 112 a and a lower portion 112 b , wherein the conductive trace 108 is located on a lower surface of the upper portion 112 a of the lower guide plate 112 , and the at least two third probe pins 103 c 1 and 103 c 2 extend through an opening 115 in the lower portion 112 b of the lower guide plate 112 .

[0133] In some embodiments, the probe card 117 further includes an adhesive layer 114 including a conductive material within the openings 115 in the guide plates 111 , 112 through which each of the at least two third probe pins 103 c 1 and 103 c 2 extends.

[0134] In some embodiments, the adhesive layer 114 is positioned within the openings 115 in the guide plates 111 , 112 through which each first probe pin 103 a and each second probe pin 103 b extend.

[0135] In some embodiments, the continuous section 1142 of the adhesive layer 114 is located on the surfaces of the guide plates 111 , 112 and electrically couples at least two second probe pins 103 b .

[0136] In some embodiments, the low-k material layer 116 is located between the guide plates 111 , 112 and the at least one first probe pin 103 a .

[0137] In some embodiments, the low-k material layer 116 is located over a portion of each of the at least two third probe pins 103 c 1 and 103 c 2 adjacent to the guide plates 111 , 112 .

[0138] Other embodiments relate to a probe head 110 for a circuit probe testing system 100, comprising guide plates 111, 112, a low-k material layer 116, a conductive trace 108, and a plurality of probe pins 103a, 103b, 103c1, and 103c2, wherein the guide plates 111, 112 include a plurality of openings 115 passing through the guide plates 111, 112, and the low-k material layer 116 is located on the surface of the guide plates 111, 112 and extends within the openings 115. 15, the dielectric constant of the low dielectric constant material layer 116 is smaller than the dielectric constant of the guide plates 111 and 112, the conductive trace 108 is located on the low dielectric constant material layer 116, and the plurality of probe pins 103a, 103b, 103c1 and 103c2 extend through the openings 115 in the guide plates 111 and 112, wherein the pair of probe pins 103c1 and 103c2 are electrically connected by the conductive trace 108 to form a loopback signal path P.

[0139] In some embodiments, the probe head 110 further includes an adhesion layer 114 located between the low dielectric constant material layer 116 and the surface of the guide plates 111, 112, and on the surface of the guide plates 111, 112, wherein the adhesion layer 114 includes a conductive material, wherein the adhesion layer 114 electrically couples at least two probe pins 103a, 103b extending through the opening 115 in the guide plates 111, 112.

[0140] Other embodiments relate to a method of manufacturing a probe card 117 for a circuit probe testing system 100, comprising forming a low-k material layer 116 within a plurality of openings 115 passing through guide plates 111, 112, wherein the dielectric constant of the low-k material layer 116 is less than the dielectric constant of the guide plates 111, 112, and assembling the guide plates 111, 112 into a probe card 117, the probe card 117 comprising a substrate portion 119, the guide plates 111, 112 disposed below the substrate portion 119, and a plurality of probe pins 103c1 and 103c2 extending through the openings 115 in the guide plates 111, 112, wherein the low-k material layer 116 is located between each of the probe pins 103c1 and 103c2 and the guide plates 111, 112.

[0141] In some embodiments, the method further includes forming an adhesion layer 114 comprising a conductive material in the opening 115 passing through the guide plates 111 and 112 , wherein the low dielectric constant material layer 116 is located on the adhesion layer 114 .

[0142] Other embodiments relate to a method of manufacturing probe pins 103a, 103b, 103c1, and 103c2 for use in a circuit probe test system 100, comprising forming a low-k material layer 116 on portions of the probe pins 103a, 103b, 103c1, and 103c2, wherein the low-k material layer 116 has a dielectric constant less than that of guide plates 111 and 112, and assembling the guide plates 111 and 112 into a probe card. 117, the probe card 117 includes a substrate portion 119, guide plates 111, 112 arranged below the substrate portion 119, and a plurality of probe pins 103a, 103b, 103c1 and 103c2 extending through openings 115 in the guide plates 111, 112, wherein a layer of low dielectric constant material 116 is located between each of the probe pins 103a, 103b, 103c1 and 103c2 and the guide plates 111, 112.

[0143] In some embodiments, the method further includes forming an adhesive layer 114 on the portions of the probe pins 103a, 103b, 103c1, and 103c2 that pass through the guide plates 111 and 112, the adhesive layer comprising a conductive material, wherein a low dielectric constant material layer 116 is formed on the adhesive layer 114, so that once the guide plates 111 and 112 are assembled into a probe card 117, the adhesive layer 114 and the low dielectric constant material layer 116 can be formed on the probe pins 103a, 103b, 103c1, and 103c2. The probe card 117 includes a substrate portion 119, guide plates 111, 112 disposed below the substrate portion 119, and a plurality of probe pins 103a, 103b, 103c1, and 103c2 extending through openings 115 in the guide plates 111, 112.

[0144] The above summarizes the features of many embodiments so that those skilled in the art to which the present invention belongs can better understand the various embodiments of the present invention. Those skilled in the art to which the present invention belongs should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or obtain the same advantages as the embodiments described herein. Those skilled in the art to which the present invention belongs should also understand that these equivalent structures do not depart from the concept and scope of the present invention. Various changes, substitutions and modifications can be made to the embodiments of the present invention without departing from the concept and scope of the appended claims.

Claims

1. A probe card for a circuit probe test system, characterized in that: include: a substrate portion; a guide plate positioned below the base portion, the guide plate including a plurality of openings extending through the guide plate; as well as a plurality of probe pins extending through the openings in the guide plate, the probe pins including at least one first probe pin configured to transmit power between the substrate portion and a device under test, at least one second probe pin configured to electrically couple the device under test to ground, and at least two third probe pins configured to transmit loopback test signals between a plurality of contact areas on the device under test, A low-k dielectric constant material layer is located between the at least two third probe pins and the guide plate. The dielectric constant of the low-k dielectric constant material layer is smaller than the dielectric constant of the guide plate.

2. The probe card according to claim 1, wherein The low dielectric constant material layer is located within the openings in the guide plate through which each of the at least two third probe pins extends, and the low dielectric constant material layer is not present within the openings in the guide plate through which each of the at least one first probe pin and each of the at least one second probe pin extend.

3. The probe card according to claim 1, wherein The low-k dielectric constant material layer is located on a portion of an upper surface of the guide plate surrounding the openings in the guide plate through which the at least two third probe pins extend, and each of the at least two third probe pins includes a feature that protrudes radially outward from the at least two third probe pins and contacts the low-k dielectric constant material layer located on the upper surface of the guide plate.

4. The probe card according to claim 1, wherein The guide plate includes a lower guide plate and an upper guide plate, the upper guide plate includes a plurality of openings passing through the upper guide plate and is located between the substrate portion and the lower guide plate, wherein the low dielectric constant material layer is located between the at least two third probe pins and the upper guide plate.

5. The probe card according to claim 4, wherein The at least two third probe pins extend through the openings in the upper guide plate and contact the substrate portion, and a conductive trace on and / or in the probe card electrically couples the at least two third probe pins to provide a loopback signal path.

6. The probe card according to claim 4, wherein Also included is a conductive trace on a lower surface of the upper guide plate, the conductive trace electrically coupling the at least two third probe pins to provide a loopback signal path, wherein the low dielectric constant material layer is located between the conductive trace and the surface of the guide plate.

7. The probe card according to claim 1, wherein It also includes an adhesion layer located within the openings in the guide plate through which each of the at least two third probe pins extends, the adhesion layer comprising at least a conductive material, wherein the adhesion layer is located within the openings in the guide plate through which each of the at least one first probe pin and each of the at least one second probe pin extends, wherein a continuous section of the adhesion layer is located on a surface of the guide plate and electrically couples the at least two second probe pins.

8. The probe card according to claim 1, wherein The low dielectric constant material layer is located between the guide plate and the at least one first probe pin, and the low dielectric constant material layer is located on a portion of each of the at least two third probe pins adjacent to the guide plate.

9. A probe head for a circuit probe test system, characterized in that: include: a guide plate comprising a plurality of openings passing through the guide plate; a low-k dielectric constant material layer located on a surface of the guide plate and extending between a pair of the openings, the low-k dielectric constant material layer having a dielectric constant lower than that of the guide plate; a conductive trace located on the low dielectric constant material layer; as well as A plurality of probe pins extend through the openings in the guide plate, wherein a pair of probe pins among the probe pins are electrically connected by the conductive trace to form a loopback signal path.

10. The probe head according to claim 9, wherein: Also included is an adhesion layer located between the low dielectric constant material layer and the surface of the guide plate and above the surface of the guide plate, the adhesion layer comprising a conductive material, wherein the adhesion layer electrically couples at least two of the probe pins extending through the openings in the guide plate.

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