Chip layout structure, chip and electronic equipment

Abstract

The utility model discloses a chip layout structure, a chip and an electronic device, the chip layout structure comprises a corresponding digital area, and the digital area of the chip layout structure comprises a digital module which comprises a plurality of groups of top metal used for supplying power to a power ground; the memory interface modules are positioned on two sides of the digital module and are used for controlling and managing memory interfaces; wherein the digital area of the chip layout structure further comprises a first wiring grid, and the first wiring grid penetrates through the digital module in the extending direction perpendicular to the top layer metal in the digital module. A simulation layout is supplemented in a digital module area, and a simulation wiring layer can be used according to a bonding pad coordinate and a surrounding environment, so that convenience is provided for realizing comprehensive optimization and layout wiring planning of a layer.

Description

Technical Field

[0001] The utility model relates to the field of integrated circuit chip design, in particular to a chip layout structure, a chip, and an electronic device. Background Art

[0002] Floorplan in chip design, or layout planning, is a key step in the integrated circuit design process, used to determine and configure the location of logic modules on the physical chip. The goal of this process is to optimize the chip layout to minimize signal delays, improve performance, and reduce power consumption. Floorplan involves defining factors such as chip size, module arrangement, I / O location, and power distribution, all of which affect the performance and power consumption of the chip. Through reasonable floorplan design, the performance, power consumption, and area of ​​the chip can be optimized, and the production yield can be improved. Only after the floorplan stage is completed can subsequent layout and routing work be carried out, so its quality and accuracy are crucial to the entire chip design.

[0003] In this process, the digital part usually completes the relevant design, but some layout planning digital layout designs in related technologies have shortcomings, such as wiring planning can only be done on limited layers, such as Figure 1 As shown, in existing chip layouts, the digital area can only be laid out up to the MTT2 layer. MTT2 is the top metal layer (thick copper), the uppermost layer of copper wiring in the chip. The upper wiring ALPA of the top metal layer MTT2 is aluminum wiring, generally used to supply power to the power ground. Due to this, the optimization and layout planning of some layers are not comprehensive, which also affects subsequent chip design.

[0004] ‌ Utility Model Content

[0005] In view of the above problems, the purpose of the present invention is to provide a chip layout structure, chip, and electronic device, so as to fill in the analog layout in the digital module area. Compared with the digital layout wiring, the analog layout can see all the layers of the entire chip, and the analog wiring layer can be used according to the pad coordinates and the surrounding environment.

[0006] According to one aspect of the present invention, a chip layout structure is provided, which includes a corresponding digital area, characterized in that the digital area of ​​the chip layout structure includes: a digital module, including multiple groups of top-level metal for supplying power to a power ground; a memory interface module, located on both sides of the digital module, for controlling and managing the memory interface; wherein the digital area of ​​the chip layout structure also includes a first wiring grid, which penetrates the digital module along an extension direction perpendicular to the top-level metal in the digital module.

[0007] Preferably, the first wiring grid includes multiple groups of wirings, which are connected to the multiple groups of top-layer metals through through-holes to achieve vertical connection between the multiple groups of top-layer metals distributed laterally.

[0008] Preferably, the memory interface module includes a power supply layer, and the power supply layer is used to provide voltage to the memory interface module.

[0009] Preferably, the digital area of ​​the chip layout structure also includes a second wiring grid, which includes a first part that passes through the digital module along an extension direction perpendicular to the top metal layer in the digital module, and a second part corresponding to the power supply layer in the above-mentioned memory interface module.

[0010] Preferably, the first portion and the second portion of the second wiring grid form an I-shape to connect the power supply layers of the memory interface modules located on both sides of the digital module.

[0011] Preferably, the first wiring grids are multiple groups.

[0012] Preferably, the first wiring grid and the second wiring grid include components in a circuit and connection relationships between them.

[0013] Preferably, the plurality of first wiring grids are arranged on both sides of the second wiring grid.

[0014] According to another aspect of the present invention, a chip is provided, comprising any one of the chip layout structures described above.

[0015] According to another aspect of the present invention, an electronic device is provided, comprising: a display panel; and the chip as described above, for providing driving and / or touch signals to the display panel.

[0016] The application provided by the utility model fills the digital area with an analog layout. By comparing the digital layout wiring, the analog layout can see all the layers of the entire chip, and the analog wiring layer can be used according to the pad coordinates and the surrounding environment, thereby facilitating the comprehensive optimization of the layer and layout wiring planning. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0018] Figure 1 FIG. 4 shows a chip layout structure according to the prior art.

[0019] Figure 2 The chip layout structure according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0020] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements or modules are represented by identical or similar reference numerals. For clarity, the various parts in the accompanying drawings are not drawn to scale.

[0021] Furthermore, certain terms are used in this patent specification and claims to refer to specific components. Those skilled in the art will appreciate that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not distinguish components based on differences in name, but rather on differences in their functionality.

[0022] In this application, the term "semiconductor structure" refers collectively to the entire semiconductor structure formed during the various steps of manufacturing a memory device, including all formed layers or regions. Numerous specific details of the present invention, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present invention. However, as will be appreciated by those skilled in the art, the present invention may be practiced without adherence to these specific details.

[0023] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0024] Figure 2 The chip layout structure according to an embodiment of the present invention is shown.

[0025] like Figure 2 As shown, the digital area in the chip layout structure includes, for example, a digital module 1 , a memory interface module 2 , a first wiring grid 3 and a second wiring grid 4 .

[0026] The digital module 1 in the digital area of ​​the chip layout, for example, includes multiple layers of MTT2. MTT2 is the top metal (thick copper), the uppermost layer of copper wiring in the chip. The upper wiring ALPA of MTT2 is aluminum wiring. Multiple layers of this top metal MTT2 are distributed throughout the digital module 1, providing power to the power ground. The memory interface module 2 (Double Data Rate PHY) is the physical layer interface for controlling and managing the DDR (Double Data Rate) memory interface. It bridges the gap between the DDR chips and the DDR controller, converting data sent by the DDR controller into signals that conform to the DDR protocol and sending them to the DDR chips. Conversely, it converts data sent from the DRAM into signals that conform to the DFI protocol and sends them to the memory controller. The memory interface module 2 is located on both sides of the digital module 1, for example.

[0027] The memory interface module 2 also includes a power supply layer VDD. In the design, the power supply layer VDD of the DDR PHY provides a stable voltage to ensure the normal operation of the DDR memory controller. In one embodiment, the power supply layer VDD provides a 1.8V voltage to the memory interface module 2.

[0028] In addition, the digital area of ​​the chip layout structure according to the embodiment of the present invention further includes a first wiring grid 3 and a second wiring grid 4 .

[0029] The first wiring grid 3 runs through the digital module 1 perpendicular to the direction in which the top metal MTT 2 extends, thereby providing a grid-like reinforcement for the power ground of the digital module 1 itself. The first wiring grid 3 represents the components (such as resistors, capacitors, inductors, etc.) in the circuit and their connections as a grid structure. Calculations performed on the grid simulate parameters such as current and voltage in the circuit. Circuits can be designed by placing components and connecting them on the grid, and their performance can be analyzed through simulation. In one embodiment, the first wiring grid 3 includes multiple groups of wiring, which are electrically connected to the multiple top metal MTTs 2 in the digital module through perforations, interconnecting the multiple groups of top metal MTTs 2 in the digital module and achieving vertical connection between the power ground lines connected through the multiple groups of top metal.

[0030] The second wiring grid 4 includes a first portion extending perpendicularly to the extension direction of the top metal MTT 2 in the digital module 1 and a second portion corresponding to the power supply layer in the memory interface module 2. The second wiring grid 4 is in an I-shape. By adding the second wiring grid 4, the blank space in the second wiring grid 4 in the digital module area is utilized to connect the power supply layers in the memory interface module 2 located inwardly above and below.

[0031] The difference between the above-mentioned second wiring grid 4 and the second wiring grid 3 is that the second wiring grid 4 only occupies the area in the digital module 1 and is not connected to the top metal MTT 2 in the digital module 1 through punching. Instead, it only connects the power supply layers in the memory interface modules 2 on both sides of the digital module 1 through wiring.

[0032] In another aspect of this embodiment, a chip is provided, including the above chip layout structure.

[0033] This application adds an analog layout to the digital area and compares the digital layout wiring. The analog layout can see all the layers of the entire chip and can use the analog wiring layer according to the pad coordinates and the surrounding environment, thereby facilitating the comprehensive optimization of the layer and layout and wiring planning.

[0034] It should be noted that those skilled in the art will understand that the terms "during," "when," and "when..." used herein in connection with circuit operation are not strict terms indicating an action that occurs immediately upon the start of an initiation action. Rather, there may be some small but reasonable delay or delays between the initiation action and the reaction action initiated by the initiation action, such as various transmission delays. The terms "approximately" or "substantially" are used herein to indicate that an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that make it difficult for the value or position to be strictly the stated value. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive logic or negative logic is used.

[0035] While the embodiments of the present invention are described above, these embodiments do not exhaustively describe all details, nor do they limit the present invention to specific embodiments. Clearly, many modifications and variations are possible based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, thereby enabling those skilled in the art to better utilize the present invention and its modifications. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention and their equivalents.

Claims

1. A chip layout structure, comprising corresponding digital areas, characterized in that: The digital area of ​​the chip layout structure includes: a digital module including multiple sets of top metal for supplying power ground; Memory interface module, located on both sides of the digital module, is used to control and manage the memory interface; The digital area of ​​the chip layout structure further includes a first wiring grid, and the first wiring grid penetrates the digital module along an extension direction perpendicular to the top metal layer in the digital module.

2. The chip layout structure according to claim 1, characterized in that: The first wiring grid includes multiple groups of wirings connected to the multiple groups of top metals through through holes to achieve vertical connections between horizontal power ground lines respectively connected to the multiple groups of top metals.

3. The chip layout structure according to claim 2, characterized in that: The memory interface module includes a power supply layer, and the power supply layer is used to provide voltage to the memory interface module.

4. The chip layout structure according to claim 3, characterized in that: The digital area of ​​the chip layout structure also includes a second wiring grid, The second wiring grid includes a first portion extending perpendicularly to an extension direction of the top metal layer in the digital module and a second portion corresponding to the power supply layer in the memory interface module.

5. The chip layout structure according to claim 4, characterized in that: The wiring of the first part and the second part of the second wiring grid form an I-shape, connecting the power supply layers of the memory interface modules located on both sides of the digital module.

6. The chip layout structure according to claim 5, characterized in that: There are multiple first wiring grids.

7. The chip layout structure according to claim 6, characterized in that: The first wiring grid and the second wiring grid also include components in the circuit and the connection relationship between them.

8. The chip layout structure according to claim 7, characterized in that: The plurality of first wiring grids are arranged on both sides of the second wiring grid.

9. A chip, characterized in that: The chip layout structure comprises the chip layout structure according to any one of claims 1 to 8.

10. An electronic device, characterized in that: include: Display panel; as well as The chip as claimed in claim 9, used to provide driving and / or touch signals to the display panel.

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