Semiconductor packaging bridging structure

Abstract

The utility model discloses a semiconductor packaging bridging structure, which comprises a support limiting frame, a substrate, chip bodies, a dielectric material layer, a wiring layer, a support column, a plastic packaging layer and an RDL adding layer, the substrate is embedded in the support limiting frame, the upper end face of the substrate is fixedly provided with an embedded groove, the chip bodies of different types are embedded in the embedded groove, and the chip bodies of different types are embedded in the RDL adding layer. A dielectric material layer is fixedly arranged on the upper end face of the substrate, a pattern groove is formed in the dielectric material layer, a wiring layer is arranged in the pattern groove, a supporting column is fixedly arranged on the upper end face of the wiring layer, a plastic packaging layer is fixedly arranged on the upper end face of the dielectric material layer, an RDL adding layer is arranged on the upper end face of the plastic packaging layer, and the RDL adding layer is fixedly connected with the supporting column. According to the utility model, different types of chips are pre-arranged on the substrate, then the chips are fixed through the dielectric material, and the RDL connected with the chips is formed on the dielectric material layer through windowing and electroplating, so that the overall yield of the central layer structure of the final packaging substrate is improved, and the reliability of the structure is improved.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor packaging substrates, in particular to a semiconductor packaging bridge structure. Background Art

[0002] In SIP packaging (chiplet), the connection between different chips is achieved through interposer transfer. Existing interposer production can only be done at the wafer (Fab) level, which is costly. In addition, the interposer has poor compatibility with board-level materials, which can easily cause the finished package to fail.

[0003] This solution embeds the chip wafer inside the board-level frame, fixes it with board-level high-resolution photosensitive material, and connects different chips in different areas through fine electroplating. It replaces the interposer and converts the interposer from a wafer-level manufacturing process to a board-level manufacturing process, reducing the risk of failure of the packaged finished product. Utility Model Content

[0004] The main purpose of the utility model is to provide a semiconductor packaging bridge structure.

[0005] In order to achieve the above purpose, the technical solution adopted by the utility model is:

[0006] A semiconductor packaging bridge structure includes a support and limiting frame, a substrate, a chip body, a dielectric material layer, a wiring layer, a support column, a plastic encapsulation layer and an RDL build-up layer. The support and limiting frame is embedded with the substrate, the upper end surface of the substrate is fixedly provided with an embedding groove, and different types of chip bodies are embedded in the embedding groove. The upper end surface of the substrate is fixedly provided with a dielectric material layer, the dielectric material layer is provided with a pattern groove, and a wiring layer is provided in the pattern groove. The wiring layer is fixedly connected to the input and output ends of the chip body, the upper end surface of the wiring layer is fixedly provided with a support column, the upper end surface of the dielectric material layer is fixedly provided with a plastic encapsulation layer, the upper end surface of the plastic encapsulation layer is provided with an RDL build-up layer, and the RDL build-up layer is fixedly connected to the support column.

[0007] Furthermore, the dielectric material layer is a high-resolution photosensitive material, and the dielectric material layer fills the gap between the chip body and the embedding groove, fixing the chip body in the embedding groove.

[0008] Furthermore, the support column is made of conductive metal, and the support column connects the wiring layer and the RDL build-up layer.

[0009] Furthermore, a seed layer is provided between the wiring layer and the chip body. The seed layer is formed by a PVD or CVD process, and the seed layer connects the wiring layer and the chip body.

[0010] Furthermore, the arrangement positions of the embedded grooves are determined according to the prefabricated bridge circuit diagrams of different chip bodies.

[0011] Compared with the prior art, the beneficial effects of the present invention are:

[0012] The utility model embeds the entire chip inside the substrate, and uses a high-sensitivity dielectric material to fill the cavity, which makes it convenient to use the exposure and development method to open windows to lead out the pins, greatly improving the risk of damage to the chip pins. The compression molding method can prevent the metal copper column from being easily deformed and the substrate from warping, thereby improving the overall yield of the central layer structure of the final package substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 This is a main cross-sectional structural diagram of the present utility model.

[0014] Reference numerals

[0015] 1. Support limit frame; 2. Chip body; 3. Dielectric material layer; 4. Seed layer; 5. Wiring layer; 6. Plastic encapsulation layer; 7. Support column; 8. RDL build-up layer; 9. Substrate. DETAILED DESCRIPTION

[0016] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more precise definition of the protection scope of the present invention.

[0017] See also Figure 1 As shown, a semiconductor package bridge structure includes a support limit frame, a substrate, a chip body, a dielectric material layer, a wiring layer, a support column, a plastic encapsulation layer and an RDL build-up layer. The support limit frame is embedded with the substrate, and the support limit frame is used to limit and support the entire structure, which facilitates subsequent fixing processing. The upper end surface of the substrate is fixed with an embedding groove, and the arrangement position of the embedding groove is determined according to the bridge prefabricated circuit diagram of different chip bodies. Different types of chip bodies are embedded in the embedding groove. The upper end surface of the substrate is fixed with a dielectric material layer, which is a high-resolution photosensitive material. The dielectric material layer fills the gap between the chip body and the embedding groove, and fixes the chip body in the embedding groove.

[0018] A pattern groove is opened on the dielectric material layer through pattern transfer and exposure and development process, and then a seed layer is formed in the pattern groove through PVD or CVD process, and a wiring layer is made to connect the seed layer for wiring. The wiring layer is fixedly connected to the output and input ends of the chip body. A support column is fixedly provided on the upper end surface of the wiring layer. A plastic encapsulation layer is fixedly provided on the upper end surface of the dielectric material layer. An RDL build-up layer is provided on the upper end surface of the plastic encapsulation layer. The RDL build-up layer is fixedly connected to the support column.

[0019] The utility model nests the pre-made chip wafer with different chips pasted into the embedding groove of the substrate, then uses high-resolution optical dielectric material to press and cure the chip, performs exposure and development on different chip connection positions, opens windows for different pins on the chip surface, and then uses PVD / CVD to make a seed layer, and then makes a fan-in RDL layer. The entire module is then plastic-sealed and cured using the C-Mold method, and the fan-out RDL is led out and added layers are realized in the plastic sealing material layer. After the module is manufactured, it is cut into single modules.

[0020] The technical solution of the present invention can produce a 500*500mm C-mold, which will greatly improve the efficiency of subsequent RDL production, which is much higher than the C-mold of wafer production or ordinary packaging lines in the existing technology.

[0021] The above description is only a preferred embodiment of the present invention. The protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the content disclosed in the present invention should be included in the protection scope recorded in the claims.

Claims

1. A semiconductor package bridge structure, comprising a support frame, a substrate, a chip body, a dielectric material layer, a wiring layer, a support column, a plastic layer and an RDL build-up layer, characterized in that: A substrate is embedded in the support limit frame, and an embedding groove is fixedly provided on the upper end surface of the substrate. Different types of chip bodies are embedded in the embedding groove. A dielectric material layer is fixedly provided on the upper end surface of the substrate, and a graphic groove is provided on the dielectric material layer. A wiring layer is provided in the graphic groove, and the wiring layer is fixedly connected to the output and input ends of the chip body. A support column is fixedly provided on the upper end surface of the wiring layer, and a plastic packaging layer is fixedly provided on the upper end surface of the dielectric material layer. An RDL build-up layer is provided on the upper end surface of the plastic packaging layer, and the RDL build-up layer is fixedly connected to the support column.

2. The semiconductor package bridge structure according to claim 1, wherein: The dielectric material layer is a high-resolution photosensitive material, and the dielectric material layer fills the gap between the chip body and the embedding groove, fixing the chip body in the embedding groove.

3. The semiconductor package bridge structure according to claim 1, wherein: The support column is made of conductive metal and connects the wiring layer and the RDL build-up layer.

4. The semiconductor package bridge structure according to claim 1, wherein: A seed layer is provided between the wiring layer and the chip body. The seed layer is formed by a PVD or CVD process and connects the wiring layer and the chip body.

5. The semiconductor package bridge structure according to claim 1, wherein: The arrangement positions of the embedded grooves are determined according to the prefabricated bridge circuit diagrams of different chip bodies.

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