MIM capacitor structure, radio frequency passive device and substrate

Abstract

The utility model discloses an MIM capacitor structure, a radio frequency passive device and a substrate, and relates to the technical field of passive devices, the MIM capacitor structure comprises a first electrode, a laminated dielectric layer and a second electrode; the laminated dielectric layer covers the top surface and the side surface of the second electrode and extends for a preset length along the direction parallel to the bottom surface of the second electrode; the first electrode at least covers part or all of the top surface of the laminated dielectric layer; the laminated dielectric layer at least comprises a first dielectric layer, a second dielectric layer and a third dielectric layer; the first dielectric layer covers the top surface and the side surface of the second electrode; the refractive index of the second dielectric layer is greater than those of the first dielectric layer and the third dielectric layer, the second dielectric layer has negative stress, and the third dielectric layer has positive stress. According to the invention, the gap problem of a single dielectric layer at the base angle can be overcome.

Description

Technical Field

[0001] The utility model relates to the technical field of passive devices, in particular to a MIM capacitor structure, a radio frequency passive device and a substrate. Background Art

[0002] Currently, packaged integrated passive devices (capacitors, inductors, resistors, etc.) are becoming more complex and denser, and the characteristic structural dimensions of the devices are becoming smaller and allowing for higher performance. For example, capacitors require smaller sizes and higher voltage resistance. When the aspect ratio of the capacitor electrode increases, some problems will be exposed. Under high voltage resistance requirements, the capacitor dielectric layer needs to be denser and have a higher refractive index, which will lead to greater stress in the dielectric layer. At the corners under high aspect ratios, gaps appear due to stress concentration and different deposition rates. In addition, due to the large difference in thermal expansion coefficients between the upper and lower electrodes and the middle dielectric layer and stress mismatch, delamination between the electrodes and the dielectric layer and cracks in the dielectric layer occur. This eventually leads to leakage in the insulation layer and short circuits between the upper and lower electrodes. Utility Model Content

[0003] The main technical problem solved by the utility model is that in existing capacitor devices with high aspect ratio structures, a single dielectric layer has gaps at the bottom corners, which affects the performance of the device.

[0004] According to the first aspect, an embodiment provides a MIM capacitor structure, comprising: a first electrode, a laminated dielectric layer, and a second electrode;

[0005] The laminated dielectric layer covers the top surface and side surfaces of the second electrode and extends a preset length in a direction parallel to the bottom surface of the second electrode;

[0006] The first electrode covers at least part or all of the top surface of the laminated dielectric layer;

[0007] The laminated dielectric layer comprises at least a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence; the first dielectric layer covers the top surface and side surfaces of the second electrode;

[0008] The refractive index of the second dielectric layer is greater than the refractive indexes of the first dielectric layer and the third dielectric layer, the second dielectric layer has a negative stress, and the third dielectric layer has a positive stress;

[0009] The thickness of the second dielectric layer at the lower end near the second electrode side is thinner than that at the upper end, and the thickness of the third dielectric layer at the lower end near the second electrode side is thinner than that at the upper end.

[0010] In some embodiments, the material of the first dielectric layer, the second dielectric layer, and the third dielectric layer are all the same one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate;

[0011] The density of the second dielectric layer is greater than the density of the first dielectric layer and the third dielectric layer;

[0012] or,

[0013] The second dielectric layer is made of a different material from the first dielectric layer, and the second dielectric layer is made of a different material from the third dielectric layer, which are respectively one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate;

[0014] The dielectric constant of the second dielectric layer is greater than the dielectric constants of the first dielectric layer and the third dielectric layer.

[0015] In some embodiments, the material of the second dielectric layer is silicon nitride, the material of the first dielectric layer is ethyl silicate or silicon dioxide, and the material of the third dielectric layer is silicon dioxide;

[0016] or,

[0017] The materials of the first dielectric layer, the second dielectric layer and the third dielectric layer are all silicon nitride.

[0018] In some embodiments, along the stacking direction, the thickness of the third dielectric layer is 1 / 2 to 2 / 3 of the thickness of the second dielectric layer.

[0019] In some embodiments, along the stacking direction, the thickness of the first dielectric layer is 30 nm to 100 nm; and / or the thickness of the second dielectric layer is 600 nm to 800 nm; and / or the thickness of the third dielectric layer is 200 nm to 400 nm.

[0020] In some embodiments, the minimum thickness of the second dielectric layer at the lower end near the side of the second electrode is 70% to 80% of the maximum thickness at the upper end.

[0021] In some embodiments, the first electrode covers the top surface and side surfaces of the laminated dielectric layer.

[0022] In some embodiments, the ratio of the depth of the second electrode in the stacking direction to the width perpendicular to the stacking direction is 1:1 to 1:10;

[0023] And / or, a planar dimension of the MIM capacitor structure perpendicular to the stacking direction is 3 μm to 50 μm.

[0024] According to the second aspect, an embodiment provides a radio frequency passive component, including the MIM capacitor structure described in the first aspect.

[0025] According to a third aspect, an embodiment provides a substrate, comprising a substrate and at least one MIM capacitor structure, the MIM capacitor structure comprising: a first electrode, a laminated dielectric layer, and a second electrode;

[0026] A second electrode is formed on the substrate;

[0027] The laminated dielectric layer covers the top surface and side surfaces of the second electrode and extends a preset length in a direction parallel to the bottom surface of the second electrode;

[0028] The first electrode covers at least part or all of the top surface of the laminated dielectric layer;

[0029] The laminated dielectric layer comprises at least a first dielectric layer, a second dielectric layer and a third dielectric layer stacked in sequence; the first dielectric layer covers the top surface and side surfaces of the second electrode;

[0030] The refractive index of the second dielectric layer is greater than the refractive indexes of the first dielectric layer and the third dielectric layer, the second dielectric layer has a negative stress, and the third dielectric layer has a positive stress;

[0031] The thickness of the second dielectric layer at the lower end near the second electrode side is thinner than that at the upper end, and the thickness of the third dielectric layer at the lower end near the second electrode side is thinner than that at the upper end.

[0032] According to the MIM capacitor structure, RF passive device and substrate of the above-mentioned embodiment, by depositing multiple dielectric layers with different refractive indices on the second electrode, the gap problem of a single dielectric layer at the bottom corner can be overcome. By using a third dielectric layer with positive stress in combination with a second dielectric layer with negative stress, the stress problem between the electrode and the dielectric layer can be overcome. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A schematic diagram of the structure of an existing lateral capacitor structure;

[0034] Figure 2 A schematic diagram of the structure of an existing vertical capacitor structure;

[0035] Figure 3 A schematic diagram of another existing vertical capacitor structure;

[0036] Figure 4 for Figure 3 A partial enlarged view of area A in the middle;

[0037] Figure 5 A schematic diagram of the structure of a MIM capacitor provided in one embodiment of the present application;

[0038] Figure 6 for Figure 5 A partial enlarged view of the middle B area;

[0039] Figure 7 for Figure 5 A top view of

[0040] Figure 8 A schematic structural diagram of a substrate provided in one embodiment of the present application;

[0041] Figure 9 A schematic diagram of a process for manufacturing a MIM capacitor structure provided in one embodiment of the present application.

[0042] Reference numerals: 100 - MIM capacitor structure; 1 - first electrode; 2 - second electrode; 3 - laminated dielectric layer; 31 - first dielectric layer; 32 - second dielectric layer; 33 - third dielectric layer; 10 - substrate; 4 - photoresist layer; 200 - base plate. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted under different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0044] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0045] The serial numbers assigned to components herein, such as "first," "second," etc., are used solely to distinguish the objects being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0046] RF passive components generally include devices / structures such as capacitors, resistors, and inductors. For example, wireless IPD filters in base stations are used. With the development of technology, devices need to remain miniaturized, and the internal circuits are becoming more and more complex. At this time, the characteristic dimensions of the devices need to become smaller, and their working capabilities need to be improved.

[0047] Taking capacitors as an example, if they need to have a high withstand voltage, the dielectric layer between the electrodes must meet the following conditions:

[0048] High dielectric constant: The dielectric constant (relative permittivity) of the dielectric material needs to be high enough to increase the capacitance of the capacitor. High dielectric constant materials can store more charge in a smaller volume.

[0049] Good insulation performance: The dielectric layer should have high resistivity to prevent leakage current and ensure that the capacitor can effectively store charge without energy loss.

[0050] Higher breakdown voltage: The dielectric layer must be able to withstand a certain electric field strength without breakdown to ensure safe operation under high voltage.

[0051] The above performance requirements are generally based on the integrity of the dielectric layer. When defects occur in the dielectric layer, it is difficult for the dielectric layer to meet the above performance requirements.

[0052] The MIM (Metal-Insulator-Metal) capacitor structure is a parallel plate capacitor, generally consisting of two metal electrodes and an insulating dielectric layer between the electrodes. Figure 1-Figure 2 As shown, according to the arrangement of the electrodes, the existing MIM capacitor structure can be divided into a horizontal structure (or a left-right structure) or a vertical structure (or an up-down structure).

[0053] In high aspect ratios (aspect ratios, such as Figure 3 In the field of capacitor structures (where the up and down directions are longitudinal and the left and right directions are transverse), a longitudinal structure is generally used, such as Figure 3-Figure 4 As shown in FIG, when a dielectric layer is required to wrap the lower electrode, since the dielectric layer is deposited faster on the bottom surface and the side of the electrode than in the bottom corner area, the dielectric layer at the bottom corner is formed by splicing the side wall and the bottom, and the thickness of the dielectric layer at the bottom corner (such as Figure 4 The left and right dimensions in the middle are relatively thin. In this case, the dielectric layer is prone to gaps / cracks at the bottom corners of the lower electrode (such as Figure 4 (As shown by the dotted line), due to the large difference in thermal expansion coefficients between the two electrodes and the dielectric layer in the middle, stress problems may also occur. This may cause or aggravate the peeling of the dielectric layer or cracks at the bottom corners during the use of the device.

[0054] Some existing solutions and packaging technologies address this issue by changing the deposition process conditions of the dielectric layer above the lower electrode. This method is difficult to debug, as it requires both high density and defect-free dielectric layers. Different devices require different dimensions and materials, making this approach less applicable. Therefore, new technologies are needed to ensure that the dielectric layer can withstand high voltages while eliminating the leakage risk caused by cracks in the dielectric layer. Furthermore, the stress mismatch between the upper and lower electrodes and the dielectric layer must be addressed. This application aims to address at least one of these technical issues.

[0055] like Figures 5 and 6 As shown, an embodiment of the present application provides a MIM capacitor structure 100 including: a first electrode 1 , a laminated dielectric layer 3 and a second electrode 2 .

[0056] The second electrode 2 is formed on the substrate 10, for example, by thin film deposition (physical vapor deposition or magnetron sputtering), or by electroplating, chemical plating or evaporation. In this application, the substrate 10 can be a silicon substrate or a glass substrate.

[0057] The laminated dielectric layer 3 covers the top and side surfaces of the second electrode 2 and extends parallel to the bottom surface of the second electrode 2 (eg Figure 5 The left and right directions in the image are extended by the preset length. Figure 5 As shown, the laminated dielectric layer 3 is partially formed on the top surface of the second electrode 2, partially on the side surface of the second electrode 2, and the remaining portion is on the surface of the substrate 10, which can be correspondingly divided into three parts: top, side, and bottom. In this application, the bottom corner position of the laminated dielectric layer 3 refers to the interval where the side surface and the bottom are connected.

[0058] The first electrode 1 covers at least part or all of the top surface of the laminated dielectric layer 3. Figure 3 and Figure 5 As shown in Figure 3 In the present application, the first electrode 1 may be formed only on the top surface of the laminated dielectric layer 3; Figure 5 In the embodiment, the first electrode 1 may also cover all or part of the side surface of the laminated dielectric layer 3 .

[0059] The laminated dielectric layer 3 includes at least a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33, stacked in sequence, and may further include a fourth dielectric layer, a fifth dielectric layer, and so on. The first dielectric layer 31 is disposed adjacent to the second electrode 2 and covers the top and side surfaces of the second electrode 2. The laminated dielectric layer 3 covers the top surface and portions of both side surfaces of the second electrode 2, thereby reducing air breakdown and improving reliability.

[0060] The refractive index of the second dielectric layer 32 is greater than that of the first dielectric layer 31 , and the refractive index of the second dielectric layer 32 is greater than that of the third dielectric layer 33 . The second dielectric layer 32 has negative stress, the third dielectric layer 33 has positive stress, and the first dielectric layer 31 has zero stress. It should be noted that zero stress is a relatively ideal stress condition. This application does not limit the stress of the first dielectric layer 31 to zero. It can be substantially zero or very small.

[0061] The second dielectric layer 32 is located near the lower end of the side of the second electrode 2 (eg Figure 6 The thickness of D1 in the figure is smaller than that of the upper end (such as Figure 6Furthermore, the thickness of the third dielectric layer 33 at the lower end position close to the side of the second electrode 2 is smaller than the thickness at the upper end position.

[0062] The first electrode 1 can be composed of a conductive material such as aluminum, copper, or copper-doped aluminum. The multiple dielectric layers of the laminated dielectric layer 3 can be a multilayer structure formed of one or more materials selected from silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate. The second electrode 2 can be composed of a conductive material such as aluminum, copper, or copper-doped aluminum.

[0063] Generally speaking, for dielectric materials, the higher the refractive index of the dielectric material, the higher the density. The deposition rate of the dense second dielectric layer 32 is slow, resulting in gaps at the bottom corners. The deposition rate of the loose third dielectric layer 33 is faster, which can quickly fill the gaps in the second dielectric layer 32, thereby avoiding leakage.

[0064] The third dielectric layer 33 is located at the bottom corner of the second dielectric layer 32 (eg Figure 6 The thickness is thinner at D1 in the figure, and thicker at other locations (such as Figure 6 ), can better match the negative stress at different thickness positions of the second dielectric layer 32, so that the overall stress is offset to 0.

[0065] Since the second dielectric layer 32 is thinnest at the bottom corners (corresponding to negative stress), it is also the most prone to cracking. Therefore, a third dielectric layer 33 with a correspondingly strong positive stress is provided at the bottom corners of the second dielectric layer 32 (offsetting the stress to zero) to minimize cracking. Simultaneously, the first dielectric layer 31 maintains zero stress and is relatively loose, making it less susceptible to peeling when covered on the second electrode 2. The third dielectric layer 33 is thinner at the bottom corners of the second dielectric layer 32 and thicker at other locations. This allows it to better match the negative stress at different thickness locations of the second dielectric layer 32, resulting in the overall stress being offset to zero. This allows the first electrode 1 to be covered on a stress-free structure, ensuring a strong direct bond between the second electrode 2 and the third dielectric layer 33 and less susceptible to peeling.

[0066] In some embodiments, the materials of the first dielectric layer 31 , the second dielectric layer 32 , and the third dielectric layer 33 are all the same one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate; the density of the second dielectric layer 32 is greater than that of the first dielectric layer 31 and the third dielectric layer 33 .

[0067] For example, the materials of the first dielectric layer 31, the second dielectric layer 32, and the third dielectric layer 33 can all be silicon nitride. The first dielectric layer 31 and the third dielectric layer 33, which are in contact with the first electrode 1 and the second electrode 2, respectively, are relatively loose silicon nitride films, while the second dielectric layer 32 is a relatively dense silicon nitride film. During the deposition process, the deposition rate of the loose silicon nitride film is faster than that of the dense silicon nitride film. Therefore, the first dielectric layer 31 and the third dielectric layer 33 are set as the two outermost layers of the entire dielectric layer, so that the entire dielectric layer has good conformal properties. Because the dielectric constant of silicon nitride is higher than that of silicon oxide, silicon nitride is used as the main voltage-resistant material, and the thickness of the silicon nitride layer can be adjusted according to the voltage strength of the capacitor.

[0068] In other embodiments, the second dielectric layer 32 is made of a different material than the first dielectric layer 31 , and the second dielectric layer 32 is made of a different material than the third dielectric layer 33 , and the three dielectric layers are respectively made of one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate; the dielectric constant of the second dielectric layer 32 is greater than the dielectric constants of the first dielectric layer 31 and the third dielectric layer 33 .

[0069] By using materials with different dielectric constants, it is also possible to control the density and refractive index of the three dielectric layers.

[0070] For example, the material of the second dielectric layer 32 may be silicon nitride, the material of the first dielectric layer 31 may be ethyl silicate or silicon dioxide, and the material of the third dielectric layer 33 may be silicon dioxide. The dielectric constant of silicon dioxide is 3.9 to 4.2, the dielectric constant of silicon nitride is 11.8, the electric field strength of silicon dioxide is 0.8 V / nm, and the electric field strength of silicon nitride is 1.1 V / nm.

[0071] The first dielectric layer 31 with a relatively loose density can make the second dielectric layer 32 adhere better to the surface of the second electrode 2; and the third dielectric layer 33 with a relatively loose density not only makes the second dielectric layer 32 adhere better to the surface of the first electrode 1, but also takes advantage of the fast deposition rate of the third dielectric layer 33 to allow the third dielectric layer 33 to be deposited into the bottom corner of the second dielectric layer 32, thereby forming a thinner third dielectric layer 33 at the bottom corner of the second dielectric layer 32 (such as Figure 6 ), thereby avoiding leakage between the first electrode 1 and the second electrode 2.

[0072] At the same time, under different densities of the same material, or under different materials, the refractive index of the second dielectric layer 32 is higher than the refractive index of the third dielectric layer 33, and the third dielectric layer 33 with a low refractive index has a positive stress, and the second dielectric layer 32 with a high refractive index has a negative stress. By arranging the third dielectric layer 33 on the side of the second dielectric layer 32 close to the first electrode 1, the negative stress of the second dielectric layer 32 can be effectively offset, thereby avoiding cracks in the entire laminated dielectric layer 3.

[0073] In some embodiments, along the stacking direction (eg Figure 5 In the vertical direction (in the vertical direction), the thickness of the third dielectric layer 33 is 1 / 2 to 2 / 3 of the thickness of the second dielectric layer 32. At the bottom corners, the thickness ratio of the two dielectric layers is also roughly 1 / 2 to 2 / 3. Taking silicon nitride as an example, the negative stress of the dense second dielectric layer 32 can reach -200 MPa to -400 MPa, while the positive stress of the third dielectric layer 33 can reach +300 MPa to +600 MPa, and the overall stress can be adjusted to zero. Therefore, the thickness of the third dielectric layer 33 is 1 / 2 to 2 / 3 of the thickness of the second dielectric layer 32.

[0074] In some embodiments, along the stacking direction, the thickness of the first dielectric layer 31 is 30 nm to 100 nm; and / or the thickness of the second dielectric layer 32 is 600 nm to 800 nm; and / or the thickness of the third dielectric layer 33 is 200 nm to 400 nm. Because the first dielectric layer 31 primarily serves the adhesion function, the zero-stress first dielectric layer 31 can be relatively thin, such as 30 nm to 100 nm. To achieve a withstand voltage greater than 1000 V, a thickness of greater than 800 nm in the stacked dielectric layer 3 can easily create gaps at the bottom corners. Therefore, the thickness of the second dielectric layer 32 should be set to 600 nm to 800 nm.

[0075] In some embodiments, the second dielectric layer 32 is located near the lower end of the side of the second electrode 2 (eg Figure 6 The minimum thickness at the upper end (e.g. D1 in Figure 6 The ratio of the upper and lower ends of the second dielectric layer 32 is related to its own thickness. When the thickness is 600nm to 800nm, the ratio can be controlled to be 70% to 80% to ensure that the thickness at the bottom corner is neither too thin nor too thick.

[0076] In some embodiments, such as Figure 5 As shown, the first electrode 1 covers the top and side surfaces of the laminated dielectric layer 3. The first electrode 1 covers the upper surface and part of the two side surfaces of the second electrode 2. The area where the effective capacitor is formed between the first electrode 1 and the second electrode 2 is increased, thereby improving the overall capacitance value of the capacitor.

[0077] In some embodiments, such as Figure 5As shown, the ratio of the depth of the second electrode 2 in the stacking direction (vertical direction) to the width perpendicular to the stacking direction (lateral direction) is 1:1 to 1:10. The embodiment of the present application is mainly directed to a MIM capacitor structure 100 (capacitor device) having a second electrode 2 (bottom electrode) with a high aspect ratio, but does not exclude the possibility of application to a MIM capacitor structure 100 with a low aspect ratio.

[0078] like Figure 7 As described above, in the above-mentioned embodiment, the plane size of the MIM capacitor structure 100 provided in the embodiment of the present application can be 3μm to 50μm in the direction perpendicular to the stacking direction. This application is mainly aimed at solving the gap problem existing at the bottom corner of the dielectric layer in the small-sized MIM capacitor structure 100. However, it is not ruled out that it can also be applied to solve the same technical problem in the large-sized MIM capacitor structure 100.

[0079] The implementation of the MIM capacitor structure 100 of the present application has been described in detail above. The MIM capacitor structure 100 can be applied to various radio frequency passive devices, such as filters.

[0080] Therefore, another aspect of the embodiment of the present application further provides a radio frequency passive device, including the MIM capacitor structure 100 described in the above embodiment.

[0081] like Figure 8 As shown, another aspect of the embodiment of the present application further provides a substrate 200 or wafer, comprising a substrate 10 and at least one MIM capacitor structure 100 described in the above embodiment.

[0082] The MIM capacitor structure 100 includes: a first electrode 1, a laminated dielectric layer 3, and a second electrode 2; the second electrode 2 is formed on a substrate 10; the laminated dielectric layer 3 covers the top surface and side surfaces of the second electrode 2 and extends a predetermined length in a direction parallel to the bottom surface of the second electrode 2; the first electrode 1 covers at least part or all of the top surface of the laminated dielectric layer 3.

[0083] The laminated dielectric layer 3 includes at least a first dielectric layer 31, a second dielectric layer 32, and a third dielectric layer 33 stacked in sequence; the first dielectric layer 31 covers the top surface and side surfaces of the second electrode 2; the refractive index of the second dielectric layer 32 is greater than the refractive indexes of the first dielectric layer 31 and the third dielectric layer 33, the second dielectric layer 32 has a negative stress, and the third dielectric layer 33 has a positive stress; the thickness of the second dielectric layer 32 at the lower end near the side surface of the second electrode 2 is less than the thickness at the upper end, and the thickness of the third dielectric layer 33 at the lower end near the side surface of the second electrode 2 is less than the thickness at its upper end.

[0084] Based on the substrate 200 or wafer, further device processing or packaging can be performed so that the final device includes the MIM capacitor structure 100 to ensure device performance and also has the technical effects of the MIM capacitor structure 100 described in the above embodiment.

[0085] like Figure 9 As shown, the present application also provides a method for manufacturing the MIM capacitor structure 100, which may include:

[0086] S1, such as Figure 9 As shown in (A) in FIG. 1 , the second electrode 2 is formed on the substrate 10 .

[0087] S2, such as Figure 9 As shown in (B) in FIG, a laminated dielectric layer 3 covering the second electrode 2 is formed. The laminated dielectric layer 3 covers the top surface and side surfaces of the second electrode 2 and extends in a direction parallel to the bottom surface of the second electrode 2 by a preset length.

[0088] S3, such as Figure 9 As shown in (C) and (D) in FIG, a first electrode 1 is formed on the laminated dielectric layer 3, and the first electrode 1 can cover the top surface and side surfaces of the laminated dielectric layer 3. Figure 9 As described in (C), by controlling the pattern of the photoresist layer 4, the shape and position of the first electrode 1 can be controlled.

[0089] A specific implementation is provided below, and the manufacturing method may include:

[0090] Step 1: Clean the glass slide.

[0091] Step 2: Attach the glass slide by coating, rolling, pressing, etc. The subsequent steps include exposure and development. The exposure machine is not a photolithography machine, and the development solution is K2CO3, Na2CO3, etc., which serves as a mask for evaporating the second electrode 2.

[0092] Step three, such as Figure 9 As shown in (A), the second electrode 2 is prepared by evaporation process, and the evaporation raw material is AlCu containing 0.5% Cu.

[0093] Step 4: Single wafer operation, remove the photoresist (PR glue) in acetone solution.

[0094] Step five, such as Figure 9 As shown in (B), a PECVD machine is used to deposit the dielectric layer. Since it is a three-layer dielectric layer, it needs to enter and exit the process chamber three times, which can be a silicon oxide chamber and a silicon nitride chamber respectively. The parameters are optimized to obtain a film that meets the product performance requirements. Special attention should be paid to the need for low-temperature deposition, such as 150 to 250 degrees Celsius, because too high a temperature will make the lower electrode grains coarse, causing air breakdown and resulting in low withstand voltage.

[0095] Step six: Yellow light is used to coat PR glue and then undergoes photolithography and development. The photoresist PR glue serves as a mask for etching the dielectric layer.

[0096] Step seven: perform dry etching with plasma to etch out the topography of the laminated dielectric layer 3, and wash away the etched PR glue with a solvent.

[0097] Step eight, such as Figure 9 As shown in (C), PR glue is coated with yellow light and then undergoes photolithography and development. The photoresist layer 4 is used as a mask for evaporating the first electrode 1.

[0098] Step nine, such as Figure 9 As shown in (D) in FIG. 1 , the first electrode 1 is prepared by an evaporation process, and AlCu containing 0.5% Cu is selected as the evaporation raw material.

[0099] Step 10: Single piece operation, remove the PR glue in acetone solution.

[0100] In summary, the present application provides a MIM capacitor structure 100, a radio frequency passive device and a substrate 200, wherein the capacitor sealing structure includes a second electrode 2, a laminated dielectric layer 3, and a first electrode 1, wherein the second electrode is above a glass substrate, a silicon substrate, etc., the laminated dielectric layer 3 is completely covered above the second electrode 2, and the first electrode 1 is above the laminated dielectric layer, which can effectively avoid short circuits caused by air breakdown, improve the stability of the device, and have a high product yield. It can be applied to the packaging of a variety of products with different requirements and has a wide range of applications.

[0101] By depositing a multi-layer dielectric layer 3 structure of different materials above the second electrode, the problem of gaps in the dielectric layer at the bottom corner is solved, and the problem of peeling caused by stress mismatch between the upper and lower electrodes is also solved.

[0102] This document is described with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the scope of this document. For example, the various operational steps and components used to perform the operational steps may be implemented in different ways (e.g., one or more steps may be deleted, modified, or incorporated into other steps) depending on the specific application or considering any number of cost functions associated with the operation of the system.

[0103] Although the principles of this invention have been shown in various embodiments, many modifications of structure, arrangement, proportion, elements, materials and components that are particularly suitable for specific environments and operational requirements can be used without departing from the principles and scope of this invention. The above modifications and other changes or amendments are intended to be included within the scope of this invention.

[0104] The foregoing detailed description has been described with reference to various embodiments. However, those skilled in the art will recognize that various modifications and changes can be made without departing from the scope of this disclosure. Therefore, the present disclosure will be considered in an illustrative rather than a restrictive sense, and all such modifications will be included within its scope. Similarly, the advantages, other advantages and solutions to the problems of the various embodiments have been described above. However, the benefits, advantages, solutions to the problems and any elements that can produce these, or make them more specific, should not be interpreted as critical, required or necessary. The term "comprising" and any other variants used in this article are all non-exclusive inclusions, so that a process, method, article or device that includes a list of elements includes not only these elements, but also other elements that are not explicitly listed or do not belong to the process, method, system, article or device. In addition, the term "coupled" and any other variants used in this article refer to physical connections, electrical connections, magnetic connections, optical connections, communication connections, functional connections and / or any other connections.

[0105] Those skilled in the art will appreciate that many changes can be made to the details of the above embodiments without departing from the basic principles of the present invention. Therefore, the scope of the present invention should be determined solely by the claims.

Claims

1. A MIM capacitor structure, characterized in that: include: A first electrode (1), a laminated dielectric layer (3), and a second electrode (2); The laminated dielectric layer (3) covers the top surface and side surfaces of the second electrode (2) and extends to a preset length in a direction parallel to the bottom surface of the second electrode (2); The first electrode (1) covers at least part or all of the top surface of the laminated dielectric layer (3); The laminated dielectric layer (3) comprises at least a first dielectric layer (31), a second dielectric layer (32), and a third dielectric layer (33) stacked in sequence; the first dielectric layer (31) covers the top surface and side surfaces of the second electrode (2); The refractive index of the second dielectric layer (32) is greater than the refractive indexes of the first dielectric layer (31) and the third dielectric layer (33); the second dielectric layer (32) has a negative stress, and the third dielectric layer (33) has a positive stress; The thickness of the second dielectric layer (32) at the lower end position close to the side of the second electrode (2) is smaller than the thickness at the upper end position, and the thickness of the third dielectric layer (33) at the lower end position close to the side of the second electrode (2) is smaller than the thickness at the upper end position.

2. The MIM capacitor structure according to claim 1, wherein: The materials of the first dielectric layer (31), the second dielectric layer (32) and the third dielectric layer (33) are all the same one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide and ethyl silicate; The density of the second dielectric layer (32) is greater than the density of the first dielectric layer (31) and the third dielectric layer (33); or, The second dielectric layer (32) is made of a different material from the first dielectric layer (31), and the second dielectric layer (32) is made of a different material from the third dielectric layer (33), and the three dielectric layers are respectively made of one of silicon nitride, silicon oxynitride, silicon dioxide, titanium oxide, and ethyl silicate; The dielectric constant of the second dielectric layer (32) is greater than the dielectric constants of the first dielectric layer (31) and the third dielectric layer (33).

3. The MIM capacitor structure according to claim 1, wherein: The material of the second dielectric layer (32) is silicon nitride, the material of the first dielectric layer (31) is ethyl silicate or silicon dioxide, and the material of the third dielectric layer (33) is silicon dioxide; or, The materials of the first dielectric layer (31), the second dielectric layer (32) and the third dielectric layer (33) are all silicon nitride.

4. The MIM capacitor structure according to claim 1, wherein: Along the stacking direction, the thickness of the third dielectric layer (33) is 1 / 2 to 2 / 3 of the thickness of the second dielectric layer (32).

5. The MIM capacitor structure according to claim 4, wherein: Along the stacking direction, the thickness of the first dielectric layer (31) is 30nm-100nm; and / or the thickness of the second dielectric layer (32) is 600nm-800nm; and / or the thickness of the third dielectric layer (33) is 200nm-400nm.

6. The MIM capacitor structure according to claim 4, wherein: The minimum thickness of the second dielectric layer (32) at the lower end position close to the side of the second electrode (2) is 70% to 80% of the maximum thickness at the upper end position.

7. The MIM capacitor structure according to claim 1, wherein: The first electrode (1) covers the top surface and side surfaces of the laminated dielectric layer (3).

8. The MIM capacitor structure according to any one of claims 1 to 7, wherein: The ratio of the depth of the second electrode (2) in the stacking direction to the width perpendicular to the stacking direction is 1:1 to 1:10; And / or, the plane size of the MIM capacitor structure (100) perpendicular to the stacking direction is 3 μm to 50 μm.

9. A radio frequency passive device, characterized in that: The MIM capacitor structure (100) comprises any one of claims 1-8.

10. A substrate, characterized in that: It comprises a substrate (10) and at least one MIM capacitor structure (100), wherein the MIM capacitor structure (100) comprises: a first electrode (1), a laminated dielectric layer (3) and a second electrode (2); The second electrode (2) is formed on the substrate (10); The laminated dielectric layer (3) covers the top surface and side surfaces of the second electrode (2) and extends to a preset length in a direction parallel to the bottom surface of the second electrode (2); The first electrode (1) covers at least part or all of the top surface of the laminated dielectric layer (3); The laminated dielectric layer (3) comprises at least a first dielectric layer (31), a second dielectric layer (32), and a third dielectric layer (33) stacked in sequence; the first dielectric layer (31) covers the top surface and side surfaces of the second electrode (2); The refractive index of the second dielectric layer (32) is greater than the refractive indexes of the first dielectric layer (31) and the third dielectric layer (33); the second dielectric layer (32) has a negative stress, and the third dielectric layer (33) has a positive stress; The thickness of the second dielectric layer (32) at the lower end position close to the side of the second electrode (2) is smaller than the thickness at the upper end position, and the thickness of the third dielectric layer (33) at the lower end position close to the side of the second electrode (2) is smaller than the thickness at the upper end position.

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