PWM (Pulse Width Modulation) audio driving optimization circuit

Abstract

The utility model discloses a PWM (Pulse Width Modulation) audio drive optimization circuit. The circuit comprises a digital arithmetic unit, an adder and a comparator, by optimizing the whole PWM audio drive circuit, the playing sound quality can be improved when the low-sampling-rate audio is played, and the sound playing quality can be improved even under the condition that the flash occupied space is not increased. According to the invention, the PWM waveform with the transition duty ratio change is added between every two sampling points to gradually change the duty ratio change process of the PWM, so that the audio signal simulated by the PWM is more restored, and the sound quality is improved.

Description

Technical Field

[0001] The present application relates to the field of audio driving, and in particular to a PWM audio driving optimization circuit. Background Art

[0002] Low-cost voice solutions typically use PWM (pulse-width modulation) with an external half-bridge circuit to directly drive the speaker, generating sound. This approach works similarly to a Class D amplifier, modulating the audio signal through rapid switching to drive the speaker. However, in this low-cost solution, the audio data doesn't originate from an external device or advanced audio processing module. Instead, it is read directly from the device's internal Flash memory and loaded into the PWM module for sound generation.

[0003] Due to cost constraints, the Flash memory used cannot be too large, so these circuits typically choose a lower audio sampling rate to reduce data size. Common sampling rates range from 6K to 8K, effectively reducing the amount of data stored. However, the low sampling rate reduces the fineness of the audio signal, resulting in significant sound distortion, poor playback quality, and a less-than-ideal listening experience. Summary of the Invention

[0004] In order to overcome the shortcomings and deficiencies of the prior art, the present application provides a PWM audio drive optimization circuit.

[0005] The technical solution adopted in this application is a PWM audio drive optimization circuit, which includes: a digital operator, an adder, and a comparator;

[0006] The digital operator has an input connected to the target PWM duty cycle setting value and the original PWM duty cycle setting value; an output connected to the comparator, and transmits the calculation result to the comparator for further processing;

[0007] The adder has an input connected to the duty cycle change value of each PWM cycle and the cycle control execution; an output connected to the PWM duty cycle setting value, and uses the addition result as the newly set duty cycle value;

[0008] The comparator has an input connected to the digital operator and receives the calculated value for comparison; an output connected to the PWM duty cycle setting value and adjusts the duty cycle according to the comparison result.

[0009] Furthermore, the digital operator is used to calculate a duty cycle change value per PWM cycle based on the duty cycle gradual change period setting, the target PWM duty cycle setting value, and the original PWM duty cycle setting value. The calculation formula is: duty cycle change value per PWM cycle = (target PWM duty cycle setting value - original PWM duty cycle setting value) / duty cycle gradual change period setting.

[0010] Furthermore, the adder is used to add the duty cycle change value of each PWM cycle and the PWM duty cycle setting value, and update the result into the PWM duty cycle setting value register.

[0011] Furthermore, the comparator determines whether to update the original PWM duty cycle setting value by comparing the PWM duty cycle setting value with the target PWM duty cycle setting value. When the PWM duty cycle setting value is consistent with the target PWM duty cycle setting value, the target PWM duty cycle value is loaded into the original PWM duty cycle setting value.

[0012] Beneficial effects:

[0013] This application proposes a PWM audio driver optimization circuit. By optimizing the entire PWM audio driver circuit, this application can improve the sound quality when playing low-sampling-rate audio, even without increasing the flash memory footprint. This application gradually changes the PWM duty cycle by adding a transitional PWM waveform between each sampling point. This allows the audio signal simulated by the PWM to be more faithfully reproduced, thereby improving sound quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a circuit structure diagram of this application;

[0015] Figure 2 These are the non-optimized PWM waveform a and the optimized PWM waveform b of this application. DETAILED DESCRIPTION

[0016] It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other. The present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] like Figure 1 As shown, a PWM audio driver optimization circuit is implemented primarily through an improved PWM circuit structure. By adding a series of digital circuits before the PWM setting, the entire process is automatically completed by hardware. The figure below shows the PWM optimization circuit structure of this application. The blue part of this application represents the special function register designed for the MCU.

[0018] A PWM audio drive optimization circuit, comprising: a digital operator, an adder, and a comparator;

[0019] Digital operator, input: connected to the target PWM duty cycle setting value and the original PWM duty cycle setting value; output: connected to the comparator, passing the calculation result to the comparator for further processing;

[0020] Adder, input: connected to the duty cycle change value of each PWM cycle and the cycle control execution; output: connected to the PWM duty cycle setting value, and the addition result is used as the new duty cycle value;

[0021] Comparator, input: connected to the digital operator, receives the calculated value for comparison; output: connected to the PWM duty cycle setting value, adjusts the duty cycle according to the comparison result.

[0022] The digital operator is used to calculate the duty cycle change value per PWM cycle based on the duty cycle gradient period setting, the target PWM duty cycle setting value, and the original PWM duty cycle setting value. The calculation formula is: Duty cycle change value per PWM cycle = (target PWM duty cycle setting value - original PWM duty cycle setting value) / Duty cycle gradient period setting.

[0023] The adder is used to add the duty cycle change value of each PWM cycle and the PWM duty cycle setting value, and the result is updated to the PWM duty cycle setting value register.

[0024] The comparator determines whether to update the original PWM duty cycle setting value by comparing the PWM duty cycle setting value with the target PWM duty cycle setting value. When the PWM duty cycle setting value is consistent with the target PWM duty cycle setting value, the target PWM duty cycle value is loaded into the original PWM duty cycle setting value.

[0025] The duty cycle gradual change period setting is a period module used to set the PWM duty cycle change in the circuit. It sets the time interval for the duty cycle gradual change and is used to control the change speed of the PWM signal.

[0026] The PWM Duty Cycle Gradual Timer is responsible for gradually adjusting the PWM duty cycle according to a set period. It accepts the "Duty Cycle Gradual Change Period Setting" input and adjusts the duty cycle at the set interval. Its output is connected to the PWM Duty Cycle Change Value per Cycle module, providing duty cycle change data within each cycle. Its output is also connected to the Cycle Control Execution module, which controls the circuit's periodic operation.

[0027] Target PWM duty cycle setting value: This module represents the target PWM duty cycle setting value expected by the circuit. This value is usually set by the user or calculated by the control circuit, and is used to compare and adjust the current PWM duty cycle.

[0028] The original PWM duty cycle setting value, which is the circuit's current PWM duty cycle state value, is used as a reference value for comparison and adjustment. This value, along with the target duty cycle, is input into the subsequent "digital operator" for calculation.

[0029] The duty cycle change value of each PWM cycle is output based on the change information provided by the PWM timer. Its output is connected to the adder to calculate the new duty cycle.

[0030] The PWM duty cycle setting value receives inputs from the adder and comparator, ultimately setting the PWM duty cycle. This setting is used to control the MOSFET driver circuit. The output is connected to the MOSFET driver, providing the drive signal for the MOSFET.

[0031] A MOSFET driver receives a PWM signal to drive the MOSFET switching circuit. The MOSFET driver amplifies the PWM signal and controls the MOSFET's switching state, thereby controlling the load (such as a speaker or motor).

[0032] The output is connected to a low-pass filter (LPF) to filter the PWM signal into a smooth analog signal.

[0033] The LPF (low-pass filter) receives the PWM signal output by the MOSFET driver, filters out the high-frequency components, retains the low-frequency components, and outputs a relatively smooth analog voltage or current signal. The final output is used to drive an external load (such as a speaker or motor).

[0034] This circuit design demonstrates a complete PWM control process, detailing the steps from duty cycle setting and adjustment to final output. The entire circuit controls the MOSFET's switching state by setting and adjusting the duty cycle, achieving precise control of the output load.

[0035] Through this circuit, PWM will gradually change to the target duty cycle, such as Figure 2 The following figure shows two different PWM signal shapes: "Non-optimized PWM waveform a" and "Optimized PWM waveform b". The following are the detailed differences between the two:

[0036] 1. Waveform stability and consistency:

[0037] Unoptimized PWM waveform a: This waveform displays irregular pulse widths, with significant variations in pulse intervals and duration. This irregularity indicates that the PWM signal may be jittering or unstable during operation, which can lead to reduced control accuracy or unstable load response.

[0038] Optimized PWM waveform b: The optimized PWM waveform exhibits more uniform pulse widths, significantly improving pulse periodicity and consistency. This consistency ensures stable drive of loads (such as speakers and motors) during control, reducing noise or errors caused by unstable signals.

[0039] 2. Duty cycle change and control:

[0040] Unoptimized PWM waveforms: Without optimization, the duty cycle varies irregularly, and the pulse widths are inconsistent. This can be due to a lack of precise control during signal processing or external interference. This often leads to uneven output power, impacting circuit performance.

[0041] Optimized PWM waveform: The optimized PWM waveform shows a clear duty cycle adjustment. While maintaining a consistent period, the duty cycle gradually adjusts, forming a smooth transition. This optimization allows the circuit to precisely control the output signal based on actual needs, improving circuit responsiveness and efficiency.

[0042] 3. Audio and control accuracy:

[0043] Non-optimized PWM waveform: If this waveform is used in audio or motor control, it may cause distortion or vibration because the unstable waveform affects the continuity and accuracy of the output.

[0044] Optimized PWM waveform: The optimized waveform can improve audio quality or motor control accuracy, making the output signal smoother and more precise, thereby ensuring higher control effect and stability.

[0045] The non-optimized PWM waveform shows an unprocessed or unadjusted PWM waveform, exhibiting unstable and inconsistent characteristics. The optimized PWM waveform, on the other hand, displays a tuned and optimized PWM waveform with a stable period and regular pulse width. This optimization helps improve circuit control accuracy and signal quality, ensuring smoother and more efficient output.

[0046] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "disposed," "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will be able to understand the specific meanings of the above terms in this application based on specific circumstances.

[0047] Although the embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various equivalent changes, modifications, substitutions and variations may be made to these embodiments without departing from the principles and spirit of the present application, and the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A PWM audio driver optimization circuit, characterized in that ,The circuit includes a digital operator, an adder, and a comparator; The digital operator has an input connected to the target PWM duty cycle setting value and the original PWM duty cycle setting value; an output connected to the comparator, and transmits the calculation result to the comparator for further processing; The adder has an input connected to the duty cycle change value of each PWM cycle and the cycle control execution; an output connected to the PWM duty cycle setting value, and uses the addition result as the newly set duty cycle value; The comparator has an input connected to the digital operator to receive the calculated value for comparison; an output connected to the PWM duty cycle setting value to adjust the duty cycle according to the comparison result.

2. A PWM audio drive optimization circuit as claimed in claim 1, characterized in that: The digital operator is used to calculate the duty cycle change value of each PWM cycle according to the duty cycle gradual change period setting, the target PWM duty cycle setting value, and the original PWM duty cycle setting value. The calculation formula is: duty cycle change value of each PWM cycle = (target PWM duty cycle setting value - original PWM duty cycle setting value) / duty cycle gradual change period setting.

3. A PWM audio drive optimization circuit as claimed in claim 1, characterized in that: The adder is used to add the duty cycle change value of each PWM cycle and the PWM duty cycle setting value, and update the result into the PWM duty cycle setting value register.

4. A PWM audio drive optimization circuit as claimed in claim 1, characterized in that: The comparator determines whether to update the original PWM duty cycle setting value by comparing the PWM duty cycle setting value with the target PWM duty cycle setting value. When the PWM duty cycle setting value is consistent with the target PWM duty cycle setting value, the target PWM duty cycle value is loaded into the original PWM duty cycle setting value.

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