Testing device
Through the testing device integrating the main controller and multiple memory modules, the FSMC module functional testing problem is solved, fast and comprehensive functional verification is achieved, and the MCU chip design and testing costs are reduced.
Patent Information
- Application Number
- CN202422603975.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-28
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2034-10-28
AI Technical Summary
The lack of special functional testing of FSMC modules in the prior art has led to the inability to accurately verify during the design and development stage, affecting the performance and development of application equipment.
It provides a test device, integrating the main controller, SRAM module, NOR FLASH module, NAND FLASH module, PC CARD module and corresponding read and write interfaces, and communicates with the target MCU chip through the main controller, simulates the read and write operations of the FSMC module, and realizes functional testing of the FSMC module.
It realizes complete and fast functional verification of FSMC modules, reduces the cost of MCU chip design and testing, and ensures that FSMC module meets functional requirements.
Smart Images
Figure CN223296556U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of computers, in particular to a testing device. Background Art
[0002] The Flexible Static Memory Controller (FSMC) is a novel memory expansion technology used in the STM32 series. FSMC can connect to synchronous or asynchronous memories as well as 16-bit PC memory cards. Conventional FSMC module interfaces support common memories such as SRAM, NAND FLASH, NOR FLASH, and PC CARDs. With the widespread adoption of FSMC functional modules, custom-designed MCU FSMC modules are also being used in a variety of scenarios. Therefore, effectively evaluating the usability of FSMC modules in MCUs is crucial for the practical implementation of MCU chips equipped with built-in FSMC modules. Utility Model Content
[0003] The purpose of the utility model is to provide a testing device that can completely and quickly implement functional testing of an MCU chip with a built-in FSMC module, effectively reducing the time cost and testing cost of MCU chip design.
[0004] In order to solve the above technical problems, the present invention provides a test device for testing a target MCU chip with a built-in FSMC module, the test device comprising:
[0005] Test board;
[0006] A main controller provided on the test board;
[0007] A memory module is provided on the test board, wherein the memory module includes an SRAM module, a NOR FLASH module, a NAND FLASH module and a PC CARD module;
[0008] A plurality of read-write interfaces respectively connected to the memory modules;
[0009] The main controller is used to communicate with the target MCU chip to send a test instruction to the target MCU chip;
[0010] Each of the memory modules is used to connect to each read-write interface of the FSMC module to be tested in the target MCU chip through each read-write interface, and receive the read-write operation of the FSMC module to be tested.
[0011] In an optional embodiment of the present application, the read / write interface to be tested includes an SRAM interface, a NOR FLASH interface, a NAND FLASH interface, and a PC CARD interface;
[0012] Correspondingly, the read-write interface includes a first read-write interface, a second read-write interface, a third read-write interface, and a fourth read-write interface, which correspond one-to-one to each of the read-write interfaces to be tested;
[0013] Wherein, the SRAM interface and the NOR FLASH interface are the same first shared interface to be tested; the NAND FLASH interface and the PC CARD interface are the same second shared interface to be tested;
[0014] The first read-write interface and the second read-write interface are the same first shared interface, used to connect to the first shared interface to be tested; the third read-write interface and the fourth read-write interface are the same second shared interface, used to connect to the second shared interface to be tested.
[0015] In an optional embodiment of the present application, the main controller is provided with a GPIO output pin for outputting test instructions to the target MCU chip and a GPIO input pin for receiving test results uploaded by the target MCU chip.
[0016] In an optional embodiment of the present application, the test board is provided with a wireless communication module and / or a wired communication interface connected to the main controller;
[0017] The main controller is connected to the host computer through the wireless communication module or the wired communication interface.
[0018] In an optional embodiment of the present application, the test board is further provided with a start switch connected to the main controller; when the start switch is closed, the main controller outputs a test instruction to the target MCU chip.
[0019] In an optional embodiment of the present application, the start switch includes a plurality of switches corresponding one-to-one to each of the read-write interfaces to be tested;
[0020] When one of the start switches is closed, the main controller outputs a test instruction of the read-write interface to be tested corresponding to the closed start switch to the target MCU chip.
[0021] In an optional embodiment of the present application, the test board is further provided with a display module connected to the main controller for displaying the test results.
[0022] In an optional embodiment of the present application, the display module includes a plurality of LED indicator lights; wherein each of the LED indicator lights is an indicator light of a different luminous color and / or a different flashing frequency.
[0023] In an optional embodiment of the present application, the test board is further provided with an SPI FLASH module connected to the main controller for storing test results.
[0024] In an optional embodiment of the present application, the test board is further provided with a DC power supply connected to the main controller and each of the memory modules respectively.
[0025] The test device provided by the utility model includes: a test board; a main controller arranged on the test board; a memory module arranged on the test board, the memory module including an SRAM module, a NOR FLASH module, a NAND FLASH module and a PC CARD module; a plurality of read-write interfaces respectively connected to each memory module; wherein the main controller is used to communicate with a target MCU chip to send a test instruction to the target MCU chip; each memory module is used to connect to each read-write interface to be tested of a FSMC module to be tested in the target MCU chip through each read-write interface, and receive read-write operations of the FSMC module to be tested.
[0026] In the test device of the present application, a plurality of different memory modules such as SRAM module, NOR FLASH module, NAND FLASH module, PC CARD module are respectively configured for each different read and write function of the FSMC module. Therefore, after the main controller sends a test instruction to the target MCU chip with a built-in FSMC module, the target MCU chip can trigger its built-in FSMC module to perform read and write operations on each memory module, which is equivalent to simulating the read and write operation process of the FSMC module in the target MCU chip. Based on whether the FSMC module succeeds or not in the read and write operations on each memory module, it can be determined whether the read and write functions of the FSMC module are good, and then the read and write function test of the target MCU chip with a built-in FSMC module is realized. The complete and rapid functional verification of the FSMC module in the MCU can be realized during the design and verification stages of the MCU chip to ensure that the FSMC module meets the functional requirements and effectively reduce the time cost and testing cost of MCU chip design. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0028] Figure 1 A schematic diagram of the principle structure of the test device provided in an embodiment of the present application;
[0029] Figure 2 A schematic diagram of a circuit structure of a test device provided in an embodiment of the present application;
[0030] Figure 3 A schematic diagram of the test flow of the test device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0031] Although the FSMC module is currently widely used in various application scenarios, there is currently no dedicated functional testing for the FSMC module in the industry, and it is impossible to accurately and effectively verify its functions during the design and development phase of the FSMC module. When the FSMC module is set in a specific application device and the performance test of the application device is carried out, it is discovered that the FSMC module's functions are unavailable, which will inevitably affect the application and development of the FSMC module.
[0032] To help those skilled in the art better understand the present invention, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the embodiments described are only a portion of the present invention, not all of the embodiments. All other embodiments derived by those skilled in the art based on the embodiments of the present invention without inventive effort are also within the scope of protection of the present invention.
[0033] like Figure 1 and Figure 2 As shown, Figure 1 A schematic diagram of the principle structure of the test device provided in an embodiment of the present application; Figure 2 A schematic diagram of a circuit structure of a test device provided in an embodiment of the present application.
[0034] It can be understood that the testing device in the present application is mainly used to test the target MCU chip 1 with a built-in FSMC module to determine whether the reading and writing functions of the FSMC module in the target MCU chip 1 are good.
[0035] Reference Figure 1 and Figure 2It can be seen that the FSMC module 10 to be tested in the target MCU chip 1 required to be tested in this application can generally support SRAM (Static Random-Access Memory) read and write functions, NORFLASH read and write functions, NAND FLASH read and write functions, and PC CARD read and write functions.
[0036] Therefore, the read and write interfaces to be tested corresponding to the FSMC module 1 to be tested include the SRAM interface 11, the NOR FLASH interface 12, the NAND FLASH interface 13 and the PC CARD interface 14; in actual applications, the FSMC module 10 to be tested also realizes various different read and write functions through the SRAM interface 11, the NOR FLASH interface 12, the NAND FLASH interface 13 and the PC CARD interface 14 respectively.
[0037] On this basis, in order to implement the read and write function test of the target MCU chip 1 with a built-in FSMC module in this application, the test device in this application may include:
[0038] Test board 2;
[0039] A main controller 20 provided on the test board 2;
[0040] The memory module is provided on the test board 2, and the memory module includes an SRAM module 21, a NOR FLASH module 22, a NAND FLASH module 23 and a PC CARD module 24;
[0041] A plurality of read and write interfaces respectively connected to each memory module;
[0042] The main controller 20 is used to communicate with the target MCU chip 1 and send test instructions to the target MCU chip 1;
[0043] Each memory module is used to connect to each read-write interface of the FSMC module 10 to be tested in the target MCU chip 1 through each read-write interface, and receive read and write operations of the FSMC module 10 to be tested.
[0044] In this embodiment, a main controller 20 and a plurality of different types of memory modules are integrated on the same test board 2; the memory modules are configured based on the read and write functions of the FSMC module 10 to be tested in the target MCU chip 1.
[0045] As described above, the FSMC module 10 to be tested supports SRAM read and write functions, NOR FLASH read and write functions, NANDFLASH read and write functions, and PC CARD read and write functions.
[0046] Correspondingly, the memory modules configured on the test board 2 include an SRAM module 21, a NOR FLASH module 22, a NAND FLASH module 23 and a PC CARD module 24; wherein, the SRAM module 21 includes an SRAM memory chip and its peripheral circuits; the NOR FLASH module 22 includes a NOR FLASH memory chip and its peripheral circuits; the NAND FLASH module 23 includes a NAND FLASH memory chip and its peripheral circuits; and the PC CARD module 24 includes a PC CARD memory chip and its peripheral circuits.
[0047] In addition, in order to achieve communication connection between each memory module on the test board 2 and the FSMC module 10 to be tested in the target MCU chip 1, a read-write interface connected to each memory module should be further provided on the test board 2.
[0048] Based on the read and write functions supported by the FSMC module 10 to be tested, the read and write interfaces to be tested of the FSMC module 10 to be tested include an SRAM interface 11 , a NOR FLASH interface 12 , a NAND FLASH interface 13 , and a PC CARD interface 14 .
[0049] Accordingly, in this embodiment, a plurality of read / write interfaces are provided on the test board 2 for connecting to the above-mentioned read / write interfaces to be tested in a one-to-one correspondence. Each read / write interface may specifically include:
[0050] A first read / write interface connected to the SRAM module 21 and used to connect to the SRAM interface 11, so that the FSMC module 10 to be tested is connected to the SRAM module 21, thereby providing a communication link for the SRAM read / write function of the FSMC module 10 to be tested;
[0051] A second read / write interface connected to the NOR FLASH module 22 and used to connect to the NOR FLASH interface 12, so that the FSMC module 10 to be tested is connected to the NOR FLASH module 22, thereby providing a communication link for the NOR FLASH read / write function of the FSMC module 10 to be tested;
[0052] A third read / write interface connected to the NAND FLASH module 23 and used to connect to the NAND FLASH interface 13, so that the FSMC module 10 to be tested is connected to the NAND FLASH module 23, thereby providing a communication link for the NAND FLASH read / write function of the FSMC module 10 to be tested;
[0053] The fourth read-write interface connected to the PC CARD module 24 is used to connect to the PC CARD interface 14, so that the FSMC module 10 to be tested is connected to the PC CARD module 24, thereby providing a communication link for the PC CARD read-write function of the FSMC module 10 to be tested.
[0054] Furthermore, considering that the FSMC module supports multiple storage peripheral interfaces and there is signal pin multiplexing in the interfaces; when the SRAM interface 11 and the NOR FLASH interface 12 in the various read-write interfaces to be tested of the FSMC module to be tested are the same first shared interface to be tested, then the first read-write interface and the second read-write interface are also the same first shared interface; and the NANDFLASH interface 13 and the PC CARD interface 14 are the same second shared interface to be tested, which are used to be connected to the first shared interface to be tested; and the third read-write interface and the fourth read-write interface are the same second shared interface, which are used to be connected to the second shared interface to be tested.
[0055] In this embodiment, the first shared interface to be tested is used as both the SRAM interface 11 and the NOR FLASH interface 12; accordingly, the first shared interface is both the first read-write interface and the second read-write interface. Similarly, the second shared interface to be tested is used as both the NAND FLASH interface 13 and the PC CARD interface 14; accordingly, the second shared interface is used as both the third read-write interface and the fourth read-write interface. Thus, in actual application, when the first shared interface is connected to the first shared interface to be tested, the FSMC module 10 to be tested can perform SRAM read-write operations and NOR FLASH read-write operations through the first shared interface and the first shared interface to be tested; and when the second shared interface is connected to the second shared interface to be tested, the FSMC module 10 to be tested can perform NAND FLASH read-write operations and PC CARD read-write operations through the second shared interface and the second shared interface to be tested.
[0056] Of course, it is understandable that, based on different actual application requirements, the interface of the FSMC module 10 to be tested in the designed target MCU chip 1 may also have other shared modes, and the read-write interface on the test board 2 can also be configured according to the same shared mode of the interface in the target MCU chip 1. In addition, in actual applications, multiple groups of different read-write interfaces can be configured on the test board 2, wherein one group of read-write interfaces includes a first read-write interface, a second read-write interface, a third read-write interface, and a fourth read-write interface, which are respectively connected to four memory modules; and the second group of read-write interfaces includes a first shared interface and a second shared interface, and each shared interface is connected to two memory modules; there can also be a third group of read-write interfaces, including a first read-write interface, a second read-write interface, and a shared interface, wherein only the first read-write interface and the second read-write interface are each connected to a memory module, and the shared interface is connected to two memory modules; similarly, according to the shared mode of the interface of the FSMC module, corresponding read-write interfaces can also be configured on the test board 2 in other ways, thereby enabling the test device in this embodiment to implement more different forms of testing of the target MCU chip 1 with a built-in FSMC module.
[0057] On the basis that the various read-write interfaces of the FSMC module 10 to be tested are connected to the various memory modules through the various read-write interfaces on the test board 2, the main controller 20 in the test device needs to further establish a communication connection with the target MCU chip 1. The main controller 20 is provided with a GPIO output pin for outputting test instructions to the target MCU chip 1 and a GPIO input pin for receiving the test results uploaded by the target MCU chip 1; the GPIO output pin and the GPIO input pin can be two different pins or the same pin. The main controller 20 can trigger the test program by sending a test instruction to the GPIO output pin of the target MCU chip 1, thereby testing the various read and write functions of the FSMC module 10 to be tested in the target MCU chip 1; after the FSMC module 10 to be tested completes the read and write operation, the target MCU chip 1 can further output the read and write function test to the main controller 20 through the GPIO input pin.
[0058] In the actual test process, you can follow Figure 3 The test flow shown implements the test process of the FSMC module 10. In the test device of this embodiment, the main controller 20 can output corresponding test instructions to the target MCU chip 1 based on the command issued by the host computer.
[0059] As Figure 3Taking the test process shown in the figure as an example, when the main controller 20 receives the command sent by the host computer, it first determines whether the command is a single mode test. The so-called single mode test is to test only the SRAM read and write function, NOR FLASH read and write function, NAND FLASH read and write function and PC One of the CARD read and write functions is tested; if it is not a single mode test, each read and write function of the FSMC module 10 to be tested needs to be tested; when the FSMC module needs to be tested in single mode, it can be further determined which specific read and write function in the FSMC module needs to be tested; for example, the command of the single mode test is an SRAM test, then the main controller 20 can send an SRAM test instruction to the target MCU chip 1, and the target MCU chip 1 also controls the FSMC module 10 to be tested to perform read and write operations on the SRAM module 21. If the read and write operations on the SRAM module 21 are successful, it means that the SRAM read and write functions of the FSMC module 10 to be tested are good. After the SRAM read and write function operations are completed, the target MCU chip 1 feeds back the test results to the main controller 20, and the test process ends. However, when the command sent by the upper computer is not a single-mode test, that is, each read and write function in the FSMC module 10 to be tested needs to be tested in turn, the main controller 20 will output SRAM test instructions, NOR FLASH test instructions, NAND FLASH test instructions and PC CARD test instructions to the FSMC module 10 to be tested in turn, thereby causing the FSMC module 10 to be tested to execute read and write operations on the SRAM module 21, NOR FLASH module 22, NAND FLASH module 23 and PC CARD module 24 in turn, until the results of all read and write operations are fed back to the main controller 20, and the entire test process ends.
[0060] Of course, it is understandable that the main controller 20 in the test device of this embodiment does not necessarily need to execute the following Figure 3The program flow shown, for example, when the host computer needs to control the test device to perform different types of tests, it can send different types of test commands to the main controller 20 respectively, and the main controller 20 can output corresponding test instructions to the FSMC module 10 to be tested based on different test commands; for example, the main controller 20 outputs test instructions for each read and write function to the FSMC module 10 to be tested in a fixed order, which can also implement the technical solution of the present application. Regardless of which test flow program the main controller 20 needs to execute, the test flow program can be implemented based on a conventional computer program and is not the key to the improvement of the present application. The key in the present application is to integrate the main controller 20 with this function and each memory module on the same test board 2 to achieve the test of the target MCU chip 1, which meets the protection object of the utility model.
[0061] As described above, in order to realize the communication connection between the main controller 20 and the host computer, a wireless communication module and / or a wired communication interface can be further provided on the test board 2 in this embodiment; the wireless communication module and the wired communication interface are both connected to the main controller 20, so that the main controller 20 can be connected to the host computer through at least one of the wireless communication module or the wired communication interface; the wired communication interface can be a USB interface, a Type-C interface, etc.
[0062] Of course, in actual applications, the main controller 20 in the test device does not necessarily need to be connected to the host computer to implement the test process. Figure 1 and Figure 2 As shown, in another optional embodiment of the present application, the testing device may further include:
[0063] The test board 2 is also provided with a start switch 25 connected to the main controller 20 ; when the start switch 25 is closed, the main controller 20 outputs a test instruction to the target MCU chip 1 .
[0064] like Figure 1 and Figure 2As shown, in this embodiment, a start switch 25 is further configured on the test board 2. The start switch 25 can be a switch that is manually opened or closed, such as a mechanical switch such as a key switch or a knob switch, or a non-mechanical switch such as a touch switch. When the start switch 25 is operated and closed, it triggers the main controller 20 to generate a start signal, and the main controller 20 can trigger the output of a test instruction to the target MCU chip 1 based on the start signal, thereby starting the entire test process. Therefore, in actual application, when the test device and the host computer are in an online communication state, the test process of the test device can be triggered by the host computer, and when the test device and the host computer are in a disconnected state, the test process can be directly triggered by manually operating the start switch 25. Of course, even if the host computer and the main controller 20 are in a state of mutual communication, the main controller 20 can also be triggered to start the test process by the start switch 25; in addition, this application does not exclude the possibility that the main controller 20 in the test device can only trigger the start of the test process through one of the host computer and the start switch 25.
[0065] On this basis, in an optional implementation of this embodiment, the start switch 25 may further include:
[0066] A plurality of ones corresponding one to one to each read / write interface to be tested;
[0067] When one of the start switches 25 is closed, the main controller 20 outputs a test instruction of the read / write interface to be tested corresponding to the closed start switch 25 to the target MCU chip 1 .
[0068] As described above, the FSMC module 10 to be tested in the target MCU chip 1 has a variety of different read and write functions. Therefore, during actual testing, one read and write function of the FSMC module 10 to be tested can be tested, or all of its read and write functions can be completely tested one by one. Therefore, in order to trigger the test of different read and write functions of the FSMC module 10 to be tested through the start switch 25, multiple start switches 25 can be configured respectively, and each start switch 25 corresponds to a test mode for triggering the read and write function of the FSMC module 10 to be tested; for example, in actual application, the start switch 25 may include a first start switch, a second start switch, a third start switch, a fourth start switch and a main start switch; when the first start switch is operated and closed, the main controller 20 outputs an SRAM test instruction to the FSMC module 10 to be tested, when the second start switch is operated and closed, the main controller 20 outputs a NOR FLASH test instruction to the FSMC module 10 to be tested, and when the third start switch is operated and closed, the main controller 20 outputs a NAND to the FSMC module 10 to be tested. FLASH test instruction. When the fourth start switch is operated and closed, the main controller 20 outputs the PC CARD test instruction to the FSMC module 10 to be tested; and when the main start switch is operated and closed, the main controller 20 outputs the main test instruction to the FSMC module 10 to be tested, thereby starting the process of testing all read and write functions of the FSMC module 10 to be tested one by one.
[0069] Based on the above discussion, after the FSMC module 10 to be tested performs the read and write function operations, the target MCU chip 1 needs to feedback the test results of whether each read and write operation is successful or not to the main controller 20 in the test device. In order to display this test result more intuitively, in another optional embodiment of the present application, the test device may further include a display module 26 connected to the main controller 20 on the test board 2 for displaying the test results.
[0070] The display module 26 in this embodiment can be a display screen or an LED indicator light, or other types of display devices, which are not specifically limited in this embodiment.
[0071] Taking the display module 26 as an LED indicator light as an example, the display module 26 may include multiple LED indicator lights, and the LED indicator lights may be different in at least one of light emitting color and flashing frequency.
[0072] For example, in Figure 2 In the embodiment shown, three LED indicator lights are provided. When the test result fed back by the target MCU chip 1 is a successful read or write, the green LED indicator light is on; when the test result is a read or write failure, the red LED indicator light is on; and when the test result is a successful write but a read failure, the yellow LED indicator light is on.
[0073] It can be understood that, for the test results fed back by the target MCU chip 1, in addition to being displayed using the display module 26 and uploaded to the host computer, they can also be further stored and recorded. For this purpose, in another optional embodiment of the present application, the test board 2 of the test device is also provided with an SPI FLASH module 27 connected to the main controller 20 for storing the test results, thereby facilitating subsequent retrieval and viewing of the test results at any time.
[0074] Furthermore, to provide electrical energy to the various components in the test apparatus, in an optional embodiment of the present application, a DC power supply 28 may be provided on the test board 2 of the test apparatus. The output of the DC power supply 28 may be electrically connected to the power supply inputs of the main controller 20, the memory module, and other electrical components on the test board 2. In practical applications, the DC power supply 28 may be a rechargeable power supply or a removable and replaceable battery, etc., and this application does not impose any specific limitations thereon.
[0075] To sum up, the test device of the present application is equipped with multiple different memory modules such as SRAM module, NOR FLASH module, NAND FLASH module, PC CARD module, etc. for each different read and write function of the FSMC module. Therefore, after the main controller sends a test instruction to the target MCU chip with a built-in FSMC module, the target MCU chip can trigger its built-in FSMC module to perform read and write operations on each memory module, which is equivalent to simulating the read and write operation process of the FSMC module in the target MCU chip. Based on whether the FSMC module succeeds or not in the read and write operations on each memory module, it can be determined whether the read and write functions of the FSMC module are good, and then the read and write function test of the target MCU chip with a built-in FSMC module is realized. The complete and rapid functional verification of the FSMC module in the MCU can be realized during the design and verification stages of the MCU chip to ensure that the FSMC module meets the functional requirements and effectively reduce the time cost and testing cost of MCU chip design.
[0076] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements are inherent to the elements. In the absence of further restrictions, the elements limited by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device comprising the elements. In addition, the above-mentioned technical solutions provided in the embodiments of the present application are not described in detail in accordance with the corresponding technical solutions in the prior art to achieve the same principle, so as to avoid excessive elaboration.
[0077] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The above examples are only intended to help understand the method and core concept of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention.
Claims
1. A testing device, characterized in that: Used to test the target MCU chip with a built-in FSMC module, the test device includes: Test board; A main controller provided on the test board; A memory module is provided on the test board, wherein the memory module includes an SRAM module, a NOR FLASH module, a NAND FLASH module and a PC CARD module; A plurality of read-write interfaces respectively connected to the memory modules; The main controller is used to communicate with the target MCU chip to send a test instruction to the target MCU chip; Each of the memory modules is used to connect to each read-write interface of the FSMC module to be tested in the target MCU chip through each read-write interface, and receive the read-write operation of the FSMC module to be tested.
2. The testing device according to claim 1, wherein: The read-write interface to be tested includes an SRAM interface, a NORFLASH interface, a NAND FLASH interface and a PC CARD interface; Correspondingly, the read-write interface includes a first read-write interface, a second read-write interface, a third read-write interface and a fourth read-write interface, which correspond one-to-one to each of the read-write interfaces to be tested; Wherein, the SRAM interface and the NOR FLASH interface are the same first shared interface to be tested; the NAND FLASH interface and the PC CARD interface are the same second shared interface to be tested; The first read-write interface and the second read-write interface are the same first shared interface, used to connect to the first shared interface to be tested; the third read-write interface and the fourth read-write interface are the same second shared interface, used to connect to the second shared interface to be tested.
3. The testing device according to claim 1, wherein: The main controller is provided with a GPIO output pin for outputting a test instruction to the target MCU chip and a GPIO input pin for receiving a test result uploaded by the target MCU chip.
4. The testing device according to claim 1, wherein: The test board is provided with a wireless communication module and / or a wired communication interface connected to the main controller; The main controller is connected to the host computer through the wireless communication module or the wired communication interface.
5. The testing device according to claim 1, wherein: The test board is also provided with a start switch connected to the main controller; when the start switch is closed, the main controller outputs a test instruction to the target MCU chip.
6. The testing device according to claim 5, wherein: The start switch includes a plurality of switches corresponding to each of the read-write interfaces to be tested; When one of the start switches is closed, the main controller outputs a test instruction of the read-write interface to be tested corresponding to the closed start switch to the target MCU chip.
7. The testing device according to claim 1, wherein: The test board is also provided with a display module connected to the main controller for displaying the test results.
8. The testing device according to claim 7, wherein: The display module includes a plurality of LED indicator lights; wherein each of the LED indicator lights is an indicator light of a different luminous color and / or a different flashing frequency.
9. The testing device according to claim 1, wherein: The test board is also provided with an SPI FLASH module connected to the main controller for storing test results.
10. The testing device according to claim 1, wherein: The test board is also provided with a DC power supply connected to the main controller and each of the memory modules respectively.