Semiconductor package with at least one prefabricated conductive unit

Abstract

The utility model relates to a semiconductor package having at least one prefabricated conductive unit. A semiconductor package includes at least one semiconductor die, a molding layer for encapsulating the at least one semiconductor die; at least one prefabricated conductive unit, the at least one prefabricated conductive unit being prepared from a molded conductive substrate; a front-side build-up layer electrically coupled to the at least one semiconductor die and the at least one prefabricated conductive unit; and an external connection layer electrically coupled to the front-side build-up layer. The at least one semiconductor die may include a first semiconductor die and a second semiconductor die, which may be arranged in a juxtaposed manner or a vertical manner.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority from Singapore application No. 10202303101X, filed on November 2, 2023, the disclosure of which is incorporated herein in its entirety. Technical Field

[0003] The present application relates to a prefabricated conductive unit for a semiconductor package and also relates to a semiconductor package having the prefabricated conductive unit. Background Art

[0004] Traditionally, vertical electrical connections are typically formed during the semiconductor package manufacturing process. For example, multiple build-up layers can be formed using in-situ metallization processes during small-scale semiconductor package manufacturing. However, these traditional methods can cause severe warpage issues when used in large-scale panel-level processes. Furthermore, in-situ metallization processes are too slow to form vertical electrical connections. Utility Model Content

[0005] As a first aspect of the present application, a semiconductor package having at least one prefabricated conductive unit is disclosed, which includes at least one semiconductor bare chip; a mold layer for encapsulating the at least one semiconductor bare chip; at least one prefabricated conductive unit, wherein the at least one prefabricated conductive unit is prepared from a molded conductive substrate; a front-side building layer electrically coupled to the at least one semiconductor bare chip and the at least one prefabricated conductive unit; and an external connection layer electrically coupled to the front-side building layer. The at least one prefabricated conductive unit can lead out the functional circuit of the at least one semiconductor bare chip. At the same time, because it is formed before the semiconductor package manufacturing process, it overcomes the serious warping problem caused by traditional on-site metal electroplating processes in large-scale panel-level processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings illustrate embodiments of the present application for explaining the principles disclosed in the present application. However, it should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of the present application.

[0007] Figure 1 FIG. 1 is a flowchart of a panel-level method S10 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0008] Figures 2a to 2g A first embodiment of steps S11 and S12 of the panel-level method S10 is shown.

[0009] Figure 2a ' shows an enlarged cross-sectional view of an independent first conductive portion in one embodiment.

[0010] Figure 2b FIG. ' shows an enlarged cross-sectional view of an independent second conductive portion in one embodiment.

[0011] Figures 3a to 3f A second embodiment of steps S11 and S12 of the panel-level method S10 is shown.

[0012] Figures 4a to 4d A third embodiment of steps S11 and S12 of the panel-level method S10 is shown.

[0013] Figure 5a and Figure 5b Step S13 of the panel-level method S10 is shown.

[0014] Figure 6 Step S14 of the panel-level method S10 is shown.

[0015] Figures 7a to 7c Step S15 of the panel-level method S10 is shown.

[0016] Figure 8 and Figure 9 Step S16 of the panel-level method S10 is shown.

[0017] Figure 10a and Figure 10b Step S17 of the panel-level method S10 is shown.

[0018] Figure 11 Step S18 of the panel-level method S10 is shown.

[0019] Figure 12 Step S19 of the panel level method S10 is shown.

[0020] Figures 13a to 13e Several embodiments of semiconductor packages (single chip modules (SCMs)) obtained from the panel-level method S10 are shown.

[0021] Figures 14 to 17 Another embodiment of the panel-level method S10 is shown.

[0022] Figures 18a to 18c Shows the use of Figures 14 to 17 Several embodiments of semiconductor packages (SCMs) are obtainable by the methods shown.

[0023] Figures 19a to 19c A variation of the first embodiment of steps S11 and S12 of the panel-level method S10 is shown for a multi-chip module (MCM).

[0024] Figures 20a to 20c A variation of the second embodiment of steps S11 and S12 of panel-level method S10 is shown for a multi-chip module (MCM).

[0025] Figures 21a to 21c A variation of the third embodiment of steps S11 and S12 of the panel-level method S10 is shown for a multi-chip module (MCM).

[0026] Figure 22a and Figure 22b Step S13 of the panel-level method S10 for a multi-chip module (MCM) is shown.

[0027] Figure 23 Step S14 of the panel-level method S10 for a multi-chip module (MCM) is shown.

[0028] Figure 24 Step S15 of the panel-level method S10 for a multi-chip module (MCM) is shown.

[0029] Figure 25 and Figure 26 Step S16 of the panel-level method S10 for a multi-chip module (MCM) is shown.

[0030] Figure 27a and Figure 27b Step S17 of the panel-level method S10 for a multi-chip module (MCM) is shown.

[0031] Figure 28 Steps S18 and S19 of the panel-level method S10 for a multi-chip module (MCM) are shown.

[0032] Figures 29a to 29e Several embodiments of semiconductor packages (multi-chip modules (MCMs)) obtained from the panel-level method S10 are shown.

[0033] Figures 30 to 33 A variation of the panel-level method S10 is shown.

[0034] Figures 34a to 34c Shown as Figures 30 to 33 The method shown may provide several embodiments of semiconductor packages (multi-chip modules (MCMs)).

[0035] Figure 35 Another embodiment of step S12 of the panel-level method S10 is shown.

[0036] Figures 36a to 36c Shown as Figure 35 Several embodiments of semiconductor packages (multi-chip modules (MCMs)) are obtained by the method shown.

[0037] Figures 37a to 37dSeveral embodiments of semiconductor packages (multi-chip modules (MCMs)) obtained from the panel-level method S10 are shown.

[0038] Figure 38 FIG. 1 is a flowchart of another panel-level method S20 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure.

[0039] Figures 39a to 39i A schematic diagram of the panel-level method S20 is shown.

[0040] Figure 40a and Figure 40b Shown as Figures 39a to 39i Two embodiments of available semiconductor packages (multi-chip modules (MCM)) are shown.

[0041] Reference numerals:

[0042] 100a Molded Interconnect Substrate (MIS) 110a First Conductive Portion

[0043] 110b second conductive portion 112a interconnection wiring layer

[0044] 1122a first wiring layer 1123a first side

[0045] 1124a second wiring layer 1125a second side

[0046] 112b conductive through hole 1122b through hole front surface

[0047] 1124b through hole rear surface 1126 hollow through hole

[0048] 1128 side wall 114a / 114b insulation assembly

[0049] 1142a / 1142b first surface 1144a / 1144b second surface

[0050] 116 prefabricated conductive unit 1162 first prefabricated conductive unit

[0051] 1164 Second prefabricated conductive unit 1161 First prefabricated conductive unit

[0052] 1162 Prefabricated conductive unit second piece 1163 Prefabricated conductive unit third piece

[0053] 118 gap 1182 first gap

[0054] 1184 second gap 120 insulation part

[0055] 130 first carrier 132 die bonding area

[0056] 133 Main mark 134 unit bonding area

[0057] 135 auxiliary mark 136 reference point

[0058] 140 first thermal release tape 150 semiconductor bare chip

[0059] 150a first semiconductor die 150b second semiconductor die

[0060] 1502 active surface 1504 back surface

[0061] 152 contact pad 154 protective layer

[0062] 156 Pre-through hole 158 Filling through hole

[0063] 160 molding layer 162 top

[0064] 164 grinding equipment 170 reconstruction panel

[0065] 180 front side building layer 182 front side dielectric layer

[0066] 1822 first dielectric surface 184 front side trace

[0067] 186 front stud 1862 first stud surface

[0068] 188 stud cavity 190 rear side building layer

[0069] 192 rear side through hole 194 rear side filling through hole

[0070] 1942 first through hole surface 1944 second through hole surface

[0071] 196 Backside dielectric layer 198 Backside trace

[0072] 199 rear stud 1992 second stud surface

[0073] 200 second carrier 210 second heat release tape 220 External connection layer (solder ball) 230a-230e Semiconductor package (single chip 240 Passive Component Module (SCM)

[0074] 250 top semiconductor package 254 internal connection layer (solder balls)

[0075] 252 package dielectric layer 260 heat sink

[0076] 256 internal spaces 272 additional traces

[0077] 270 Additional build-up layer 276 Additional through-hole

[0078] 274 additional dielectric layers 280a-280c ​​semiconductor package (SCM) 278 additional filled vias 292 antenna

[0079] 290a-290e semiconductor package (MCM) 322 copper pillar

[0080] 300a-300c, 310a-310c, 320a-320d, 340a 332 intermediate dielectric layer

[0081] -340b semiconductor package (MCM) 336 intermediate traces

[0082] 330 interposer 350 external devices

[0083] 334 Intermediary filled through hole 3362 first intermediate trace surface DETAILED DESCRIPTION

[0084] Figure 1 FIG. 1 is a flow chart of a panel-level method S10 for manufacturing a semiconductor package according to an exemplary embodiment of the present disclosure. The panel-level method S10 includes steps S11 to S19 .

[0085] Figures 2a to 4d Three embodiments of steps S11 and S12 of the panel-level method S10 are shown. Figures 2a to 2g A first embodiment is shown, wherein step S11 includes a first sub-step S112, namely, mounting the molded conductive substrate on a first carrier 130. Optionally, a first thermal release tape 140 is applied between the molded conductive substrate and the first carrier 130. The first thermal release tape 140 is used to secure the molded conductive substrate to the first carrier 130 at room temperature. The molded conductive substrate has a conductive portion that extends through the molded conductive substrate in the thickness direction. The molded conductive substrate may also have an insulating portion 120 that holds the molded conductive substrate in one piece when mounted on the first carrier 130. The insulating portion 120 may be made of any electrically insulating material, such as a molding material. The conductive portion may also include a conductive component and an insulating component.

[0086] Figure 2a A cross-sectional view of one embodiment of a molded conductive substrate is shown, wherein the molded conductive substrate may be a molded interconnect substrate (MIS) 100a. The molded interconnect substrate (MIS) 100a has a first conductive portion 110a (as a type of conductive portion) separated by an insulating portion 120; the insulating portion 120 may be removed along the dashed line shown. Figure 2aFIG. 1 shows an enlarged cross-sectional view of the isolated first conductive portion 110a after the insulating portion 120 has been removed. Thus, the isolated first conductive portion 110a becomes a form of a separate prefabricated conductive unit 116. As a type of conductive assembly, the first conductive portion 110a includes a plurality of interconnecting wiring layers 112a for electrically conducting electricity along the thickness of the first conductive portion 110a, located between the first wiring layers 1122a and the second wiring layers 1124a. The first conductive portion 110a also includes an insulating component 114a, such as a molding material, for encapsulating the interconnecting wiring layers 112a. The insulating component 114a may be part of the electrically insulating material of the insulating portion 120 extending into the first conductive portion 110a. However, the first wiring layers 1122a and the second wiring layers 1124a are not enclosed within the insulating component 114a. In other words, the first side 1123a defining the first thickness of the first wiring layers 1122a is exposed from the first surface 1142a of the insulating component 114a. Similarly, the second side 1125a for defining the second thickness of the second wiring layer 1124a is also exposed from the second surface 1144a of the insulating component 114a. The first thickness of the first wiring layer 1122a and the second thickness of the second wiring layer 1124a can be the same or different.

[0087] Figure 2b A cross-sectional view of another embodiment of a molded conductive substrate is shown, wherein the molded conductive substrate may be a molded via substrate (MVS). Similarly, the molded via substrate (MVS) also has a second conductive portion 110b (as another type of conductive portion) separated by an insulating portion 120. The insulating portion 120 may also be removed along the dashed line shown. Figure 2b FIG1 shows an enlarged cross-sectional view of the independent second conductive portion 110b after the insulating portion 120 is removed. Thus, the independent second conductive portion 110b becomes another form of a separate prefabricated conductive unit 116. The second conductive portion 110b includes one or more conductive vias 112b as another type of conductive component. These can conduct electricity along the thickness direction between a via front surface 1122b and a via rear surface 1124b. The second conductive portion 110b may also include an insulating component 114b, such as a molding material for encapsulating the conductive via 112b. The insulating component 114b may be a portion of the electrically insulating material of the insulating portion 120 that extends into the second conductive portion 110b. Specifically, the conductive via 112b extends through the insulating component 114b; and the via front surface 1122b and via rear surface 1124b of the conductive via 112b are flush with the first surface 1142b and the second surface 1144b of the insulating component 114b, respectively.

[0088] The molded through-hole substrate (MVS) can be formed by first forming one or more hollow through-holes 1126 in the second conductive portion 110b through the insulating component 114b, and then completely or partially filling the hollow through-holes 1126 with any conductive material such as copper. Preferably, the hollow through-holes 1126 are partially filled to save the conductive material used to fill the hollow through-holes 1126, thereby reducing the weight of the second conductive portion 110b, thereby further eliminating warping that may occur in subsequent processes. Figure 2b As shown, the conductive material adheres only to the sidewalls 1128 of hollow via 1126, leaving the central region of hollow via 1126 partially unfilled. However, the amount of conductive material that is filled is sufficient to form a continuous conductive path along the sidewalls 1128 between the front surface 1122b and the rear surface 1124b of conductive via 112b. It should be understood that molded interconnect substrate (MIS) 100a and molded via substrate (MVS) are merely two examples of molded conductive substrates; other types of molded conductive substrates are also within the scope of this application. Accordingly, first conductive portion 110a and second conductive portion 110b are merely two examples of conductive portions (and, if separated, prefabricated conductive elements 116); other types of conductive portions (and, if separated, prefabricated conductive elements 116) are also within the scope of this application. For ease of explanation, only the molded interconnect substrate (MIS) 100a is used as the molded conductive substrate, and only the first conductive portion 110a is used as the conductive portion (and the prefabricated conductive unit 116 after separation) to illustrate the subsequent steps of S10. However, it should be understood that the following description is also applicable to other forms of molded conductive substrates and conductive portions, including molded through-hole substrates (MVS) and second conductive portions 110b.

[0089] Figure 2c As shown in the top view, the insulating portion 120 can be removed along the dashed lines in the width direction. Then, the first conductive portion 110a of the molded interconnect substrate (MIS) 100a can also be divided along the dotted lines in the length direction. In this way, the first conductive portion 110a surrounded by the dashed and dotted lines can form a prefabricated conductive unit 116. Figure 2dA cross-sectional view shows step S11 including the second sub-step S114, wherein insulating portion 120 is removed from molded interconnect substrate (MIS) 100a and first conductive portions 110a are separated, thereby forming prefabricated conductive units 116. Thus, gaps 118 are formed between first conductive portions 110a at the original locations of insulating portion 120. Compared to conventional methods of making vertical electrical connections during semiconductor packaging, such as in-situ metal plating, prefabricated conductive units 116 are formed prior to the panel-level packaging process of bonding semiconductor die 150 to first carrier 130. Therefore, S10 of the present application can significantly reduce or even eliminate the severe warpage problem that occurs in conventional methods.

[0090] Figure 2e The top view of FIG1 shows that the first carrier 130 has a die bonding area 132 (shown as a dashed rectangle) at the gap 118 for accommodating a semiconductor die 150. The die bonding area 132 has primary marks 133 therein for guiding the semiconductor die 150 to be bonded to its corresponding predetermined position within the die bonding area 132. Although the die bonding area 132 is shown as having four primary marks 133 at each of its four corners, other numbers and distributions of primary marks 133 are also within the scope of the present application.

[0091] Figure 2f The cross-sectional view of step S12 shows bonding of a semiconductor die 150 within its die bonding region 132. Semiconductor die 150 has one or more contact pads 152 on its active surface 1502 for leading out functional circuits, a protective layer 154 formed on active surface 1502 for protecting the functional circuits, and one or more pre-vias 156 in protective layer 154 for exposing contact pads 152 from protective layer 154. Semiconductor die 150 is bonded face-down, with protective layer 154 in contact with first thermal release tape 140 or first carrier 130. Figure 2g The top view of FIG. 1 shows that the semiconductor die 150 has been bonded to the die bonding area 132 on the first carrier 130. Preferably, the primary mark 133 is not covered by the semiconductor die 150 so that a post-bonding inspection process can be performed to check whether the semiconductor die 150 is bonded to the predetermined position within its respective die bonding area 132.

[0092] In contrast to the first embodiment, the insulating portion 120 may not be removed after the molded conductive substrate is mounted on the first carrier 130. Instead, the insulating portion 120 is removed elsewhere, and the independent conductive portion becomes a separate prefabricated conductive unit 116. The prefabricated conductive unit 116 is then bonded to its predetermined position on the first carrier 130. Figures 3a to 3f A second embodiment of steps S11 and S12 of the panel-level method S10 is shown. Figure 3a and Figure 3b The cross-sectional view of step S11 is shown, that is, the prefabricated conductive unit 116 (for example, Figure 3a and Figure 3b In addition to the die bonding area 132 for accommodating the semiconductor die 150 and the main mark 133, Figure 3c As shown in the top view of FIG, the first carrier 130 may also have a cell bonding area 134 (shown as a dashed rectangle in the figure) for accommodating the prefabricated conductive elements 116. Auxiliary marks 135 within the cell bonding area 134 may be used to guide the prefabricated conductive elements 116 to their predetermined positions. Although the figure shows four auxiliary marks 135 located at the four corners of the cell bonding area 134, it will be understood that other numbers and distributions of auxiliary marks 135 are also within the scope of this application. Preferably, the auxiliary marks 135 are not covered by the prefabricated conductive elements 116, so that a post-bonding inspection process can be performed to check whether the prefabricated conductive elements 116 are bonded to their respective predetermined positions. Alternatively, if the first carrier 130 does not have auxiliary marks 135, the main marks 133 may also be used to guide the prefabricated conductive elements 116 during bonding. In addition, the first carrier 130 may also have fiducials 136 for locating the die bonding area 132 and the cell bonding area 134 on the first carrier 130.

[0093] Figure 3d A cross-sectional view of step 12 in the second embodiment is shown, ie, bonding the semiconductor die 150 to the corresponding die bonding area 132 on the first carrier 130 . Figure 3e and Figure 3f 1 shows a cross-sectional view and a top view of bonding a prefabricated conductive element 116 and a semiconductor die 150 to a first carrier 130 according to a package design. Instead of the primary mark 133, the semiconductor die 150 can also be guided by the auxiliary mark 135 during bonding. If the bonding is performed accurately, the semiconductor die 150 and the prefabricated conductive element 116 can be easily positioned on the first carrier 130 using the primary mark 133 and / or the auxiliary mark 135. The primary mark 133 and / or the auxiliary mark 135 can then be further positioned using the fiducials 136.

[0094] Similar to the second embodiment above, Figures 4a to 4c A third embodiment of steps S11 and S12 of the panel level method S10 is shown. In the third embodiment, steps S11 and S12 are performed in the reverse order of the second embodiment. Figure 4aAs shown, first, step S12 is performed to bond the semiconductor die 150 to the first carrier 130. Then, step S11 is performed to bond the prefabricated conductive unit 116 (shown in the form of the first conductive portion 110a) to the first carrier 130, as shown. Figure 4b As shown. Figure 4c The cross-sectional view shows that the prefabricated conductive unit 116 and the semiconductor die 150 are bonded to respective predetermined positions on the first carrier 130 . Figure 4d and Figure 4c The difference is that the prefabricated conductive unit 116 is bonded in the form of the second conductive portion 110b. Therefore, the third embodiment can also achieve the same Figure 3f If bonding is performed accurately, the semiconductor die 150 and the prefabricated conductive unit 116 can be easily positioned on the first carrier 130 by the main mark 133 and / or the auxiliary mark 135 , and the main mark 133 and the auxiliary mark 135 can be further positioned by the fiducial 136 .

[0095] Figure 5a and Figure 5b Step S13 of the panel-level method S10 is shown, which is to form a mold layer 160 for encapsulating the prefabricated conductive unit 116 (shown in the form of the first conductive portion 110a) and the semiconductor die 150, thereby forming a reconstructed panel 170. In particular, the first wiring layer 1122a and the second wiring layer 1124a of the first conductive portion 110a are encapsulated in the mold layer 160. The mold layer 160 can be implemented by any known molding process, such as compression molding. Figure 5a The cross-sectional view of FIG. 1 shows that the pre-via 156 of the semiconductor die 150 is not filled before the semiconductor die 150 is bonded to the first carrier 130. Figure 5b As shown, the pre-via 156 of the semiconductor die 150 may be filled with a conductive material before bonding the semiconductor die 150 to the first carrier 130. Thus, a filled via 158 is formed in the protection layer 154 and electrically coupled to the contact pad 152 to further lead out the functional circuit of the semiconductor die 150.

[0096] Figure 6 Step S14 of panel-level method S10 is shown, which involves removing a portion of mold layer 160 from the back side 1504 of semiconductor die 150 by any known method (e.g., grinding equipment 164), thereby thinning mold layer 160. Step S14 is optional when the thickness of mold layer 160 is greater than the package design. Specifically, a top portion 162 of mold layer 160 remains to encapsulate prefabricated conductive element 116 and semiconductor die 150 (including back side 1504 of semiconductor die 150).

[0097] Figures 7a to 7c Step S15 of the panel-level method S10 is shown, namely forming a back-side build-up layer 190 on the prefabricated conductive unit 116 . Figure 7a A first sub-step S152 of step S15 is shown, ie, forming a backside through hole 192 in the top portion 162 of the mold layer 160 for exposing the second wiring layer 1124a of the first conductive portion 110a. Figure 7b The second sub-step S154 of step S15 is shown, which is to fill the backside via 192 with a conductive material to form a backside filled via 194. The backside filled via has a first via surface 1942 electrically coupled to the second wiring layer 1124a and a second via surface 1944 exposed from the top 162 of the mold layer 160. Figure 7c A third sub-step S156 of step S15 is shown, namely forming a backside trace 198 electrically coupled to the backside filled via 194 , and a backside dielectric layer 196 for encapsulating the backside trace 198 .

[0098] Figure 8 and Figure 9 Step S16 of panel-level method S10 is shown, namely transferring the reconstructed panel 170 with the backside build-up layer 190 onto a second carrier 200 . Figure 8 The first sub-step S162 of step S16 is shown, which is to separate the reconstructed panel 170 with the backside build-up layer 190 from the first carrier 130 and the first thermal release tape 140. The first sub-step S162 can be performed by heating the first thermal release tape 140 to a certain elevated temperature, because at a certain elevated temperature, the first thermal release tape 140 will lose its ability to adhere to the reconstructed panel 170. Figure 9 The second sub-step S164 of step S16 is shown, namely, mounting reconstructed panel 170 with backside build-up layer 190 on second carrier 200 in a flipped manner, such that backside dielectric layer 196 contacts second carrier 200, and contact pads 152 (through pre-vias 156) and first wiring layer 1122a of first conductive portion 110a are exposed from mold layer 160. Similarly, second thermal release tape 210 may also be applied between backside build-up layer 190 and second carrier 200 to secure reconstructed panel 170 with backside build-up layer 190 to second carrier 200 at room temperature.

[0099] Figure 10a and Figure 10b Step S17 of the panel-level method S10 is shown, namely forming a front-side build-up layer 180 on the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122 a of the first conductive portion 110 a . Figure 10a The first sub-step S172 of step S17 is shown. Figure 5aAs shown, if the pre-via 156 is not filled before the semiconductor die 150 is bonded to the first carrier 130, the pre-via 156 is filled with a conductive material to form a filled via 158. Figure 5b , that is, the pre-via 156 has been filled before the semiconductor die 150 is bonded to the first carrier 130 , then sub-step S172 may be skipped. Figure 10b The second sub-step S174 of step S17 is shown, namely, forming a front-side build-up layer 180 on the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122a of the first conductive portion 110a. Front-side build-up layer 180 includes front-side traces 184 electrically coupled to the filled vias 158, front-side studs 186 electrically coupled to the front-side traces 184, and a front-side dielectric layer 182 encapsulating the front-side traces 184 and the front-side studs 186. Front-side studs 186 have first stud surfaces 1862 exposed from the front-side dielectric layer 182. In one embodiment, first stud surfaces 1862 are coplanar with first dielectric surface 1822 of the front-side dielectric layer 182. In another embodiment, first stud surfaces 1862 are exposed from the first dielectric surface 1822 of the front-side dielectric layer 182 through stud cavities 188. The stud cavity 188 may have a cavity depth in the range of 1 to 15 micrometers (μm), or more specifically in the range of 1 to 5 micrometers (μm), in the range of 3 to 6 micrometers (μm), or in the range of 5 to 15 micrometers (μm).

[0100] Figure 11 Step S18 of panel-level method S10 is shown, which involves forming an external connection layer 220, such as solder balls. The cross-sectional view shows the placement and electrical coupling of solder balls (as external connection layer 220) to front-side studs 186. Preferably, the solder balls are first melted and fused into stud cavities 188 before being coupled to front-side studs 186, thereby securely securing the solder balls during subsequent processing. It should be understood that other forms of external connection layer 220, such as copper pillars 322, are also within the scope of this application.

[0101] Figure 12 Step S19 of the panel-level method S10 is shown, which is to separate the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 from the second carrier 200 and the second thermal release tape 210, and then divide the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 into individual semiconductor packages (single-chip modules (SCM)) along saw lines (indicated by dotted lines in the figure).

[0102] Figures 13a to 13e Several embodiments of semiconductor packages 230 a to 230 e (single chip modules (SCMs)) obtained from the panel-level method S10 are shown. Figure 13aA cross-sectional view of semiconductor package 230a is shown, in which functional circuitry of semiconductor die 150 is electrically brought out through contact pads 152, filled vias 158, frontside traces 184 and frontside studs 186 of frontside build-up layer 180, and external connection layer 220 (e.g., solder balls). Figure 13b A cross-sectional view of semiconductor package 230 b is shown, wherein backside build-up layer 190 further includes backside stud 199 coupled to backside trace 198. Backside stud 199 has a second stud surface 1992 exposed from backside dielectric layer 196 so that a passive device 240 (e.g., a capacitor) can be mounted on and electrically coupled to backside build-up layer 190. Figure 13c A cross-sectional view of the semiconductor package 230c is shown, wherein the back side 1504 of the semiconductor die 150 is exposed from the molding layer 160. Thus, the heat spreader 260 can be mounted to and in direct contact with the back side 1504 of the semiconductor die 150 to enhance heat dissipation. Figure 13d A cross-sectional view of a semiconductor package 230d is shown, wherein a top semiconductor package 250 can be mounted and electrically coupled to a backside build layer 190 to form a package-on-package (PoP) configuration. Preferably, the top semiconductor package 250 is encapsulated within a packaging dielectric layer 252. At the same time, the packaging dielectric layer 252 can also act as an underfill to protect the internal connection layer 254 (e.g., solder balls). Compared to conventional molding materials (e.g., Sumitomo G730), the packaging dielectric layer 252 has a smaller fill size, so that the packaging dielectric layer 252 can enter the internal space 256 around the internal connection layer 254. Optionally, the fill size of the packaging dielectric layer 252 is less than 20 microns (μm); preferably, the fill size of the packaging dielectric layer 252 is between 10 and 20 microns (μm). Figure 13e A cross-sectional view of the semiconductor package 230 e is shown without the backside build-up layer 190 ; the first conductive portion 110 a , which is a prefabricated conductive unit 116 , is fully encapsulated within the mold layer 160 .

[0103] Figures 14 to 17 A variation of the panel-level method S10 is shown, which further includes an additional build-up layer 270 located above the active surface 1502 of the semiconductor die 150 and the first wiring layer 1122a of the first conductive portion 110a. Figure 10a , Figure 14 The cross-sectional view shows that the additional build-up layer 270 includes an additional trace 272 electrically coupled to the filled via 158 of the semiconductor die 150 and the first wiring layer 1122a (as a prefabricated conductive unit 116) of the first conductive portion 110a; an additional dielectric layer 274 for encapsulating the additional trace 272; and an additional through-hole 276 for exposing a portion of the additional trace 272 from the additional dielectric layer 274. Figure 15As shown, additional vias 276 may be filled with any conductive material to form additional filled vias 278 , which are electrically coupled to additional traces 272 . Figure 16 The front side build-up layer 180 is shown formed on the additional build-up layer 270, with the front side traces 184 electrically coupled to the additional filled vias 278; the external connection layer 220 is then formed as described above. Figure 12 , Figure 17 The reconstituted panel 170 with the front side build-up layer 180 , the back side build-up layer 190 and the additional build-up layer 270 is shown first separated from the second carrier 200 and then from the second thermal release tape 210 ; and then singulated into individual semiconductor packages, which are single chip modules (SCMs) having only one semiconductor die 150 .

[0104] Figures 18a to 18c Shown from Figures 14 to 17 1 and 2. Multiple embodiments of semiconductor packages 280a to 280c (single chip modules (SCM)) obtained by variations of the present invention. Figures 18a to 18c Cross-sectional views of semiconductor packages 280 a , 280 b , and 280 c are shown, having similar structures to semiconductor packages 230 b , 230 d , and 230 e , respectively, except that semiconductor packages 280 a , 280 b , and 280 c also have an additional build-up layer 270 sandwiched between reconstruction panel 170 and front-side build-up layer 180 . Figure 18b The internal connection layer 254 in the embodiment may also be used as an underfill as described above to protect the internal connection layer 254 (eg, solder balls).

[0105] The following description also illustrates a variation of the panel-level method S10 for manufacturing a multi-chip module (MCM) having two or more semiconductor dies 150 . Figures 19a to 19c Briefly shows the Figures 2a to 2g A variation of the first embodiment of steps S11 and S12 of the panel-level method S10 is shown. Similarly, Figure 19a It is shown that the molded interconnect substrate (MIS) 100a is first mounted on the first carrier 130 and the first thermal release tape 140, and then the insulating portion 120 is removed from the molded interconnect substrate (MIS) 100a along the dotted line in the figure, thereby obtaining the first conductive portion 110a as a prefabricated conductive unit 116. Figure 19b As shown, two types of prefabricated conductive units 116 can be prepared from the first conductive portion 110a, namely, a first prefabricated conductive unit 1162 and a second prefabricated conductive unit 1164. Accordingly, two types of gaps 118 can be formed between the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164, namely, a first gap 1182 and a second gap 1184, to accommodate two types of semiconductor dies 150, namely, a first semiconductor die 150a and a second semiconductor die 150b. Figure 19c A first semiconductor die 150 a and a second semiconductor die 150 b are shown bonded within a first gap 1182 and a second gap 1184 on the first carrier 130 and the first thermal release tape 140 , respectively.

[0106] Figures 20a to 20c Briefly shows Figures 3a to 3f A variation of the second embodiment of steps S11 and S12 of the panel-level method S10 is shown. Similarly, Figure 20a The first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 are shown bonded to their predetermined positions on the first carrier 130 and the first thermal release tape 140, respectively, separated by a first gap 1182 and a second gap 1184. Figure 20b It is shown that the first semiconductor die 150 a and the second semiconductor die 150 b are bonded to the first carrier 130 at predetermined positions within the first gap 1182 and the second gap 1184 , respectively. Figure 20c Step S11 and step S12 are completed, wherein the first semiconductor die 150 a is located in the first gap 1182 between the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164 , and the second semiconductor die 150 b is located in the second gap 1184 between the second prefabricated conductive unit 1164 and the first prefabricated conductive unit 1162 .

[0107] Figures 21a to 21c Shown Figures 4a to 4d The third embodiment of the panel level method S10 shown in FIG. 1 is a variation of steps S11 and S12. Figure 21a The first semiconductor die 150 a and the second semiconductor die 150 b are shown bonded to their predetermined positions on the first carrier 130 . Figure 21b It is shown that the first prefabricated conductive element 1162 and the second prefabricated conductive element 1164 are subsequently also bonded to their predetermined positions on the first carrier 130 . Figure 21c It shows that after completing steps S11 and S12, the Figure 20c The same packaging structure.

[0108] Figure 22a and Figure 22b Step S13 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 5a , forming a molding layer 160 for encapsulating the first prefabricated conductive unit 1162 , the second prefabricated conductive unit 1164 , the first semiconductor die 150 a and the second semiconductor die 150 b to form a reconstruction panel 170 . Figure 22a The cross-sectional view of FIG. 1 shows that the pre-via 156 is not filled before bonding. Figure 22bThe cross-sectional view of FIG. 1 shows that the pre-via 156 is filled to form a filled via 158 before bonding.

[0109] Figure 23 Step S14 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 6 After the mold layer 160 passes through the grinding device 164, the top 162 is left; then a backside through hole 192 is formed in the top 162, thereby exposing the second wiring layer 1124a of the first prefabricated conductive unit 1162 and the second prefabricated conductive unit 1164.

[0110] Figure 24 Step S15 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 7c Similarly, backside vias 192 are filled with a conductive material to form backside filled vias 194 ; a backside dielectric layer 196 and backside traces 198 are then formed to form backside build-up layer 190 .

[0111] Figure 25 and Figure 26 Step S16 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 8 and Figure 9 The reconstructed panel 170 with the rear-side building layer 190 is separated from the first carrier 130 and the first thermal release tape 140 at an elevated temperature, and then mounted on the second carrier 200 and the second thermal release tape 210 in a flip-chip manner, with the rear-side dielectric layer 196 of the rear-side building layer 190 in contact with the second carrier 200 and the second thermal release tape 210.

[0112] Figure 27a and Figure 27b Step S17 of the panel level method S10 for a multi-chip module (MCM) is shown. Figure 10a , Figure 27a As shown, the pre-vias 156 of the first semiconductor die 150a and the second semiconductor die 150b are filled with a conductive material to form filled vias 158. If the pre-vias 156 have been filled to form filled vias 158 before bonding the first semiconductor die 150a and the second semiconductor die 150b to the first carrier 130 and the first thermal release tape 140, the pre-via 156 can be skipped. Figure 27a . Similar to Figure 10b , Figure 27b The front side building layer 180 is shown (not shown). Figure 10b The stud cavity 188 in is formed as described above.

[0113] Figure 28 Steps S18 and S19 of the panel level method S10 for a multi-chip module (MCM) are shown. Figure 11Similarly, an external connection layer 220 (eg, solder balls) is formed on the front side building layer 180; then similarly Figure 12 , the reconstructed panel 170 having the front-side building layer 180 and the back-side building layer 190 is separated from the second carrier 200 and the second thermal release tape 210; and then divided into individual semiconductor packages (multi-chip modules (MCMs)) having the first semiconductor die 150a and the second semiconductor die 150b.

[0114] Figures 29a to 29e Several embodiments of semiconductor packages (MCMs) 290 a to 290 e obtained from the panel level method S10 are shown. Figure 29a Shown as Figure 28 The resulting first semiconductor package (MCM) 290 a is singulated and includes the reconstructed panel 170 having the front-side build-up layer 180 and the back-side build-up layer 190 . Figure 29b A second semiconductor package (MCM) 290 b is shown, wherein passive components 240 and a top semiconductor package 250 are mounted on the front-side build-up layer 180 and electrically coupled to rear-side studs 199 of the rear-side build-up layer 190 . Additionally, an antenna 292 may also be mounted on the rear-side studs 199 of the rear-side build-up layer 190 . Figure 29c A third semiconductor package (MCM) 290 c is shown in which a heat spreader 260 is mounted to and in direct contact with the back side 1504 of the semiconductor die 150 to enhance heat dissipation. Figure 29d A fourth semiconductor package (MCM) 290d is shown, wherein the top semiconductor package 250 is mounted to the backside build-up layer 190 to form a package-on-package (PoP) configuration. Additionally, the package dielectric layer 252 may also serve as an underfill as described above. Figure 29e A fifth semiconductor package (MCM) 290 e is shown whose reconstruction panel 170 has a front-side build-up layer 180 but no back-side build-up layer 190 .

[0115] Similar to Figures 14 to 17 , Figures 30 to 33 A variation of panel-level method S10 for a multi-chip module (MCM) is shown, further including an additional build-up layer 270 . Figure 30 The cross-sectional view shows that the additional build-up layer 270 includes an additional trace 272 electrically coupled to the first wiring layer 1122a of the first conductive portion 110a; an additional dielectric layer 274 for encapsulating the additional trace 272; and an additional through-hole 276 for exposing a portion of the additional trace 272 from the additional dielectric layer 274. Figure 31 Additional vias 276 are shown filled with a conductive material to form additional filled vias 278 that are electrically coupled to additional traces 272 . Figure 32Front side build-up layer 180 is shown formed on additional build-up layer 270 , with front side traces 184 electrically coupled to additional filled vias 278 ; external connection layer 220 (eg, solder balls) is then formed, electrically coupled to front side studs 186 of front side build-up layer 180 . Figure 33 As shown, the reconstructed panel 170 having the front-side building layer 180, the back-side building layer 190 and the additional building layer 270 is first separated from the second carrier 200 and the second thermal release tape 210; and then divided along the saw line into individual semiconductor packages (multi-chip modules (MCMs)) having the first semiconductor die 150a and the second semiconductor die 150b.

[0116] Figures 34a to 34c Shown from Figures 30 to 33 1 and 2. Multiple embodiments of semiconductor packages (MCM) 300a to 300c are obtained by modifying the above-described embodiment. Figure 34a Shown from Figure 33 A cross-sectional view of the resulting first semiconductor package (MCM) 300 a . In the backside build-up layer 190 , backside traces 198 are encapsulated in the backside dielectric layer 196 . Figure 34b A cross-sectional view of a second semiconductor package (MCM) 300 b is shown, wherein the passive components 240 , the top semiconductor package 250 , and the antenna 292 are mounted on the backside studs 199 of the backside build-up layer 190 . Figure 34c A cross-sectional view of a third semiconductor package (MCM) 300c is shown, forming a package-on-package (PoP) configuration by mounting a top semiconductor package 250 to a backside build-up layer 190. As described above, the package dielectric layer 252 may also serve as an underfill.

[0117] Figure 35 Another variation of the panel-level method S10 for a multi-chip module (MCM) is shown. Figure 19c 、 Figure 20c and Figure 21c As shown, a first semiconductor die 150a and a second semiconductor die 150b are bonded to a first carrier 130. However, here, the first conductive portion 110a (as prefabricated conductive elements 116) only uses one or more first prefabricated conductive elements 1162 to surround the first and second semiconductor dies 150a, 150b, but is not located between them. Because the first and second semiconductor dies 150a, 150b are adjacent to each other, communication between them is faster. The subsequent processes of this variation are the same as those described above and are omitted here.

[0118] Figures 36a to 36c Shown as Figure 35 The illustrated variations provide various embodiments of semiconductor packages (MCMs) 310 a to 310 c . Figure 36a A cross-sectional view of a first semiconductor package (MCM) 310 a is shown. Similar to the first semiconductor package (MCM) 300 a, here the backside traces 198 of the backside build-up layer 190 are encapsulated in the backside dielectric layer 196 . Figure 36b A cross-sectional view of the second semiconductor package (MCM) 310 b is shown. Similar to the second semiconductor package (MCM) 300 b, the passive components 240 , the top semiconductor package 250 , and the antenna 292 are mounted on the backside studs 199 of the backside build-up layer 190 . Figure 36c A cross-sectional view of a third semiconductor package (MCM) 310c is shown. Similar to the third semiconductor package (MCM) 300c, a package-on-package (PoP) configuration is formed by mounting a top semiconductor package 250 onto a backside build-up layer 190. As described above, the package dielectric layer 252 may also serve as an underfill.

[0119] Figures 37a to 37d Several embodiments of semiconductor packages (MCMs) 320 a to 320 d obtained from the panel level method S10 are shown. Figure 37a The semiconductor package (eg Figure 29a FIG2 is a cross-sectional view of a first semiconductor package 320a similar to semiconductor package 290a in FIG2 . However, semiconductor package 320a utilizes second conductive portion 110b as prefabricated conductive element 116, rather than first conductive portion 110a in semiconductor package 290a. Therefore, via front surface 1122b and via rear surface 1124b of second conductive portion 110b are electrically coupled to rear trace 198 of rear build-up layer 190 and front trace 184 of front build-up layer 180, respectively.

[0120] Figure 37b A cross-sectional view of a second semiconductor package 320b is shown. Second semiconductor package 320b also includes an additional build-up layer 270 positioned between reconstruction panel 170 and front-side build-up layer 180. In addition to second conductive portion 110b, semiconductor package 320b also includes one or more copper pillars 322 positioned between first semiconductor die 150a and second semiconductor die 150b for electrical coupling. It should be understood that other structures similar to copper pillars 322 are also within the scope of this application. Figure 37c A cross-sectional view of a third semiconductor package 320 c is shown, wherein backside studs 199 , passive components 240 , and a top semiconductor package 250 are mounted on the backside build-up layer 190 and electrically coupled to the backside studs 199 of the backside build-up layer 190 . Figure 37dA cross-sectional view of a fourth semiconductor package 320d is shown, wherein the top semiconductor package 250 is mounted on the backside build-up layer 190 to form a package-on-package (PoP) configuration. As described above, the package dielectric layer 252 may also serve as an underfill.

[0121] For all of the above-mentioned semiconductor packages (MCMs) manufactured by the panel-level method S10, including semiconductor packages 290a to 290e, 300a to 300c, 310a to 310c and 320a to 320d, the first semiconductor die 150a and the second semiconductor die 150b, and the prefabricated conductive unit 116 (in the form of the first conductive part 110a or the second conductive part 110b) are encapsulated in a parallel manner in the mold layer 160 and become part of the reconstructed panel 170.

[0122] Figure 38 FIG. 1 is a flow chart of another panel-level method S20 for manufacturing a semiconductor package (MCM) according to an exemplary embodiment of the present disclosure. The panel-level method S20 includes steps S21 to S29. Accordingly, Figures 39a to 39i A cross-sectional view of the panel-level method S20 is shown.

[0123] Figure 39a The first step S21 of the panel-level method S20 is shown, which is bonding the semiconductor die 150 to the first carrier 130 and possibly the first thermal release tape 140. Only the first semiconductor die 150a and the second semiconductor die 150b are shown here, but it should be understood that more semiconductor dies 150 may be bonded to the first carrier 130. Figure 39b A second step S22 of the panel-level method S20 is shown, ie, forming a reconstructed panel 170 by forming a mold layer 160 for encapsulating the first semiconductor die 150 a and the second semiconductor die 150 b . Figure 39c The third step S23 of the panel level method S20 is shown, which is to thin the mold layer 160 with a grinding device 164 but leave the top 162 , so that the top 162 still encapsulates the backside 1504 of the first semiconductor die 150 a and the second semiconductor die 150 b .

[0124] Figure 39d The first sub-step S242 of the fourth step S24 of the panel-level method S20 is shown, namely separating the reconstituted panel 170 from the first carrier 130 and the first thermal release tape 140 at an elevated temperature. Figure 39eThe second sub-step S244 of the fourth step S24 is shown, which involves flipping the reconstructed panel 170 over onto the second carrier 200, or possibly onto the second thermal release tape 210. As a result, the contact pads 152 are exposed from the pre-vias 156 of the first semiconductor die 150a and the second semiconductor die 150b. In this manner, the reconstructed panel 170 is transferred from the first carrier 130 to the second carrier 200. Figure 39f A fifth step 25 of the panel-level method S20 is shown, namely forming a front-side build-up layer 180 on the reconstituted panel 170 ; and the contact pads 152 are electrically coupled to the front-side traces 184 and the front-side studs 186 of the front-side build-up layer 180 . Figure 39g The sixth step S26 of the panel-level method S20 is shown, which is to install a prefabricated conductive unit 116 (for example, in the form of a first conductive portion 110a) on the front side building layer 180, wherein the internal connection layer 254 is electrically coupled to the front side stud 186 of the front side building layer 180. As described above, the first conductive portion 110a is made by removing the insulating portion 120 from the molded interconnect substrate (MIS) 100a. Alternatively, as described above, the prefabricated conductive unit 116 can also be a second conductive portion 110b made by removing the insulating portion 120 from the molded through-hole substrate (MVS). Of course, other forms of prefabricated conductive units 116 are also within the scope of the present application. Instead of solder balls, the external connection layer 220 can also include a back surface texture (surface finish) for providing a flat surface for input / output (I / O). The back surface texture can be made of a single layer of metal such as tin or a single layer of a metal composite such as nickel / gold. Alternatively, the back surface texture can also be made of multiple layers. In some embodiments, the back surface texture is made of Electroless Nickel Immersion Gold (ENIG), which has two layers of metal surface coating, wherein the first nickel layer can be formed using an electroless plating chemical reaction; then a very thin layer of gold is plated on the nickel layer. In other embodiments, the back surface texture can be made of Electroless Nickel Electroless Palladium Immersion Gold (ENEPIG), which is formed by depositing electroless nickel, followed by depositing electroless palladium, and finally immersion gold flash. The back surface texture is compatible with I / O chemistry to improve the stability of the connection. The thickness of the back surface texture can be in the range of 1 micron (μm) to 10 microns (μm), preferably, in the range of 1 micron (μm) to 5 microns (μm), or more preferably, in the range of 1 micron (μm) to 3 microns (μm).

[0125] Figure 39hThe seventh step S27 of panel-level method S20 is shown, namely, forming an interposer 330, which includes an interposer-filled via 334 electrically coupled to the first wiring layer 1122a of the first conductive portion 110a; an interposer trace 336 electrically coupled to the interposer-filled via 334; and an interposer dielectric layer 332 for encapsulating the internal connection layer 254, the first conductive portion 110a (including the first wiring layer 1122a), the interposer-filled via 334, and the interposer trace 336. However, a first interposer trace surface 3362 of the interposer trace 336 is exposed from the interposer dielectric layer 332. Furthermore, similar to the encapsulation dielectric layer 252, the interposer dielectric layer 332 can also serve as an underfill to protect the internal connection layer 254. Optionally, the filler size of the interposer dielectric layer 332 is less than 20 micrometers (μm); preferably, the filler size is 10 to 20 micrometers (μm). Figure 39i The eighth step S28 of the panel-level method S20 is shown, which is to form an external connection layer 220 (such as solder balls shown here) electrically coupled to the interposer traces 336. The ninth step S29 of the panel-level method S20 is to separate the reconstructed panel 170 with the front-side build-up layer 180 and the interposer 330 from the second carrier 200 and the second thermal release tape 210 at an elevated temperature, and to singulate the reconstructed panel 170 with the front-side build-up layer 180 and the interposer 330 into individual semiconductor packages (MCMs).

[0126] Figure 40a and Figure 40b Shown from Figures 39a to 39i Two examples of semiconductor packages (MCMs) were obtained. Figure 40a The cross-sectional view of FIG shows a first semiconductor package (MCM) 340 a mounted on an external device 350 (e.g., a PCB). The first semiconductor die 150 a and the second semiconductor die 150 b are electrically connected through the front-side build-up layer 180, the internal connection layer 254, the prefabricated conductive unit 116 (e.g., in the form of the first conductive portion 110 a), the interposer 330's interposer-filled vias 334 and interposer traces 336, and the external connection layer 220, ultimately reaching the external device 350. Figure 40a Also shown are a first prefabricated conductive unit part 1161 of the prefabricated conductive unit 116 for electrically coupling the first semiconductor die 150a to the external device 350, a second prefabricated conductive unit part 1162 of the prefabricated conductive unit 116 for electrically coupling the second semiconductor die 150b to the external device 350, and a third prefabricated conductive unit part 1163 of the prefabricated conductive unit 116 for internal electrical coupling between the first semiconductor die 150a and the second semiconductor die 150b, which can also be further led to the external device 350. Figure 40bA cross-sectional view of a second semiconductor package (MCM) 340b is shown, similar to semiconductor package 340a. However, semiconductor package 340b only includes a third prefabricated conductive element 116 1163, which is used for internal electrical coupling between first semiconductor die 150a and second semiconductor die 150b and further leads to external device 350. Although not shown here, it should be understood that prefabricated conductive element 116 can also take the form of second conductive portion 110b. Other forms of prefabricated conductive element 116 are also within the scope of this application.

[0127] For all semiconductor packages (MCMs) formed using panel-level method S20 as described above, including semiconductor packages 340a and 340b, the first and second semiconductor dies 150a and 150b and the prefabricated conductive element 116 (e.g., in the form of first conductive portion 110a or second conductive portion 110b) are arranged vertically. Thus, the first and second semiconductor dies 150a and 150b are encapsulated within the mold layer 160 and become part of the reconstructed panel 170, while the prefabricated conductive element 116 is encapsulated within the additional dielectric layer 274 and becomes part of the additional build-up layer 270.

[0128] The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics of the present disclosure. The foregoing embodiments are therefore to be considered in all respects as illustrative and not limiting of the present disclosure. The scope of the present disclosure is therefore indicated by the appended claims rather than the foregoing description, and all variations that come within the meaning and scope of the claims are intended to be included in the present disclosure. In this application, unless otherwise indicated, the terms "comprises," "comprising," and their grammatical variations are intended to mean "open" or "comprising" language such that they include the listed elements, but also allow for the inclusion of additional, non-explicitly recited elements.

Claims

1. A semiconductor package having at least one prefabricated conductive unit, characterized in that: include: at least one semiconductor die; a molding layer for encapsulating the at least one semiconductor die; at least one prefabricated conductive unit, wherein the at least one prefabricated conductive unit is prepared from a molded conductive substrate; a front-side build-up layer electrically coupled to the at least one semiconductor die and the at least one prefabricated conductive element; and An external connection layer is electrically coupled to the front-side build-up layer.

2. The semiconductor package according to claim 1, wherein Also includes: A rear-side building layer is located on the prefabricated conductive unit and is opposite to the front-side building layer.

3. The semiconductor package according to claim 1, wherein The at least one prefabricated conductive unit includes a plurality of interconnect wiring layers, and a first wiring layer of the plurality of interconnect wiring layers is configured to be electrically coupled to the front-side build-up layer.

4. The semiconductor package according to claim 1, wherein The at least one prefabricated conductive unit includes at least one conductive via, and a via front surface of the at least one conductive via is configured to be electrically coupled to the front-side build-up layer.

5. The semiconductor package according to claim 1, wherein Also includes: An additional build-up layer is located between the at least one semiconductor die and the front-side build-up layer. The semiconductor package according to claim 1 , wherein: The at least one semiconductor die includes a first semiconductor die and a second semiconductor die, both of which are electrically coupled through the at least one prefabricated conductive unit.

7. The semiconductor package according to claim 6, wherein The at least one prefabricated conductive unit is packaged in the molding layer in a parallel manner with the first semiconductor die and the second semiconductor die.

8. The semiconductor package according to claim 6, wherein The at least one prefabricated conductive unit is vertically packaged with the first semiconductor die and the second semiconductor die in a dielectric layer.

9. The semiconductor package according to claim 3, wherein The at least one prefabricated conductive unit includes an insulating component, and the first wiring layer is exposed from the insulating component.

10. The semiconductor package according to claim 4, wherein The at least one conductive through-hole of the prefabricated conductive unit is formed by filling any conductive material into a hollow through-hole in the insulating component of the prefabricated conductive unit.

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