SGMII interface optical module and switch

Abstract

The utility model discloses an SGMII interface optical module and a switch. The SGMII interface optical module comprises a PHY chip, a single-chip microcomputer, an SFP golden finger, an optical chip, a TOSA module and an ROSA module. The single-chip microcomputer is provided with an MDIO interface and is electrically connected with the PHY chip through the MDIO interface, the PHY chip is provided with a first SGMII interface and a second SGMII interface, the SFP golden finger is electrically connected with the first SGMII interface, and the optical chip is electrically connected with the second SGMII interface, the TOSA module and the ROSA module at the same time; the first communication interface of the optical chip is electrically connected with the second communication interface of the SFP golden finger. According to the technical scheme, the PHY chip is subjected to initial configuration and double SGMII interfaces by using the single chip microcomputer, one SGMII interface is connected with the SFP golden finger, and the other SGMII interface is connected with the optical chip, so that the whole link can realize 10 / 100 / 1000M rate self-adaption.

Description

Technical Field

[0001] The utility model relates to the technical field of photoelectric transmission, in particular to an SGMII interface optical module and a switch. Background Art

[0002] For most network devices in the related art, the optical interfaces of some switches are configured in SGMII (Serial Gigabit Media Independent Interface) mode, which supports 10 / 100 / 1000M rate adaptation, thus providing flexible interface configuration for network devices with different speed requirements. However, the common gigabit optical modules currently on the market only support 1000M transmission speed and cannot achieve 10 / 100 / 1000M rate adaptation, that is, there is a lack of rate compatibility. Utility Model Content

[0003] The main purpose of the present invention is to provide an SGMII interface optical module and a switch, so as to at least solve the technical problem of low switch rate compatibility mentioned in the related art.

[0004] To achieve the above objectives, the present invention provides the following technical solutions:

[0005] In a first aspect of the present invention, an SGMII interface optical module is provided. The SGMII interface optical module includes a PHY chip, a single-chip microcomputer, an SFP gold finger, an optical chip, a TOSA module, and a ROSA module. The single-chip microcomputer is configured with an MDIO interface and is electrically connected to the PHY chip through the MDIO interface. The PHY chip is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger is electrically connected to the first SGMII interface. The optical chip is electrically connected to the second SGMII interface, the TOSA module, and the ROSA module at the same time. The optical chip is configured with a first communication interface, the SFP gold finger is configured with a second communication interface, and the first communication interface is electrically connected to the second communication interface.

[0006] Based on the first aspect, when the SGMII interface optical module is in the first working state, the SFP gold finger is used to receive a first electrical signal from an external host device and transmit it to the PHY chip. The PHY chip is used to process the first electrical signal according to the SGMII interface protocol through the first SGMII interface and output a second electrical signal in a preset format. The optical chip is used to transmit the second electrical signal to the TOSA module. The TOSA module is used to perform photoelectric conversion on the second electrical signal to output a first optical signal, which is then transmitted through an external optical fiber.

[0007] Based on the first aspect, when the SGMII interface optical module is in the second working state, the ROSA module is used to receive a second optical signal from the external optical fiber and perform optoelectronic conversion to output a third electrical signal. The optical chip is used to output the third electrical signal to the PHY chip. The PHY chip is used to process the received third electrical signal according to the SGMII interface protocol through the second SGMII interface and output a fourth electrical signal in a preset format. The SFP gold finger is used to receive the fourth electrical signal and transmit it to an external host device.

[0008] Based on the first aspect, the Ethernet rate at which the PHY chip outputs the second electrical signal and the Ethernet rate at which the PHY chip outputs the fourth electrical signal both support 10 Mbps, 100 Mbps, and 1000 Mbps.

[0009] A second aspect of the present invention provides a switch, comprising a switch body and the SGMII interface optical module according to the first aspect; the SGMII interface optical module is built into the switch body.

[0010] The present invention provides an SGMII interface optical module and switch, comprising a PHY chip, a single-chip microcontroller, an SFP gold finger, an optical chip, a TOSA module, and a ROSA module. The single-chip microcontroller is configured with an MDIO interface and electrically connected to the PHY chip via the MDIO interface. The PHY chip is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger is electrically connected to the first SGMII interface. The optical chip is also electrically connected to the second SGMII interface, the TOSA module, and the ROSA module. The optical chip is configured with a first communication interface, the SFP gold finger is configured with a second communication interface, and the first communication interface is electrically connected to the second communication interface. Specifically, the present technical solution utilizes the single-chip microcontroller to initialize and configure the PHY chip and dual SGMII interfaces, one SGMII interface connected to the SFP gold finger and the other connected to the optical chip. This allows the entire link to achieve 10 / 100 / 1000M rate adaptation, avoiding issues such as insufficient rate compatibility. Furthermore, by combining the SGMII interface configured by the PHY chip with the optical chip, the SGMII interface optical module achieves significant advantages in transmission distance, potentially reaching tens or even hundreds of kilometers. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 This is a schematic diagram of the internal structure of the SGMII interface optical module of the utility model;

[0012] Figure 2 This is a schematic diagram of the application scenario when the SGMII interface optical module of the utility model is applied to a switch;

[0013] Description of reference numerals: PHY chip 10 , single-chip microcomputer 20 , SFP gold finger 30 , optical chip 40 , TOSA module 50 , ROSA module 60 , switch 100 , host 200 , remote network device 300 . DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0015] It should be noted that relative terms such as "first," "second," etc. may be used to describe various components, but these terms do not limit the components. These terms are only used to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and a second component may similarly be referred to as a first component. The term "and / or" refers to any one or more combinations of the related items and the described items.

[0016] See also Figure 1 and Figure 2 This embodiment provides an SGMII interface optical module, which is used in a switch and includes at least a PHY chip 10, a single-chip microcomputer 20, an SFP gold finger 30, an optical chip 40, a TOSA module 50 and a ROSA module 60.

[0017] In the SGMII interface optical module, the connection relationship between each component is as follows:

[0018] The single-chip microcomputer 20 is configured with an MDIO interface and is electrically connected to the PHY chip 10 through the MDIO interface. The PHY chip 10 is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger 30 is electrically connected to the first SGMII interface. The optical chip 40 is also electrically connected to the second SGMII interface, the TOSA module 50, and the ROSA module 60.

[0019] Regarding the first SGMII interface and the second SGMII interface, it should be noted that: SGMII (Serial Gigabit Media Independent Interface) is a high-speed serial interface standard, commonly used in Ethernet communications. SGMII is an improved MII (Media Independent Interface) that achieves higher speeds and simpler pin designs through serialized data transmission. SGMII uses a differential signal transmission method, similar to LVDS (low voltage differential signaling), so it has the advantages of strong anti-interference ability and high transmission rate. Normally, the typical range of SGMII signal levels is between a few hundred millivolts and one volt. By reducing the number of pins and simplifying wiring, SGMII improves the speed and reliability of data transmission, and has become a widely used interface in Ethernet devices with speeds of 1Gbps and above.

[0020] Regarding the PHY (Physical Layer) chip 10, it should be noted that the PHY chip is a crucial component of network communication systems, primarily responsible for implementing the physical transmission functions of the data link at the physical layer. The core function of the PHY chip is to handle signal conversion between devices and communication media and the implementation of physical layer protocols. The PHY chip includes the following main functions and features: 1. Signal conversion (conversion between electrical and physical signals): The core function of the PHY chip is to convert between digital and analog signals. Data in communication systems is generally transmitted in the form of digital signals, while data transmitted over physical media (such as optical fiber or copper wire) may be in the form of electrical or optical signals. The PHY chip is responsible for: At the transmitter: converting digital signals into physical signals (such as analog signals) suitable for transmission over the transmission medium. At the receiver: converting received physical signals (such as analog or optical signals) into digital signals that can be processed in the digital system. For example, in Ethernet communication, the PHY chip can convert parallel digital data in devices (such as switches, routers, or computers) into serial electrical signals for transmission via twisted pair cables or optical fibers. 2. Rate Adaptation and Auto-Negotiation: PHY chips typically support multiple transmission rates and can automatically adapt to the network environment. For example, common Ethernet PHY chips can support rates of 10Mbps, 100Mbps, 1Gbps, and even 10Gbps. The PHY chip's auto-negotiation function detects and negotiates the highest rate supported by both parties during connection establishment, ensuring efficient and stable data transmission.

[0021] In addition, the optical chip 40 is configured with a first communication interface, and the SFP gold finger 30 is configured with a second communication interface, and the first communication interface and the second communication interface are electrically connected. Generally, the first communication interface includes an IIC interface, and the second communication interface includes an IIC interface, that is, the optical chip 40 and the SFP gold finger 30 implement data communication via the I2C bus protocol.

[0022] The following describes the functions of each component when the SGMII interface optical module is in different working states:

[0023] When the SGMII interface optical module is in the first working state (signal transmission direction: SFP gold finger-PHY chip-optical chip-TOSA module), the SFP gold finger 30 is used to receive a first electrical signal from an external host device and transmit it to the PHY chip 10. The PHY chip 10 is used to process the first electrical signal through the first SGMII interface using the SGMII interface protocol and output a second electrical signal in a preset Ethernet frame format. The optical chip 40 is used to transmit the second electrical signal to the TOSA module 50. The TOSA module 50 is used to perform photoelectric conversion on the second electrical signal to output a first optical signal, which is then transmitted through an external optical fiber.

[0024] When the SGMII interface optical module is in the second working state (receiving signal direction: ROSA module-optical chip-PHY chip-SFP gold finger), the ROSA module 60 is used to receive the second optical signal of the external optical fiber and perform photoelectric conversion to output a third electrical signal. The optical chip 40 is used to output the third electrical signal to the PHY chip 10. The PHY chip 10 is used to process the received third electrical signal according to the SGMII interface protocol through the second SGMII interface and output a fourth electrical signal in a preset Ethernet frame format. The SFP gold finger 30 is used to receive the fourth electrical signal and transmit it to the external host device.

[0025] In summary, the SGMII interface optical module and switch of the present invention include a PHY chip, a single-chip microcontroller, an SFP gold finger, an optical chip, a TOSA module, and a ROSA module. The single-chip microcontroller is configured with an MDIO interface and electrically connected to the PHY chip via the MDIO interface. The PHY chip is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger is electrically connected to the first SGMII interface. The optical chip is also electrically connected to the second SGMII interface, the TOSA module, and the ROSA module. The optical chip is configured with a first communication interface, the SFP gold finger is configured with a second communication interface, and the first communication interface is electrically connected to the second communication interface. Specifically, this technical solution utilizes the single-chip microcontroller to initialize and configure the PHY chip and dual SGMII interfaces: one SGMII interface connects to the SFP gold finger, and the other connects to the optical chip, enabling the entire link to achieve 10 / 100 / 1000M rate adaptation. Furthermore, the SGMII interface configured by the PHY chip, combined with the optical chip, significantly improves the transmission distance of the SGMII interface optical module, potentially reaching tens or even hundreds of kilometers.

[0026] In some optional implementations of this embodiment, the microcontroller 20 transmits control signals to the PHY chip 10 via the MDIO interface. These control signals are used to initialize, configure, and monitor the operation of the PHY chip 10. Specifically, the microcontroller can communicate with the PHY chip via the MDIO (Management Data Input / Output) interface to initialize and configure it. The MDIO interface is a commonly used communication interface in Ethernet device management and is used for data exchange and communication between a controller such as the microcontroller 20 and the PHY chip 10. Specifically, the following is the MDIO interface communication process, including initialization, register reading and writing, status checking, and configuration.

[0027] The initialization process includes configuring the MDC and MDIO pins, setting the communication frequency, initializing related peripherals, etc. Specifically: Configure the MDC and MDIO pins: In the microcontroller, configure MDC as an output pin and MDIO as a bidirectional pin. Ensure that the microcontroller can provide a clock signal through MDC and transmit data through MDIO. Set the communication frequency: The clock frequency of MDIO (MDC) cannot exceed 2.5MHz and is usually set to 2MHz or lower. Initialize the frequency of MDC according to the clock configuration of the microcontroller. Initialize related peripherals: According to the hardware design of the microcontroller, initialize peripherals related to the MDIO interface, such as GPIO or dedicated MDIO interface module.

[0028] In the register read / write process, a PHY reset involves writing to the reset register and waiting for the reset to complete. Specifically: Writing to the reset register: In some cases, the MCU needs to reset the PHY chip before formal configuration. Typically, the reset operation is performed by writing to the PHY control register. Waiting for reset completion: After the reset, wait for a period of time (usually tens of milliseconds) to ensure that the PHY chip has completed the reset operation.

[0029] PHY register read and write operations include generating the MDIO frame format, MDIO write operations, and MDIO read operations. Specifically, generating the MDIO frame format consists of 32 bits of data, consisting of a pre-sync, start, opcode, PHY address, register address, transition, data field, and spare bits. The specific format is as follows: pre-sync: 32 '1's (for write operations only), start: 2 bits ('01'), opcode: 2 bits ('10' for write operations, '11' for read operations), PHY address: 5 bits (for selecting the PHY chip to communicate with), register address: 5 bits (for selecting the register to access), transition: 2 bits ('10' for write operations, 'Z0' for read operations), and data field: 16 bits (for data transmission). MDIO write operations initiate frame generation: The microcontroller, using the MDC clock, sequentially sends the above fields to the PHY chip via the MDIO line. Sending data: During a write operation, the microcontroller writes 16 bits of data to the designated register of the PHY chip via the MDIO line. Clock synchronization: During data transmission, the MDC is used to synchronize the MDIO data signal. MDIO read operation: Start frame generation: Similar to a write operation, the MCU generates the start, opcode, PHY address, and register address. Read data: In a read operation, the MCU first sends a high-impedance signal and then reads the 16-bit data returned by the PHY chip through the MDIO pin.

[0030] The process of configuring the PHY chip includes setting the working mode, configuring auto-negotiation, configuring other functions, etc. Specifically: Setting the working mode: According to the system requirements, the PHY chip is configured to a specific working mode (such as 10Mbps, 100Mbps, 1000Mbps, full-duplex or half-duplex, etc.) through the MDIO interface. Configure auto-negotiation: Write to a specific control register to enable or disable the auto-negotiation function. Generally, auto-negotiation allows the PHY chip and the peer device to automatically negotiate the optimal transmission rate and working mode. Configure other functions: According to application requirements, the power mode, fault detection function, etc. of the PHY chip can also be configured through the MDIO interface.

[0031] In summary, the MCU 20 can complete the initialization, configuration, and operation monitoring of the PHY chip 10 via the MDIO interface, enabling the entire link to achieve 10 / 100 / 1000 Mbps rate adaptation. That is, the Ethernet rate of the second electrical signal output by the PHY chip and the Ethernet rate of the fourth electrical signal output by the PHY chip both support 10 Mbps, 100 Mbps, and 1000 Mbps.

[0032] It should be further explained that the microcontroller can complete the initialization, configuration and operation monitoring operations of the PHY chip by transmitting control signals based on the MDIO interface. In this embodiment, the main protection scope is the electrical connection between the microcontroller and the PHY chip based on the MDIO interface, and the specific operating steps involved are only conventional means well known to those skilled in the art.

[0033] In some optional implementations of this embodiment, the SFP gold finger 30 is configured with a first transmit port TX+, a second transmit port TX-, a first receive port RX+, and a second receive port RX-; the first transmit port TX+, the second transmit port TX-, the first receive port RX+, and the second receive port RX- are all electrically connected to the first SGMII interface of the PHY chip 10. This configuration is intended to enable high-speed serial data transmission between the PHY chip 10 and the SFP gold finger 30 via the SGMII interface, thereby ensuring the stability and integrity of transmitted and received data. This connection method effectively utilizes the high-speed characteristics of the SGMII interface, resulting in higher communication speeds and more stable data transmission between the SFP gold finger 30 and the PHY chip 10. By connecting the transmit and receive ports to the transmit and receive channels of the PHY chip, respectively, full-duplex data transmission can be achieved, improving the bandwidth and communication efficiency of the data link.

[0034] In addition, the optical chip 40 is equipped with a third transmit port TX+, a fourth transmit port TX-, a third receive port RX+, and a fourth receive port RX-. These ports are all electrically connected to the second SGMII interface of the PHY chip 10. This configuration enables high-speed serial data transmission between the PHY chip 10 and the optical chip 40 via the SGMII interface, thereby ensuring the stability and integrity of transmitted and received data.

[0035] A second aspect of the present invention provides a switch 100 comprising a switch body and an SGMII interface optical module according to the first aspect; the SGMII interface optical module is internally mounted within the switch body. The switch 100 is electrically connected to a host 200 via an SFP gold finger, and is electrically connected to a remote network device 300 via a TOSA module 50 and a ROSA module 60.

[0036] The present invention's SGMII interface optical module and switch include a PHY chip, a single-chip microcontroller (MCU), an SFP gold finger, an optical chip, a TOSA module, and a ROSA module. The MCU is configured with an MDIO interface and electrically connected to the PHY chip via the MDIO interface. The PHY chip is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger is electrically connected to the first SGMII interface. The optical chip is also electrically connected to the second SGMII interface, the TOSA module, and the ROSA module. The optical chip is configured with a first communication interface, the SFP gold finger is configured with a second communication interface, and the first communication interface is electrically connected to the second communication interface. Specifically, the present technical solution utilizes the MCU to initialize and configure the PHY chip and dual SGMII interfaces: one SGMII interface connects to the SFP gold finger, the other connects to the optical chip, enabling the entire link to achieve 10 / 100 / 1000M rate adaptation. Furthermore, by combining the SGMII interface configured by the PHY chip with the optical chip, the SGMII interface optical module achieves significant advantages in transmission distance, potentially reaching tens or even hundreds of kilometers.

[0037] The above detailed description of the specific embodiments of the utility model is intended to be illustrative only, and the utility model is not limited to the specific embodiments described above. For those skilled in the art, any equivalent modifications or substitutions made to the utility model are also within the scope of the utility model. Therefore, equivalent changes, modifications, and improvements made without departing from the spirit and scope of the principles of the utility model should be included within the scope of the utility model.

Claims

1. An SGMII interface optical module, characterized in that: The SGMII interface optical module includes a PHY chip, a single-chip microcomputer, an SFP gold finger, an optical chip, a TOSA module and a ROSA module; The single-chip microcomputer is configured with an MDIO interface and is electrically connected to the PHY chip through the MDIO interface. The PHY chip is configured with a first SGMII interface and a second SGMII interface. The SFP gold finger is electrically connected to the first SGMII interface. The optical chip is also electrically connected to the second SGMII interface, the TOSA module, and the ROSA module. The optical chip is configured with a first communication interface, the SFP gold finger is configured with a second communication interface, and the first communication interface is electrically connected to the second communication interface.

2. The SGMII interface optical module according to claim 1, wherein: When the SGMII interface optical module is in a first working state, the SFP gold finger is used to receive a first electrical signal from an external host device and transmit the signal to the PHY chip. The PHY chip is used to process the first electrical signal according to the SGMII interface protocol through the first SGMII interface and output a second electrical signal in a preset format. The optical chip is used to transmit the second electrical signal to the TOSA module. The TOSA module is used to perform photoelectric conversion on the second electrical signal to output a first optical signal, which is then transmitted through an external optical fiber.

3. The SGMII interface optical module according to claim 2, characterized in that: When the SGMII interface optical module is in the second working state, the ROSA module is used to receive a second optical signal from the external optical fiber and perform photoelectric conversion to output a third electrical signal. The optical chip is used to output the third electrical signal to the PHY chip. The PHY chip is used to process the received third electrical signal according to the SGMII interface protocol through the second SGMII interface and output a fourth electrical signal in a preset format. The SFP gold finger is used to receive the fourth electrical signal and transmit it to the external host device.

4. The SGMII interface optical module according to claim 3, wherein: The preset format includes an Ethernet frame format.

5. The SGMII interface optical module according to claim 3, characterized in that: The first communication interface includes an IIC interface, and the second communication interface includes an IIC interface.

6. The SGMII interface optical module according to claim 3, characterized in that: The single chip microcomputer transmits a control signal to the PHY chip through the MDIO interface, and the control signal is used to initialize, configure and run monitoring operations on the PHY chip.

7. The SGMII interface optical module according to claim 3, characterized in that: The SFP gold finger is configured with a first transmitting port, a second transmitting port, a first receiving port and a second receiving port; The first transmitting port, the second transmitting port, the first receiving port and the second receiving port are all electrically connected to the first SGMII interface of the PHY chip.

8. The SGMII interface optical module according to claim 7, characterized in that: The optical chip is configured with a third transmitting port, a fourth transmitting port, a third receiving port and a fourth receiving port; The third transmitting port, the fourth transmitting port, the third receiving port and the fourth receiving port are all electrically connected to the second SGMII interface of the PHY chip.

9. The SGMII interface optical module according to claim 3, wherein: The Ethernet rate at which the PHY chip outputs the second electrical signal and the Ethernet rate at which the PHY chip outputs the fourth electrical signal both support 10 Mbps, 100 Mbps, and 1000 Mbps.

10. A switch, characterized in that: The device comprises a switch body and the SGMII interface optical module according to any one of claims 1 to 9; the SGMII interface optical module is built into the switch body.

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