Integrated circuit package

Abstract

The utility model provides an integrated circuit package and a forming method thereof. An integrated circuit package may include a first die, a first gap-fill layer along a plurality of sidewalls of the first die, a first bonding layer on the first die and the first gap-fill layer, and a first die connector in the first bonding layer. The first die connector may be directly over an interface between the first die and the first gap fill layer.

Description

Technical Field

[0001] The embodiments of the present invention relate to integrated circuit packaging. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density is due to the continuous reduction in minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices continues to grow, the demand for smaller and more innovative semiconductor die packaging technologies has also emerged. Utility Model Content

[0003] An embodiment of the present invention provides an integrated circuit package, comprising a first tube core; a first gap filling layer along multiple side walls of the first tube core; a first bonding layer located on the first tube core and the first gap filling layer; and a first tube core connector located in the first bonding layer, wherein the first tube core connector is directly located on the interface between the first tube core and the first gap filling layer.

[0004] An embodiment of the present invention provides an integrated circuit package, comprising a first tube core, wherein the first tube core further comprises a first semiconductor substrate; a first tube core gap filling layer, located on multiple side walls of the first tube core; a first tube core bonding layer, located on the first gap filling layer and the first semiconductor substrate; a first tube core connector, located in the first bonding layer, wherein the first tube core connector is in contact with the interface between the first tube core and the first gap filling layer; and a second tube core, comprising a second tube core bonding layer and a second tube core connector in the second bonding layer, wherein the second tube core bonding layer is bonded to the first bonding layer and the second tube core connector is bonded to the first tube core connector. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The various aspects of the present invention will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0006] Figure 1 、 Figure 2 、 Figure 3A 、 Figure 3B 、 Figure 3C 、 Figure 4A 、 Figure 4B 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 Cross-sectional and top-down views are shown of various intermediate stages in the formation of an integrated circuit package in accordance with some embodiments.

[0007] [Explanation of Symbols]

[0008] 100: Lower integrated circuit die

[0009] 102, 202: Semiconductor substrate

[0010] 104, 204: Internal connection structure

[0011] 105, 205: Sealing ring

[0012] 106: Via hole

[0013] 108, 118, 206, 213, 214: Bonding layer

[0014] 110, 120, 208: Die connectors

[0015] 112, 212: carrier

[0016] 114: Adhesive

[0017] 116: Lower gap filling layer

[0018] 120A, 208A: Active die connectors

[0019] 120B, 120C, 120D, 208B, 208C: Dummy die connectors

[0020] 121: Area

[0021] 200, 200A, 200B: Upper integrated circuit die

[0022] 210: Upper gap filling layer

[0023] 216: Dielectric layer

[0024] 218: Underbump Metallization

[0025] 220: Electrical connector

[0026] 222: Tape

[0027] 224: Framework

[0028] 226: Cutting Road

[0029] 228: Package substrate

[0030] 230: Conductive pad

[0031] 234: Underfill

[0032] 250: Chip structure

[0033] 250': Integrated circuit packaging components

[0034] 300: Integrated Circuit Packaging

[0035] A-A', B-B': Reference cross sections

[0036] D1, D2: distance

[0037] W1: width DETAILED DESCRIPTION

[0038] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the description below may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself specify the relationship between the various embodiments and / or configurations discussed.

[0039] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0040] An integrated circuit package having a plurality of dummy bond pads above an interface between a semiconductor device and an encapsulation body and a method for forming the same are provided. According to some embodiments, one or more lower integrated circuit dies may be encapsulated in a lower gap-filling layer, and a bonding layer may be formed on a top surface of the lower gap-filling layer and the lower integrated circuit die. A plurality of die connectors are disposed in the bonding layer, including one or more dummy die connectors located above the interface between the lower integrated circuit die and the lower gap-filling layer. One or more upper integrated circuit dies are bonded to the bonding layer and the plurality of die connectors, wherein the upper integrated circuit die may be directly located above the interface between the lower integrated circuit die and the lower gap-filling layer. By forming the plurality of dummy die connectors directly above the interface between the plurality of lower integrated circuit dies and the lower gap-filling layer, the effect of a coefficient of thermal expansion (CTE) mismatch between the plurality of lower integrated circuit dies and the lower gap-filling layer on the bonding integrity of the plurality of upper integrated circuit dies to the bonding layer and the plurality of die connectors may be eliminated or reduced, thereby eliminating or reducing the risk of delamination of the plurality of upper integrated circuit dies during manufacture and operation of the integrated circuit package. As a result, better reliability of the integrated circuit package can be achieved.

[0041] Figures 1 to 10 Several intermediate processing steps are shown to form an integrated circuit package. Figure 1 , multiple lower integrated circuit dies 100 are attached to a carrier 112 via an adhesive 114. Carrier 112 can be a semiconductor carrier, a glass carrier, a ceramic carrier, or the like. Carrier 112 can be a wafer. In some embodiments, adhesive 114 is a thermal release layer, such as an epoxy-based light-to-heat-conversion (LTHC) release material, which loses its adhesive properties when heated. In some embodiments, adhesive 114 is a UV adhesive that loses its adhesive properties when exposed to UV light. Figure 1 The illustrated layout of multiple lower integrated circuit dies 100 over carrier 112 is an example, and other layouts are contemplated.

[0042] Each lower integrated circuit die 100 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), an application processor (AP), a microcontroller, etc.); a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.); a power management die (e.g., a power management integrated circuit (PMIC) die); a radio frequency (RF) die; a sensor die; a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof.

[0043] Each lower integrated circuit die 100 can have a semiconductor substrate 102, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 102 can include other semiconductor materials, such as rhodium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP, or combinations thereof. Other substrates can also be used, such as multilayer or gradient substrates. The semiconductor substrate 102 can have an active surface, which can be referred to as a front side (e.g., Figure 1 the surface facing downward) and the inactive surface which may be referred to as the backside (e.g., Figure 1 The backside of the semiconductor substrate 102 may also be referred to as the backside of the lower integrated circuit die 100 , and the frontside of the semiconductor substrate 102 may face the frontside of the lower integrated circuit die 100 .

[0044] A plurality of devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 102. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 104 may be disposed on the active surface of the semiconductor substrate 102. The interconnect structure 104 may interconnect the plurality of devices to form an integrated circuit. The interconnect structure 104 may include a plurality of metallization patterns (not shown separately) in a plurality of dielectric layers (not shown separately). The dielectric layers may be low-k dielectric layers. The metallization patterns may include metal lines and vias, which may be formed in the dielectric layers using a damascene process (such as a single damascene process, a dual damascene process, etc.). The metallization patterns may be formed from a suitable conductive material, such as copper, tungsten, aluminum, silver, gold, combinations thereof, etc. The metallization patterns may be electrically coupled to the devices. A seal ring 105 may extend through the interconnect structure 104 of each lower integrated circuit die 100. In a top view, seal ring 105 may surround the multiple metallization patterns of corresponding interconnect structures 104, and the area between seal ring 105 and the multiple metallization patterns may be referred to as a keep-out zone (KOZ). Seal ring 105 may be made of the same or similar material and formed using the same or similar process as the metallization patterns. Seal ring 105 may be electrically isolated from the device.

[0045] A plurality of vias 106 may be arranged in the semiconductor substrate 102. The plurality of vias 106 may be electrically coupled to the plurality of metallization patterns of the interconnect structure 104. The semiconductor substrate 102 may be thinned in a subsequent process to expose the plurality of vias 106 at the inactive surface of the semiconductor substrate 102. After the thinning process, the vias 106 may be through-substrate vias (TSVs), such as through-silicon vias (TSVs). In some embodiments, the vias 106 are formed using a via-first process, such that the vias 106 extend into the semiconductor substrate 102 but not into the interconnect structure 104. The vias 106 formed using the via-first process may be connected to the lower metallization pattern of the interconnect structure 104 (e.g., closer to the semiconductor substrate 102). In some embodiments, the vias 106 are formed using a via-middle process, such that the vias 106 extend through a portion of the interconnect structure 104 and into the semiconductor substrate 102. The via 106 formed by the via-middle process can be connected to the middle metallization pattern of the interconnect structure 104. In some embodiments, the via 106 is formed by a via-last process, so that the via 106 can extend through the entire interconnect structure 104 and into the semiconductor substrate 102. The via 106 formed by the via-last process can be connected to the upper metallization pattern of the interconnect structure 104 (e.g., farther from the semiconductor substrate 102).

[0046] A bonding layer 108 may be disposed on the interconnect structure 104 at the front side of each lower integrated circuit die 100. The bonding layer 108 may be formed of an oxide (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxides, etc.); a nitride (e.g., silicon nitride); or the like. The bonding layer 108 may be formed via chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. One or more passivation layers (not separately shown) may be disposed between the bonding layer 108 and the interconnect structure 104.

[0047] A plurality of die connectors 110 can extend through the bonding layer 108 and be electrically coupled to the plurality of metallization patterns of the interconnect structure 104. The die connectors 110 can include conductive pillars, conductive pads, and the like that can make external connections. In some embodiments, the die connectors 110 include conductive pads located at the front side of the lower integrated circuit die 100 and vias connecting the conductive pads to the upper metallization patterns of the interconnect structure 104. In such embodiments, the die connectors 110, including the conductive pads and vias, can be formed using a damascene process, such as a single damascene process, a dual damascene process, or the like. The die connectors 110 can be formed from a conductive material, such as copper or aluminum, using a suitable coating process, such as plating.

[0048] exist Figure 2 In the embodiment of the present invention, a lower gapfill layer 116 is formed around the plurality of lower integrated circuit dies 100, and the plurality of semiconductor substrates 102 of the plurality of lower integrated circuit dies 100 are thinned to expose the plurality of vias 106. In a top view, the lower gapfill layer 116 may surround the plurality of lower integrated circuit dies 100. The lower gapfill layer 116 may extend along the sidewalls of the lower integrated circuit dies 100 (e.g., the semiconductor substrate 102, the interconnect structure 104, and the bonding layer 108). The lower gapfill layer 116 may have a different CTE than the components of the lower integrated circuit dies 100 (e.g., the semiconductor substrate 102). The lower gapfill layer 116 may be an insulating layer and may be formed of a dielectric material such as silicon oxide, PSG, BSG, BPSG, TEOS-based oxides, etc., which may be formed by a suitable deposition process (e.g., CVD, ALD, etc.). Initially, the lower gapfill layer 116 may cover the backsides of the plurality of lower integrated circuit dies 100. A first thinning process may be performed to level the surface of the lower gap-fill layer 116 with the backside surfaces of the plurality of lower integrated circuit dies 100. The first thinning process may be a chemical-mechanical polishing (CMP) process, a grinding process, an etch-back process, a combination thereof, or the like.

[0049] The plurality of semiconductor substrates 102 are thinned through a second thinning process to expose the plurality of vias 106. Portions of the lower gapfill layer 116 may also be removed through the second thinning process. The second thinning process may be a CMP process, a grinding process, an etch-back process, or a combination thereof, performed on the backsides of the plurality of lower integrated circuit dies 100. After the second thinning process, the surfaces of the lower gapfill layer 116 and the plurality of lower integrated circuit dies 100 (including the plurality of semiconductor substrates 102 and the plurality of vias 106) are substantially coplanar (within process variations).

[0050] exist Figure 3AIn the embodiment of the present invention, a bonding layer 118 is formed on the backside of the lower gapfill layer 116 and the plurality of lower integrated circuit dies 100, and a plurality of die connectors 120 are formed in the bonding layer 118. The die connectors 120 may also be referred to as bonding pads, which can be used to bond with the plurality of upper integrated circuit dies in subsequent processes. The plurality of die connectors 120 may include a plurality of active die connectors 120A, a plurality of dummy die connectors 120B, a plurality of dummy die connectors 120C, and a plurality of dummy die connectors 120D. The active die connectors 120A may be die connectors 120 electrically coupled to the vias 106 and the circuitry of the lower integrated circuit dies 100. The dummy die connectors 120B, dummy die connectors 120C, and dummy die connectors 120D may be die connectors 120 electrically isolated from the circuitry of the lower integrated circuit dies 100.

[0051] Dummy die connector 120B and dummy die connector 120D may be located directly above lower gapfill layer 116 and semiconductor substrate 102, respectively. As described in more detail below, after bonding with the upper integrated circuit die, dummy die connector 120B may be completely covered by the upper integrated circuit die, and dummy die connector 120D may be partially covered by the upper integrated circuit die. Dummy die connector 120D may be referred to as a landing structure. Dummy die connector 120C may be located directly above the interface between lower integrated circuit die 100 and lower gapfill layer 116. In some embodiments, dummy die connector 120C may be between corresponding active die connector 120A and dummy die connector 120B, where active die connector 120A and dummy die connector 120B are the die connectors 120 closest to dummy die connector 120C on each side. As discussed in more detail below, forming the dummy die connector 120C directly above the interface between the lower integrated circuit die 100 and the lower gap-fill layer 116 can eliminate or reduce the impact of CTE mismatch between underlying materials (e.g., between components of the lower integrated circuit die (e.g., semiconductor substrate 102) and the lower gap-fill layer 116) on the integrity of the bond between the upper integrated circuit die and the bonding layer 118 and the die connector 120.

[0052] The die connection 120 may have a width W1 in the range of about 3 μm to about 4 μm, for example about 3.5 μm. The dummy die connection 120C may be spaced apart from the closest active die connection 120A by a distance D1. The dummy die connection 120C may be spaced apart from the closest dummy die connection 120B by a distance D2. Figure 3AIn the illustrated embodiment, distance D1 is different from distance D2. For example, distance D1 may be in a range of approximately 4 μm to approximately 6 μm, such as approximately 4.82 μm, and distance D2 may be in a range of approximately 1 μm to approximately 2 μm, such as approximately 1.32 μm, wherein distance D1 is greater than distance D2. In other embodiments, distance D1 is equal to distance D2. For example, distance D1 and distance D2 may be in a range of approximately 2 μm to approximately 4 μm, such as approximately 3.07 μm.

[0053] exist Figure 3A In the illustrated embodiment, the die connector 120 extends completely through the bonding layer 118 from the top surface of the bonding layer 118 to the bottom surface of the bonding layer 118. As a result, the active die connector 120A can contact the semiconductor substrate 102 and the via 106, the dummy die connector 120B can contact the lower gap-filling layer 116, and the dummy die connector 120C can contact the semiconductor substrate 102 and the lower gap-filling layer 116 (including the interface between the lower integrated circuit die 100 and the lower gap-filling layer 116). In other embodiments, the die connector 120 can extend partially through the bonding layer 118 from the top surface of the bonding layer 118 to a depth within the bonding layer 118, and the via 106 can protrude from the surface of the semiconductor substrate 102 and extend partially through the bonding layer 118 to contact the active die connector 120A in the bonding layer 118.

[0054] The bonding layer 118 may be formed of an oxide such as silicon oxide, PSG, BSG, BPSG, or TEOS-based oxides, and may be formed by a suitable deposition process such as CVD or ALD. The die connector 120 may be formed by a damascene process, such as a single damascene process or a dual damascene process. The die connector 120 may be formed of a metal such as copper or aluminum, and may be formed by plating. In some embodiments, a planarization process such as CMP, a grinding process, an etch-back process, or a combination thereof is performed on the bonding layer 118 and the die connector 120. After the planarization process, the surfaces of the bonding layer 118 and the die connector 120 may be substantially coplanar (within process variations).

[0055] Figure 3B According to some embodiments Figure 3A A top view of a region 121 of the structure is shown, wherein a plurality of die connectors 120 are arranged in an array. Figure 3A The cross-section shown can be taken along Figure 3B For illustration purposes, the bonding layer 118 is omitted and Figure 3B 1. The portion of the interface between the plurality of lower integrated circuit dies 100 and the lower gap fill layer 116 below the plurality of dummy die connectors 120C is shown in dashed lines. Figure 3B As shown, the plurality of die connectors 120 may form an array including a plurality of columns of active die connectors 120A, a plurality of columns of dummy die connectors 120B, a plurality of columns of dummy die connectors 120C, and a plurality of columns of dummy die connectors 120D. The columns of the plurality of dummy die connectors 120C may be located above the interface between the plurality of lower integrated circuit dies 100 and the lower gap-filling layer 116 and between the plurality of active die connectors 120A and the plurality of columns corresponding to the plurality of dummy die connectors 120B. Each dummy die connector 120C may be divided by the interface between the semiconductor substrate 102 and the lower gap-filling layer 116 into a first portion above the semiconductor substrate 102 and a second portion above the lower gap-filling layer 116. Figure 3B In the embodiment shown, the first portion and the second portion of the dummy die connector 120C have the same width and size. In other embodiments, the first portion and the second portion of the dummy die connector 120C have different widths and sizes. As an example, Figure 3B Each die connector 120 is shown as having a circular shape, and other shapes are contemplated. As an example, Figure 3B One column of the plurality of dummy die connections 120B is shown positioned between two columns of the plurality of dummy die connections 120C, and other numbers of columns of the plurality of dummy die connections 120B may be positioned between two columns of the plurality of dummy die connections 120C.

[0056] Figure 3C According to some embodiments Figure 3A A top view of a region 121 of the structure is shown, wherein a plurality of die connectors 120 are arranged in a staggered array. Figure 3A The cross-section shown can be taken along Figure 3C It is obtained by the reference section BB' in. Figure 3C The top view shown is Figure 3B The top views shown are similar, with like reference numerals referring to like features. Figure 3C As shown, the plurality of die connections 120 may form a staggered array including a column of a plurality of active die connections 120A, a column of a plurality of dummy die connections 120B, a column of a plurality of dummy die connections 120C, and a column of a plurality of dummy die connections 120D.

[0057] exist Figure 4A , the plurality of upper integrated circuit dies 200 are bonded to the bonding layer 118 and the plurality of die connectors 120. The plurality of upper integrated circuit dies 200 may overlap with the plurality of lower integrated circuit dies 100. For example, Figure 4AAn embodiment is shown in which a plurality of upper integrated circuit dies 200A each overlap one lower integrated circuit die 100, and an upper integrated circuit die 200B overlaps two lower integrated circuit dies 100. Each of the two upper integrated circuit dies 200A can be electrically coupled to a corresponding lower integrated circuit die 100 below. The upper integrated circuit die 200B can be electrically coupled to the two lower integrated circuit dies 100. As a result, the plurality of lower integrated circuit dies 100 can be electrically coupled to each other through the upper integrated circuit die 200B. In some embodiments, the upper integrated circuit die 200B does not include any active devices and can therefore be referred to as a bridge die or silicon bridge. In some embodiments, the upper integrated circuit die 200B includes active devices and can therefore be referred to as an active integrated circuit die. Figure 4A The illustrated layout of the plurality of upper integrated circuit dies 200 on the bonding layer 118 is an example, and other layouts are contemplated.

[0058] Each upper integrated circuit die 200 may be a logic die (e.g., CPU, GPU, SoC, AP, microcontroller, etc.), a memory die (e.g., DRAM die, SRAM die, etc.), a power management die (e.g., PMIC die), an RF die, a sensor die, a MEMS die, a signal processing die (e.g., DSP die), a front-end die (e.g., AFE die), etc., or a combination thereof. The materials and manufacturing processes of the features in the upper integrated circuit die 200 may be found by referring to similar features in the lower integrated circuit die 100. Each upper integrated circuit die 200 may include a semiconductor substrate 202, which may have an active surface (e.g., a front side) that may be referred to as a front side. Figure 4A the surface facing downward) and the inactive surface which may be referred to as the backside (e.g., Figure 4A The backside of the semiconductor substrate 202 may also be referred to as the backside of the upper integrated circuit die 200 , and the frontside of the semiconductor substrate 202 may face the frontside of the upper integrated circuit die 200 .

[0059] A plurality of devices (not shown separately) may be disposed at the active surface of the semiconductor substrate 202. These devices may be active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. An interconnect structure 204 may be disposed on the active surface of the semiconductor substrate 202. The interconnect structure 204 may interconnect the plurality of devices to form an integrated circuit. The interconnect structure 204 may include a plurality of metallization patterns (not shown separately) in a plurality of dielectric layers (not shown separately). The plurality of metallization patterns may be electrically coupled to the plurality of devices. A bonding layer 206 may be disposed on the interconnect structure 204, located on the front side of the upper integrated circuit die 200. One or more passivation layers (not shown separately) may be disposed between the bonding layer 206 and the interconnect structure 204.

[0060] A plurality of die connectors 208 may extend through the bonding layer 206 and may be electrically coupled to the plurality of metallization patterns of the interconnect structure 204. The die connectors 208 may be referred to as bond pads. The plurality of die connectors 208 may include a plurality of active die connectors 208A, a plurality of dummy die connectors 208B, and a plurality of dummy die connectors 208C. The active die connectors 208A may be die connectors 208 electrically coupled to the active die connectors 120A. The dummy die connectors 208B and 208C may be die connectors 208 that contact the dummy die connectors 120B and 120C, respectively, in the bonding layer 118. The active die connectors 120A and 208A may be electrically coupled to circuitry of the lower integrated circuit die 100 and / or circuitry of the upper integrated circuit die 200. The dummy die connections 120B and 208B may be electrically isolated from the circuitry of the lower integrated circuit die 100 and the circuitry of the upper integrated circuit die 200 .

[0061] A seal ring 205 may extend through the interconnect structure 204 of each upper integrated circuit die 200. In a top view, the seal ring 205 may surround the multiple metallization patterns of the corresponding interconnect structure 204, and the area between the seal ring 205 and the multiple metallization patterns may be referred to as a Koz. The seal ring 205 may be made of the same or similar material and formed using the same or similar process as the metallization patterns. The seal ring 205 may be electrically isolated from the device.

[0062] The plurality of upper integrated circuit dies 200 may be placed using a pick-up process, etc., and then bonded to the bonding layer 118 and the plurality of die connectors 120 to bond the plurality of upper integrated circuit dies 200 to the bonding layer 118 and the plurality of die connectors 120. The plurality of bonding layers 206 of the plurality of upper integrated circuit dies 200 may be directly bonded to the bonding layer 118 using dielectric-to-dielectric bonding, and the plurality of die connectors 208 of the plurality of upper integrated circuit dies 200 may be directly bonded to corresponding die connectors 120 using metal-to-metal bonding. Figure 4A In the illustrated embodiment, the die connector 208 has the same or similar size and shape as the corresponding die connector 120. In other embodiments, the die connector 208 has the same or similar shape as the corresponding die connector 120, and the die connector 208 has a smaller size (e.g., width) than the corresponding die connector 120.

[0063] Bonding can include pre-bonding and annealing. During pre-bonding, a small pressure can be applied to press the multiple upper integrated circuit dies 200 against the bonding layer 118 and the multiple die connectors 120 (e.g., multiple active die connectors 120A, multiple dummy die connectors 120B, and multiple dummy die connectors 120C). Pre-bonding can be performed at low temperatures, such as room temperature. After pre-bonding, a direct bond, such as a dielectric-to-dielectric bond, can be formed between the multiple bonding layers 206 and the bonding layer 118. The bond strength between the multiple bonding layers 206 and the bonding layer 118 can then be increased in a subsequent higher temperature annealing step. The multiple die connectors 208 can be in physical contact with the multiple die connectors 120 after pre-bonding, or can expand during annealing to be in physical contact with the multiple die connectors 120. Furthermore, during the annealing step, the material of the die connect 208 may intermingle or bond with the material of the die connect 120, thereby forming a metal-to-metal bond. During the annealing step, the bonding layer 118 may also bond to portions of the plurality of dummy die connects 120D that are in contact with the bonding layer 118 through the dielectric-to-metal bond.

[0064] The plurality of dummy die connections 208C of the plurality of upper integrated circuit dies 200 can be bonded to the plurality of dummy die connections 120C above the interface between the plurality of lower integrated circuit dies 100 and the lower gap-filling layer 116. The bonded pairs of the plurality of dummy die connections 120C and the plurality of dummy die connections 208C located directly above the interface between the plurality of lower integrated circuit dies 100 and the lower gap-filling layer 116 can eliminate or reduce the impact of CTE mismatch between underlying materials (such as components of the lower integrated circuit die (e.g., semiconductor substrate 102) and the lower gap-filling layer 116) on the integrity of the bond between the upper integrated circuit die 200 and the bonding layer 118 and the die connections 120, thereby eliminating or reducing the risk of delamination of the upper integrated circuit die 200 during manufacture and operation of the integrated circuit package. As a result, better reliability of the integrated circuit package can be achieved.

[0065] Figure 4A As an example, a front-to-back bonding configuration is shown, wherein after bonding, the back side of the lower integrated circuit die 100 faces the front side of the upper integrated circuit die 200. Other bonding configurations may be used, such as a front-to-front bonding configuration or other bonding configurations. In a front-to-front bonding configuration, the front side of the lower integrated circuit die 100 may face the front side of the upper integrated circuit die 200.

[0066] Figure 4B According to some embodiments Figure 4A A top view of a region 121 of the structure is shown, wherein a plurality of die connectors 120 are arranged in an array. Figure 4A The cross-section shown can be taken along Figure 4B For illustration purposes, the bonding layer 118 is omitted, and portions of the interface between the upper integrated circuit die 200B and the plurality of lower integrated circuit dies 100 and the lower gap fill layer 116 below the plurality of dummy die connections 120C are shown in FIG. Figure 4B It is shown in dashed lines. Figure 4B As shown, the plurality of active die connections 120A, the plurality of dummy die connections 120B, and the plurality of dummy die connections 120C are completely covered by the upper integrated circuit die 200B, and the plurality of dummy die connections 120D are partially covered by the upper integrated circuit die 200B. Figure 4B In the illustrated embodiment, the plurality of dummy die connectors 120D may be a plurality of discrete pads that form a frame and extend beneath the edges of the upper integrated circuit die 200B. In other embodiments, the plurality of dummy die connectors 120D may be a plurality of discrete pads located beneath the corners of the upper integrated circuit die 200B. In still other embodiments, the plurality of dummy die connectors 120D may be a continuous frame and extend beneath the edges of the upper integrated circuit die 200B. The number of the plurality of die connectors 120 beneath the upper integrated circuit die 200B is provided as an example, and other numbers are contemplated.

[0067] exist Figure 5In the embodiment of the present invention, an upper gapfill layer 210 is formed around the plurality of upper integrated circuit dies 200. In a top view, the upper gapfill layer 210 may surround the plurality of upper integrated circuit dies 200. The upper gapfill layer 210 may extend along the sidewalls of the upper integrated circuit dies 200 (e.g., the semiconductor substrate 202, the interconnect structure 204, and the bonding layer 206). Exposed portions of the plurality of dummy die connectors 120D may contact the upper gapfill layer 210. As a result, the plurality of dummy die connectors 120D may contact the interface between the plurality of upper integrated circuit dies 200 (e.g., the bonding layer 206) and the upper gapfill layer 210. The upper gapfill layer 210 may be formed using the same or similar method as the lower gapfill layer 116 and may be formed from the same or similar dielectric material as the lower gapfill layer 116. A thinning process may be performed to remove portions of the backside of the plurality of semiconductor substrates 202 and the upper gapfill layer 210. The thinning process may be CMP, a grinding process, an etch-back process, a combination thereof, etc. After the thinning process, the surfaces of the upper gap-fill layer 210 and the plurality of upper integrated circuit dies 200 (including the semiconductor substrate 202 ) are substantially coplanar (within process variations).

[0068] exist Figure 6 , the carrier 212 is bonded to the upper surface of the plurality of semiconductor substrates 202 and the upper gap filling layer 210. The carrier 212 may be a semiconductor carrier, a glass carrier, a ceramic carrier, etc. The carrier 212 may be a wafer having the same or similar size as the carrier 112. In some embodiments, the carrier 212 is bonded to the plurality of semiconductor substrates 202 and the upper gap filling layer 210 using a bonding layer 213 and a bonding layer 214. The bonding layer 213 is formed on the plurality of semiconductor substrates 202 and the upper gap filling layer 210, and the bonding layer 214 is formed on the carrier 212. The bonding layer 213 and the bonding layer 214 may both include a dielectric material, such as silicon dioxide, etc., and may be formed by a suitable deposition process (such as CVD, ALD, etc.). The structure on the carrier 112 may be bonded Figure 4A The same or similar process described for bonding bonding layer 118 and bonding layer 206 is used to bond bonding layer 213 and bonding layer 214 to be bonded to carrier 212 .

[0069] exist Figure 7 In the embodiment of the present invention, the carrier 112 and the adhesive 114 are removed, and a dielectric layer 216 is formed on the lower gap fill layer 116 and the front side of the plurality of lower integrated circuit dies 100. The removal process may include projecting a light beam such as a laser beam or a UV beam onto the adhesive 114 (e.g., Figure 6, such that the adhesive 114 decomposes upon exposure to the light beam, and the carrier 112 can be removed. In some embodiments, the dielectric layer 216 comprises PBO, polyimide, a BCB-based polymer, or the like, and is formed by a suitable coating process (e.g., spin coating, lamination, etc.). In some embodiments, the dielectric layer 216 comprises silicon dioxide, silicon nitride, or the like, and is formed by a suitable deposition process such as CVD or ALD. In some embodiments, a redistribution structure (not separately shown) may be formed before forming the dielectric layer 216 to provide additional wiring.

[0070] exist Figure 8 In the embodiment of the present invention, a plurality of under-bump metallization (UBM) layers 218 and a plurality of electrical connectors 220 are formed. The UBMs 218 may have portions extending along the surface of the dielectric layer 216 and portions extending through the dielectric layer 216 to be physically and electrically coupled to the die connectors 110. As a result, the UBMs 218 are electrically coupled to the lower integrated circuit die 100.

[0071] As an example of forming multiple UBMs 218, dielectric layer 216 can be patterned to form multiple openings that expose the underlying multiple die connectors 110. Patterning can be accomplished using acceptable photolithography and etching processes, such as forming a mask and then performing anisotropic etching. The mask can be removed after patterning. A seed layer (not shown separately) can be formed on dielectric layer 216, in the multiple openings through dielectric layer 216, and on the exposed portions of the multiple die connectors 110. The seed layer can be a metal layer, which can be a single layer or a composite layer including multiple sublayers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using a suitable deposition process, such as physical vapor deposition (PVD). A photoresist can then be formed on the seed layer and patterned. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist can correspond to the multiple UBMs 218. The patterning may form a plurality of openings through the photoresist to expose the seed layer.

[0072] Conductive material can be formed in the plurality of openings in the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroless plating, electroplating, etc. The conductive material can include a metal or metal alloy, such as copper, titanium, tungsten, aluminum, etc., or a combination thereof. The photoresist and the portion of the seed layer on which the conductive material is not formed can then be removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using an oxygen plasma. Once the photoresist is removed, the portion of the seed layer on which the conductive material is not formed can be removed by an acceptable etching process, such as by wet or dry etching. The remaining portion of the seed layer and the conductive material can form a plurality of UBMs 218.

[0073] A plurality of electrical connectors 220 may be formed on the plurality of UBMs 218. The electrical connectors 220 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, or the like. In some embodiments, the electrical connectors 220 include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. The plurality of electrical connectors 220 may be initially formed by forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, reflow may be performed to shape the solder into the desired bump shape. In some embodiments, the electrical connector 220 comprises a metal pillar, such as a copper pillar, formed by sputtering, printing, electroplating, electroless plating, CVD, etc., which is solder-free and has substantially vertical sidewalls. A metal capping layer may be formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process. Figure 8 The structure shown may be referred to as wafer structure 250 .

[0074] exist Figure 9 In the embodiment, the wafer structure 250 is singulated to form individual integrated circuit package assemblies 250'. The processes discussed above can be performed using wafer-level processing. The carrier 212 can be a wafer and can include a number of components similar to Figure 8The structure shown (not separately shown). Wafer structure 250 can be placed on tape 222 supported by frame 224. Wafer structure 250 can then be singulated along a plurality of dicing streets 226 so that wafer structure 250 can be separated into a plurality of discrete integrated circuit package assemblies 250'. The singulation process can include a sawing process, a laser cutting process, etc. A cleaning process or a rinsing process can be performed after the singulation process.

[0075] exist Figure 10 , an integrated circuit package assembly 250′ is bonded to a package substrate 228, and an underfill 234 is formed between the integrated circuit package assembly 250′ and the package substrate 228. The package substrate 228 may include a plurality of conductive pads 230. In some embodiments, the package substrate 228 includes a material such as a fiberglass reinforced resin, a bismaleimide-triazine (BT) resin, or other printed circuit board (PCB) materials. In some embodiments, the package substrate 228 includes a material such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

[0076] The packaging substrate 228 may include a plurality of active and passive devices (not shown separately), such as transistors, capacitors, resistors, combinations thereof, and the like. These devices may be formed using any suitable method. The packaging substrate 228 may include a plurality of metallization layers and a plurality of through-holes (not shown separately) that are physically and electrically coupled to the plurality of conductive pads 230. The metallization layers may be formed over the plurality of active and passive devices and may connect the various devices to form functional circuits. The plurality of metallization layers may be alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), with a plurality of through-holes interconnecting the plurality of conductive material layers. In some embodiments, the packaging substrate 228 is free of active and passive devices.

[0077] During the bonding process, the plurality of electrical connectors 220 can be reflowed to bond the integrated circuit package assembly 250' to the plurality of conductive pads 230. The plurality of electrical connectors 220 can electrically and physically couple the package substrate 228 to the integrated circuit package assembly 250'. In some embodiments, a solder resist (not separately shown) is formed on the package substrate 228. The plurality of electrical connectors 220 can be disposed in a plurality of openings in the solder resist to electrically and physically couple to the plurality of conductive pads 230. The solder resist can be used to protect areas of the package substrate 228 from external damage.

[0078] Underfill 234 can surround the plurality of electrical connectors 220 and protect the plurality of joints created by reflowing the plurality of electrical connectors 220. In a top view, underfill 234 can surround the integrated circuit package 250'. Underfill 234 can be formed using a capillary flow process after attaching the integrated circuit package 250', or by a suitable deposition method before attaching the integrated circuit package 250'. Underfill 234 can then be cured. Figure 10 The illustrated structure may be referred to as an integrated circuit package 300 .

[0079] Various embodiments are described above in the context of a system on integrated chip (SoIC) packaging configuration. It should be understood that various embodiments may also be applicable to other packaging configurations, such as integrated fan-out on substrate (InFO), chip on wafer on substrate (CoWoS), etc. Various embodiments are described above in the context of a system on integrated chip (SoIC) packaging configuration. It should be understood that various embodiments may also be applicable to other packaging configurations, such as integrated fan-out on substrate (InFO), chip on wafer on substrate (CoWoS), etc.

[0080] These embodiments can have several advantageous properties. By forming the plurality of dummy die connectors 120C directly above the interface between the plurality of lower integrated circuit dies 100 and the lower gap-fill layer 116, the effect of the CTE mismatch between components of the plurality of lower integrated circuit dies 100 (e.g., semiconductor substrate 102) and the lower gap-fill layer 116 on the bonding integrity between the plurality of upper integrated circuit dies 200 and the bonding layer 118 and the plurality of die connectors 120 can be eliminated or reduced, thereby eliminating or reducing the risk of delamination of the plurality of upper integrated circuit dies 200 during manufacture and operation of the integrated circuit package 300. As a result, improved reliability of the integrated circuit package 300 can be achieved.

[0081] In one embodiment, an integrated circuit package includes a first die; a first gapfill layer along a plurality of sidewalls of the first die; a first bonding layer on the first die and the first gapfill layer; and a first die connector in the first bonding layer, wherein the first die connector is directly above an interface between the first die and the first gapfill layer. In one embodiment, the first die includes a first semiconductor substrate, wherein the first die connector contacts the first semiconductor substrate and the first gapfill layer. In one embodiment, the first die connector is electrically isolated from circuitry of the first die. In one embodiment, the integrated circuit package further includes a second die connector and a third die connector in the first bonding layer, wherein the first die connector is located between the second die connector and the third die connector, wherein the second die connector and the third die connector are the closest die connectors to the first die connector along a first direction, wherein the second die connector is electrically coupled to circuitry of the first die, and wherein the third die connector is located above the first gapfill layer and electrically isolated from circuitry of the first die. In one embodiment, the second die connector is spaced apart from the first die connector by a first distance and the third die connector is spaced apart from the first die connector by a second distance, wherein the first distance is greater than the second distance. In one embodiment, the second die connector is spaced apart from the first die connector by a first distance and the third die connector is spaced apart from the first die connector by a second distance, wherein the first distance is equal to the second distance. In one embodiment, the integrated circuit package further includes a second die bonded to the first bonding layer, and a second gap-filling layer on the first bonding layer, the second gap-filling layer extending along a plurality of sidewalls of the second die.

[0082] In one embodiment, an integrated circuit package includes a first die, wherein the first die further includes a first semiconductor substrate; a first gap filler layer on multiple sidewalls of the first die; a first bonding layer on the first gap filler layer and the first semiconductor substrate; a first die connector in the first bonding layer, wherein the first die connector contacts an interface between the first die and the first gap filler layer; and a second die including a second bonding layer and a second die connector in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer and the second die connector is bonded to the first die connector. In one embodiment, the first gap filler layer has a coefficient of thermal expansion that is different from a coefficient of thermal expansion of the first semiconductor substrate. In one embodiment, in a top view, the interface between the first die and the first gap filler layer divides the first die connector into two portions of equal size. In one embodiment, in a top view, the interface between the first die and the first gap filler layer divides the first die connector into two portions of different sizes. In one embodiment, the first die connector is a dummy die connector. In one embodiment, the integrated circuit package further includes a second gap-filling layer on a plurality of sidewalls of the second die, wherein the second gap-filling layer extends over a third die connector in the first bonding layer, wherein the third die connector contacts an interface between the second die and the second gap-filling layer.

[0083] In one embodiment, a method of forming an integrated circuit package includes attaching a first die to a carrier, wherein the first die includes a first substrate, wherein the first substrate includes a semiconductor material; forming a first gapfill layer on a first sidewall of the first die, wherein the first gapfill layer includes a dielectric material; forming a first bonding layer on a top surface of the first die and a top surface of the first gapfill layer; and forming a first die connector in the first bonding layer, wherein, in a top view, the first die connector overlaps an interface between the first die and the first gapfill layer. In one embodiment, the first die connector contacts the first substrate and the first gapfill layer. In one embodiment, the method further includes attaching a second die to the carrier, wherein the second die includes a second substrate, wherein a first portion of the first gapfill layer is located between a first sidewall of the first die and a first sidewall of the second die, and wherein forming the first bonding layer includes forming the first bonding layer on a top surface of the second die; and forming a second die connector in the first bonding layer, wherein, in a top view, the second die connector overlaps an interface between the second die and the first gapfill layer. In one embodiment, the method further includes forming a third die connector in the first bonding layer, wherein the third die connector is located between the first sidewall of the first die and the first sidewall of the second die. In one embodiment, the method further includes bonding the third die to the first bonding layer, the first die connector, the second die connector, and the third die connector using dielectric-to-dielectric bonding and metal-to-metal bonding. In one embodiment, the first die connector, the second die connector, and the third die connector are isolated from the circuitry of the first die, the circuitry of the second die, and the circuitry of the third die. In one embodiment, the method further includes forming a second die connector in the first bonding layer, wherein the first via of the first die extends through the first substrate and contacts the second die connector in the first bonding layer.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art will understand that they can easily use the present invention as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit package, characterized in that: include: a first tube core; a first gap-fill layer along a plurality of sidewalls of the first die; a first bonding layer located on the first die and the first gap-filling layer; as well as A first die connector is located in the first bonding layer, wherein the first die connector is directly located on an interface between the first die and the first gap-fill layer.

2. The integrated circuit package according to claim 1, wherein: The first die includes a first semiconductor substrate, wherein the first die connector contacts the first semiconductor substrate and the first gap-fill layer.

3. The integrated circuit package according to claim 1, wherein: The first die connection is electrically isolated from circuitry of the first die.

4. The integrated circuit package according to claim 1, wherein: Also included are a second die connector and a third die connector in the first bonding layer, wherein the first die connector is between the second die connector and the third die connector, wherein the second die connector and the third die connector are closest die connectors to the first die connector along a first direction, wherein the second die connector is electrically coupled to circuitry of the first die connector, and wherein the third die connector is located above the first gapfill layer, the third die connector is electrically isolated from the circuitry of the first die.

5. An integrated circuit package, characterized in that: include: a first die, wherein the first die further comprises a first semiconductor substrate; a first gap-filling layer, located on a plurality of sidewalls of the first die; a first bonding layer, located on the first gap-filling layer and the first semiconductor substrate; a first die connector located in the first bonding layer, wherein the first die connector contacts an interface between the first die and the first gap-fill layer; as well as A second die includes a second bonding layer and a second die connector in the second bonding layer, wherein the second bonding layer is bonded to the first bonding layer and the second die connector is bonded to the first die connector.

6. The integrated circuit package according to claim 5, wherein: A thermal expansion coefficient of the first gap-filling layer is different from a thermal expansion coefficient of the first semiconductor substrate.

7. The integrated circuit package according to claim 5, wherein: In a top view, the interface between the first die and the first gap-filling layer divides the first die connector into two parts of equal size.

8. The integrated circuit package according to claim 5, wherein: In a top view, the interface between the first die and the first gap-filling layer divides the first die connector into two parts of different sizes.

9. The integrated circuit package according to claim 5, wherein: The first die connector is a dummy die connector.

10. The integrated circuit package according to claim 5, wherein: Also included is a second gap-filling layer on a plurality of sidewalls of the second die, wherein the second gap-filling layer extends over a third die connector in the first bonding layer, wherein the third die connector contacts an interface between the second die and the second gap-filling layer.

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