Integrated circuit package

Abstract

The embodiment of the utility model provides an integrated circuit packaging piece which comprises a packaging substrate, an integrated circuit device attached to the packaging substrate, and a reinforcing ring arranged around the integrated circuit device and attached to the packaging substrate. An integrated circuit device includes a reinforcement ring, a cover attached to the reinforcement ring, a channel connected to a region between the cover and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top view, and a thermal interface material in the channel and in the region between the cover and the integrated circuit device. The thermal interface material may flow into the channel upon melting. Therefore, formation or redistribution of pores in the thermal interface material can be reduced, and leakage of the thermal interface material can be avoided.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated circuit package, and more particularly to an integrated circuit package including a device attached to an integrated circuit using a thermal interface material. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In large part, this increase in integration density is achieved by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. As the demand for smaller electronic devices continues to grow, the demand for smaller and more innovative semiconductor die packaging technologies has also emerged. Utility Model Content

[0003] An embodiment of the present invention provides an integrated circuit package including a package substrate, an integrated circuit device attached to the package substrate, a stiffening ring surrounding the integrated circuit device and attached to the package substrate, a lid attached to the stiffening ring, a channel connected to a region between the lid and the integrated circuit device, and a thermal interface material in the channel and in the region between the lid and the integrated circuit device. In a top view, the channel extends along at least one side of the integrated circuit device.

[0004] An embodiment of the present invention provides an integrated circuit package including a package substrate, an integrated circuit device attached to the package substrate, a thermal interface material on a top surface of the integrated circuit device, and a lid. The lid has a main portion on the thermal interface material and a protruding portion extending through the thermal interface material, the protruding portion surrounding a portion of the thermal interface material and physically contacting the top surface of the integrated circuit device.

[0005] Based on the above, an integrated circuit package includes a package lid attached to an integrated circuit device using a liquid metal thermal interface material. The integrated circuit package includes a channel into which the thermal interface material flows when molten. This reduces the formation or redistribution of voids in the thermal interface material, which helps prevent leakage of the thermal interface material. The package lid includes a protrusion that physically contacts the integrated circuit device to reduce warping, thereby preventing leakage of the thermal interface material during warping. This improves the reliability and / or performance of the integrated circuit package.

[0006] In order to make the above features and advantages of the embodiments of the present invention more obvious and easy to understand, the following embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1It is a cross-sectional view of an integrated circuit die.

[0008] Figures 2A-2B is a cross-sectional view of the die stack.

[0009] Figure 3 is a cross-sectional view of the package component.

[0010] Figure 4-10 is a diagram of an intermediate stage in the fabrication of an integrated circuit package, according to some embodiments.

[0011] Figure 11-12 is a diagram of an integrated circuit package according to some embodiments.

[0012] Figure 13-14 is a diagram of an integrated circuit package according to some embodiments.

[0013] Figure 15 is a diagram of an integrated circuit package 100 according to some embodiments.

[0014] Figure 16 is a diagram of an integrated circuit package 100 according to some embodiments.

[0015] Figure 17 is a diagram of an integrated circuit package 100 according to some embodiments.

[0016] Figure 18 is a diagram of an integrated circuit package 100 according to some embodiments.

[0017] Figure 19 is a diagram of an integrated circuit package 100 according to some embodiments.

[0018] Description of Reference Numerals

[0019] 50: integrated circuit die; 50A: first integrated circuit die; 50B: second integrated circuit die; 52: semiconductor substrate; 54, 84: interconnect structure; 56: dielectric layer; 58: die connector; 60A, 60B: die stacking; 62, 86: vias; 70: package assembly; 72: integrated circuit device; 72A: logic device; 72B: memory device; 74, 108: conductive connector; 76: encapsulation; 80: interposer; 82: substrate; 88: under-bump metallurgy (UBM); 100: integrated circuit package; 102: package substrate; 104: substrate core; 106: bonding pad; 110: Bottom filler; 112: passive device; 120, 132: adhesive; 120A, 140A: first portion; 120B, 140B: second portion; 122: stiffener ring; 122L: lower portion; 122U: upper portion; 124: aperture; 126: opening; 128: thermal interface material; 134: package lid; 134M: main portion; 134P: protrusion; 134R: ring portion; 140: area; 142: channel; A-A': cross section; H1, H2, H3, H4, H5, H6, H7, H8, H9: height; W1, W2, W3, W5, W6, W7, W8: width. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to limit the scope of the present disclosure. For example, in the following description, a first feature is formed "above" or "on" a second feature, which may include an embodiment in which the first feature and the second feature are formed to be in direct contact, or an embodiment in which an additional feature is formed between the first feature and the second feature so that the first feature and the second feature are not in direct contact. In addition, the present disclosure may reuse component numbers and / or letters in various examples. Such repetition is for the purpose of simplifying and clarifying the description of the present disclosure, and is not intended to limit the relationship between the various embodiments and / or configurations.

[0021] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one component or feature to another component or feature as depicted in the figures. These spatially relative terms encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used therein may be interpreted in a similar manner.

[0022] According to various embodiments, an integrated circuit package includes a package lid attached to an integrated circuit device using a liquid metal thermal interface material. The integrated circuit package includes features that help address the challenges of using liquid metal thermal interface materials. The integrated circuit package may include channels into which the thermal interface material can flow when melted. As a result, the formation or redistribution of pores in the thermal interface material can be reduced, which can help prevent leakage of the thermal interface material. Additionally or alternatively, the package lid can include a protrusion that physically contacts the integrated circuit device to reduce warping, which can prevent leakage of the thermal interface material during warping. This can improve the reliability and / or performance of the integrated circuit package.

[0023] Figure 1 : is a cross-sectional view of an integrated circuit die 50. Multiple integrated circuit dies 50 will be packaged in subsequent processes to form an integrated circuit package. Each integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC) die, an application processor (AP), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc., or a combination thereof.

[0024] The integrated circuit die 50 may be formed in a wafer that may include different die regions that are singulated in subsequent steps to form a plurality of integrated circuit dies 50. The integrated circuit die 50 may be processed according to an applicable manufacturing process to form an integrated circuit. For example, the integrated circuit die 50 includes a semiconductor substrate 52, which may be a doped or undoped silicon substrate or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials (e.g., germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide), or combinations thereof. Other substrates may also be used, such as multilayer or gradient substrates. The semiconductor substrate 52 has an active surface (e.g., Figure 1 upward facing surface) and non-active surfaces (e.g. Figure 1 Surfaces facing downward in the semiconductor substrate 52). Devices (not separately shown) may be formed in and / or on the active surface of the semiconductor substrate 52. The devices may be active devices (e.g., transistors, diodes, etc.) and / or passive devices (e.g., capacitors, inductors, resistors, etc.). The inactive surface may not have devices.

[0025] The interconnect structure 54 is disposed above the active surface of the semiconductor substrate 52 and is used to electrically connect the devices on the semiconductor substrate 52 to form an integrated circuit. The interconnect structure 54 may include one or more dielectric layers and one or more corresponding metallization layers within the dielectric layers. The dielectric layer may be, for example, a low-k dielectric layer. The one or more metallization layers may include vias and / or conductive lines to interconnect the devices on the semiconductor substrate 52. The one or more metallization layers may be formed from a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, or combinations thereof. The one or more metallization layers of the interconnect structure 54 may be formed using a damascene process (e.g., a single damascene process, a dual damascene process, etc.).

[0026] A dielectric layer 56 is formed over the interconnect structure 54 at the front side of the integrated circuit die 50. The dielectric layer 56 can be formed from an oxide (e.g., silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS)-based oxide, or the like), a nitride (e.g., silicon nitride or the like), a polymer (e.g., polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer, or the like), combinations thereof, or the like. The dielectric layer 56 can be formed, for example, by CVD, spin coating, lamination, or the like. One or more passivation layers (not separately shown) can optionally be disposed between the dielectric layer 56 and the interconnect structure 54.

[0027] The die connector 58 extends through the dielectric layer 56. The die connector 58 may include a conductive post, pad, or the like that allows for external connection. The die connector 58 may be formed from a suitable conductive material (e.g., copper, tungsten, aluminum, silver, gold, combinations thereof, or the like), which may be formed, for example, by electroplating. In some embodiments, the die connector 58 includes a bond pad on the front side of the integrated circuit die 50 and includes a bond pad via that connects the bond pad to the upper metallization layer of the interconnect structure 54. In such embodiments, the die connector 58 (including the bond pad and bond pad via) may be formed by a damascene process (e.g., a single damascene process, a dual damascene process, etc.). The top surfaces of the die connector 58 and the dielectric layer 56 may be coplanar (within process variations).

[0028] During the formation of the integrated circuit die 50, a solder area (not shown separately) may be optionally provided on the die connector 58. The solder area may be used to perform a chip probe (CP) test on the integrated circuit die 50. For example, the solder area may be a solder ball, a solder bump, or the like, which is used to attach a chip probe to the die connector 58. The integrated circuit die 50 may be subjected to a chip probe test to determine whether the integrated circuit die 50 is a known good die (KGD). In this way, only the integrated circuit die 50 (i.e., KGD) is subsequently processed and packaged, while the die that fails the chip probe test is not packaged. After testing, the solder area may be removed. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like is used.

[0029] Figures 2A-2B Figures 60 and 60B are cross-sectional views of die stacks 60A and 60B, respectively. Die stacks 60A and 60B may each have a single function (e.g., a logic device, a memory die, etc.) or may have multiple functions. In some embodiments, die stack 60A is a logic device (e.g., a system-on-integrated-chip (SoIC) device) and die stack 60B is a memory device (e.g., a high-bandwidth memory (HBM) device).

[0030] like Figure 2A As shown, die stack 60A includes two bonded integrated circuit dies 50 (e.g., a first integrated circuit die 50A and a second integrated circuit die 50B). In some embodiments, first integrated circuit die 50A is a logic die and second integrated circuit die 50B is an interface die. The interface die bridges the logic die to the memory die and converts instructions between the logic die and the memory die. In some embodiments, first integrated circuit die 50A and second integrated circuit die 50B are bonded so that the active surfaces face each other (e.g., a "front-to-front" bond). Vias 62 can be formed through one of the integrated circuit dies 50 to enable external connections to die stack 60A. Vias 62 can be through-substrate vias (TSVs), such as through-silicon vias (TSVs). In the illustrated embodiment, vias 62 are formed in second integrated circuit die 50B (e.g., the interface die). Vias 62 extend through the semiconductor substrate 52 of the corresponding integrated circuit die 50 to physically and electrically connect to the metallization layer of the interconnect structure 54.

[0031] like Figure 2B As shown, die stack 60B is a stacked device including multiple semiconductor substrates 52. For example, die stack 60B may be a memory device including multiple memory dies (e.g., a hybrid memory cube (HMC) device, a high bandwidth memory (HBM) device, etc.). Each semiconductor substrate 52 may or may not have a separate interconnect structure 54. The semiconductor substrates 52 are connected by vias 62 (e.g., TSVs).

[0032] Figure 3 FIG. 8 is a cross-sectional view of a package assembly 70 . The package assembly 70 includes an integrated circuit device 72 bonded to an interposer 80 . The interposer 80 includes a substrate 82 , interconnect structures 84 , vias 86 , and under bump metallurgy (UBM) 88 .

[0033] The substrate 82 may be a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer semiconductor substrate, or the like. The substrate 82 may include semiconductor materials (e.g., silicon, germanium), compound semiconductors (including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), alloy semiconductors (including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used. The substrate 82 may be doped or undoped. In embodiments, the substrate 82 typically does not include active devices therein, although the interposer 80 may include a substrate formed on the front surface of the substrate 82 (e.g., Figure 3 In embodiments where interposer 80 includes an integrated circuit, active devices (e.g., transistors, capacitors, resistors, diodes, etc.) may be formed in and / or on the front surface of substrate 82.

[0034] The interconnect structure 84 is located above the front surface of the substrate 82 and is used to electrically interconnect the devices (if any) on the substrate 82. The interconnect structure 84 may include one or more dielectric layers and one or more corresponding metallization layers within the dielectric layers. The dielectric layers may be, for example, low-k dielectric layers. The one or more metallization layers may include vias and / or conductive lines to interconnect the devices on the semiconductor substrate 52. The one or more metallization layers may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, or combinations thereof. The one or more metallization layers of the interconnect structure 84 may be formed using a damascene process (e.g., a single damascene process, a dual damascene process, etc.).

[0035] In some embodiments, die connectors (not separately shown) are on the front side of interposer 80. For example, interposer 80 may include die connectors connected to an upper metallization layer of interconnect structure 84.

[0036] Vias 86 extend into interconnect structure 84 and / or through substrate 82. Vias 86 are electrically connected to one or more metallization layers of interconnect structure 84. Vias 86 may be TSVs. As examples of forming vias 86, recesses may be formed in interconnect structure 84 and / or substrate 82, for example, by etching, milling, laser technology, or combinations thereof. A thin barrier layer may be conformally deposited in the openings, for example, by CVD, atomic layer deposition (ALD), physical vapor deposition (PVD), thermal oxidation, or combinations thereof. The barrier layer may be formed of an oxide, nitride, carbide, or combinations thereof. A conductive material may be deposited over the barrier layer and in the openings. The conductive material may be formed by electrochemical plating processes, CVD, ALD, PVD, or combinations thereof. Examples of conductive materials include copper, tungsten, aluminum, silver, gold, or combinations thereof. Excess conductive material and the barrier layer are removed from the surface of the interconnect structure 84 or substrate 82, for example, by CMP. The remaining portions of the barrier layer and the conductive material form vias 86. The substrate 82 may then be thinned to expose the vias 86 at the backside of the substrate 82. Exposing the vias 86 may be achieved by a thinning process, such as a grinding process, chemical mechanical polishing (CMP), etch back, a combination thereof, or the like.

[0037] The UBM 88 is formed on the exposed surface of the via 86 on the back side of the substrate 82. The UBM 88 may be formed of a metal such as copper, aluminum, or the like and may be formed, for example, by electroplating. Conductive connectors for external connections will then be formed on the UBM 88.

[0038] Integrated circuit devices 72 are attached to the front side of interposer 80. Multiple integrated circuit devices 72 are arranged adjacent to each other. Integrated circuit devices 72 may include one or more logic devices 72A and one or more memory devices 72B. One or more logic devices 72A and one or more memory devices 72B may be formed using a process at the same technology node or may be formed using processes at different technology nodes. For example, one or more logic devices 72A may be formed using a more advanced process node than memory devices 72B.

[0039] Each logic device 72A may be a central processing unit (CPU), a graphics processing unit (GPU), a system on a chip (SoC), an application processor (AP), a microcontroller, etc. The logic device 72A may be an integrated circuit die (similar to Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the Figure 2AIn some embodiments, one or more logic devices 72A are integrated circuit dies, such as system-on-a-chip (SoC) dies. In some embodiments, one or more logic devices 72A are die stacks, such as system-on-integrated-on-a-chip (SoIC) devices.

[0040] Each memory device 72B may be a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, etc. The memory device 72B may be an integrated circuit die (similar to Figure 1 The integrated circuit die 50 described above may be a die stack (similar to the Figure 2B In some embodiments, one or more memory devices 72B are die stacks, such as high bandwidth memory (HBM) modules.

[0041] In the illustrated embodiment, the integrated circuit device 72 is attached to the interposer 80 using conductive connectors 74 (e.g., solder bonds). An underfill (not separately shown) may be formed around the conductive connectors 74 and between the interposer 80 and the integrated circuit device 72. In other embodiments (not separately shown), the integrated circuit device 72 is attached to the interposer 80 using direct bonding (e.g., a combination of dielectric-to-dielectric bonding and metal-to-metal bonding). When direct bonding is used, the underfill may be omitted. Furthermore, a mix of bonding techniques may be used, for example, some integrated circuit devices 72 may be attached to the interposer 80 using solder bonds, while other integrated circuit devices 72 may be attached to the interposer 80 using direct bonding.

[0042] Encapsulant 76 is formed on and around each component. Encapsulant 76 encapsulates integrated circuit device 72. Encapsulant 76 may be a molding compound, epoxy resin, or the like. Encapsulant 76 may be applied by compression molding, transfer molding, or the like, and may be formed over interposer 80 so that integrated circuit device 72 is buried or covered. Encapsulant 76 may be applied in a liquid or semi-liquid form and then cured. Encapsulant 76 may be optionally thinned to expose integrated circuit device 72. The thinning process may be a grinding process, chemical mechanical polishing (CMP), etch back, or a combination thereof.

[0043] Package assembly 70 is formed by bonding an integrated circuit device 72 to a wafer including an interposer 80. An encapsulant 76 may be formed around the integrated circuit device 72 and on the wafer. The structure is then flipped to process the backside of the wafer. The backside of the wafer may be thinned to expose vias 86, and then UBMs 88 may be formed. The wafer may then be singulated to form package assembly 70, which includes the singulated portion of the wafer (e.g., interposer 80) and the integrated circuit device 72 bonded to the interposer 80. In an embodiment, package assembly 70 is a chip-on-wafer (CoW) component, but it should be understood that embodiments may be applied to other three-dimensional integrated circuit (3DIC) packages.

[0044] Figure 4-10 is a diagram of an intermediate stage in the fabrication of an integrated circuit package 100 , according to some embodiments. Figure 4 、 5 , 6, 7, 8, and 9 are cross-sectional views. Figure 10 1 is a top view. The integrated circuit package 100 is formed by attaching the package component 70 to the package substrate 102. In addition, the package cover 134 is attached to the package component 70. The resulting integrated circuit package 100 is as shown in FIG. Figure 9-10 In an embodiment, the integrated circuit package 100 is a chip-on-wafer-on-substrate ( ) package, but it should be understood that the embodiments can be applied to other 3DIC packages.

[0045] exist Figure 4, the package assembly 70 is attached to the package substrate 102. The package substrate 102 includes a substrate core 104, which can be made of a semiconductor material such as silicon, germanium, diamond, etc. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphide, gallium indium phosphide, combinations thereof, or the like can also be used. In addition, the substrate core 104 can be an SOI substrate. Generally, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. In an alternative embodiment, the substrate core 104 is an insulating core, such as a glass fiber reinforced resin core. An example of the core material is glass fiber resin, such as FR4. Alternative core materials include bismaleimide-triazine (BT) resin, or another alternative is other printed circuit board (PCB) materials or films. A build-up film (eg, Ajinomoto build-up film (ABF)) or other laminating films may be used for the substrate core 104 .

[0046] The substrate core 104 may include active and passive devices (not individually shown). Devices (eg, transistors, capacitors, resistors, combinations thereof, etc.) may be used to generate the structural and functional requirements of a system design. Devices may be formed using any suitable method.

[0047] The substrate core 104 may also include metallization layers and vias (not separately shown) and bonding pads 106 over the metallization layers and vias. The metallization layers may be formed over active and passive devices and are designed to connect the various devices to form functional circuits. The metallization layers may be formed from alternating layers of dielectric material (e.g., low-k dielectric material) and conductive material (e.g., copper), wherein the vias interconnect the conductive material layers and may be formed by any suitable process (e.g., deposition, damascene, etc.). In some embodiments, the substrate core 104 is substantially free of active and passive devices.

[0048] The package assembly 70 can be attached to the package substrate 102 using conductive connectors 108 (e.g., solder joints). The conductive connectors 108 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, etc. The conductive connectors 108 can be formed from a reflowable conductive material (e.g., solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof). In some embodiments, the conductive connectors 108 are formed by first forming a layer of solder using evaporation, electroplating, printing, solder transfer, ball planting, etc. Once a layer of solder is formed on the underlying structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 108 comprises a metal pillar (e.g., a copper pillar) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal pillar may not have solder and has substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillar. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or a combination thereof, and may be formed by an electroplating process.

[0049] Attaching the package assembly 70 to the package substrate 102 may include placing the package assembly 70 on the package substrate 102 and reflowing the conductive connectors 108. The conductive connectors 108 are reflowed to connect the UBM 88 (refer to FIG. Figure 3 ) is attached to the bonding pads 106 of the package substrate 102. The conductive connector 108 connects the package assembly 70 (including the metallization layer of the interposer 80 (see Figure 3 )) is connected to the package substrate 102 (including the metallization layer in the substrate core 104). Therefore, the package substrate 102 is electrically connected to the integrated circuit device 72 (see Figure 3 In some embodiments, a passive device (e.g., a surface mount device (SMD), not separately shown) is first attached to package assembly 70 (e.g., to UBM 88) before being mounted to package substrate 102. In such embodiments, the passive device can be attached to the same surface of package assembly 70 as conductive connector 108.

[0050] In some embodiments, underfill 110 is formed between package component 70 and package substrate 102 to surround conductive connector 108. Underfill 110 may be formed by a capillary flow process after attaching package component 70 or may be formed by a suitable deposition method before attaching package component 70. Underfill 110 may be a continuous material extending from package substrate 102 to package component 70.

[0051] Additionally, a passive device 112 is attached to the package substrate 102. The passive device 112 is attached to the same surface of the package substrate 102 as the conductive connector 108. The passive device 112 may be attached to the package substrate 102 before or after the package assembly 70 is attached to the package substrate 102. The passive device 112 may include a capacitor, a resistor, an inductor, the like, or a combination thereof. The passive device 112 may be a surface mount device (SMD), a two-terminal integrated passive device (IPD), a multi-terminal IPD, or the like.

[0052] exist Figure 5 , adhesive 120 is formed on package substrate 102. Adhesive 120 will be used to attach the package stiffener to the package substrate. In some embodiments, a first portion 120A of adhesive 120 is formed on the sidewalls of bottom filler 110 and / or package component 70, while a second portion 120B of adhesive 120 is formed around passive device 112 and / or package component 70. Adhesive 120 can be any suitable adhesive, epoxy, adhesive film, etc. A steel plate having the desired pattern of adhesive 120 can be used to form adhesive 120 in the desired location using a suitable dispensing technique. Adhesive 120 can have vertical sidewalls (as shown) or can have curved sidewalls (not shown separately).

[0053] exist Figure 6 In the embodiment of the present invention, a reinforcement ring 122 is attached to the package substrate 102 and to the package assembly 70 using an adhesive 120. The reinforcement ring 122 is a package stiffener that helps reduce warpage of the package substrate 102 and the package assembly 70. The reinforcement ring 122 is formed from a rigid material, such as copper, aluminum, cobalt, nickel-plated copper, stainless steel, tungsten, copper-tungsten alloy, copper-molybdenum alloy, silver-diamond, copper-diamond, metal-diamond composite, aluminum nitride, aluminum silicon carbide, iron-nickel alloy (e.g., Alloy 42), the like, or a combination thereof. In some embodiments, the reinforcement ring 122 includes a body formed from a first metal that is partially or completely coated with a second metal, such as gold, nickel, titanium-gold alloy, lead, tin, nickel-vanadium alloy, or the like. The reinforcement ring 122 can be attached to the package substrate 102 by clamping the reinforcement ring 122 with the adhesive 120 at high temperature and curing the adhesive 120.

[0054] In this embodiment, the reinforcement ring 122 includes an upper portion 122U and a lower portion 122L. The upper portion 122U is located above the package component 70. The upper portion 122U is attached to the package substrate 102 using the portion of the adhesive 120 that is located on the underfill 110 and / or the sidewalls of the package component 70. The upper portion 122U may be coupled to the periphery of the package component 70, depending on the shape of those portions of the adhesive 120. Therefore, the adhesive 120 may or may not fill the area where the reinforcement ring 122 overlaps the package component 70. The lower portion 122L surrounds the periphery of the package component 70. The lower portion 122L is attached to the package substrate 102 using the portion of the adhesive 120 that is located around the passive device 112 and / or the package component 70. The width of the upper portion 122U is greater than the width of the lower portion 122L. The height of the reinforcement ring 122 is greater than the height of the package component 70.

[0055] Adhesive 120 acts as a dam to seal the area between package substrate 102 and stiffener ring 122, forming aperture 124. In a top view, aperture 124 may be located around package assembly 70. Stiffener ring 122 overlaps passive device 112, so passive device 112 is within aperture 124. By sealing aperture 124 with adhesive 120, thermal interface material subsequently formed on package assembly 70 may have a reduced risk of flowing toward passive device 112 and shorting it, even when the thermal interface material is liquid.

[0056] An opening 126 extends through the middle of the stiffening ring 122. In a top view, the stiffening ring 122 can be a rectangular ring defined by the horizontal and vertical portions of the stiffening ring 122. The opening 126 is disposed above the package assembly 70. The width of the opening 126 can be less than the width of the package assembly 70. The opening 126 provides an area in which a package lid can subsequently be disposed, such that the package lid can be directly attached to the package assembly 70. The package lid acts as a heat sink and, therefore, can be directly and thermally coupled to the package assembly 70 (the stiffening ring 122 is not in the thermal path between the package lid and the package assembly 70), helping to reduce the formation of hot spots in the package assembly 70.

[0057] exist Figure 7In the embodiment of the present invention, a thermal interface material 128 is formed in the opening 126 through the stiffener ring 122 and on the package assembly 70. The thermal interface material 128 will be used to attach the package lid to the package assembly 70. The thermal interface material 128 has a high thermal conductivity. In some embodiments, the thermal interface material 128 is a liquid metal. Liquid metal is a metal that melts at a temperature below about 100°C and is in a liquid phase. Acceptable liquid metals may include solder, indium, copper, bismuth, tin, rhodium, palladium, platinum, silver, gold, gallium, combinations thereof, or the like, which are applied in film form or liquid form. The thermal interface material 128 can be dispensed into the opening 126 and onto the package assembly 70 using a suitable dispensing technique. The thermal interface material 128 can be placed in the opening 126 and onto the package assembly 70 by placing a piece of liquid metal on the package assembly 70 using a suitable pick and place technique. In some embodiments, the package assembly 70 lacks backside metallization, and thus the thermal interface material 128 may be formed directly on the backside surface of the package assembly 70 (eg, the backside of the integrated circuit device 72, see FIG. 1 ). Figure 3 Using liquid metal as thermal interface material 128 allows for a significant amount of heat to be dissipated to the subsequently attached package lid, which can be particularly advantageous when integrated circuit package 100 is used in certain devices, such as high-performance computing (HPC) systems and artificial intelligence (AI) accelerators. Liquid metal can have a thermal resistance ten times lower than that of solid thermal interface materials, such as thermal gel.

[0058] exist Figure 8 , adhesive 132 is formed on reinforcement ring 122. Adhesive 132 will be used to attach the package lid to reinforcement ring 122. Adhesive 132 can be any suitable adhesive, epoxy, adhesive film, etc. A steel plate with the desired pattern of adhesive 132 can be used and adhesive 132 can be formed in the desired location using a suitable dispensing technique. As described in more detail later, the pattern of adhesive 132 is based on the shape of the channel to be formed around package assembly 70. Specifically, adhesive 132 is not formed in the prohibited area near the location of the channel.

[0059] exist Figure 9, the package cover 134 is attached to the reinforcement ring 122 and the package component 70. The package cover 134 can be a thermal lid, a heat sink, a water cooling block, etc. The package cover 134 can be formed of a material with high thermal conductivity, such as a metal, such as copper, steel, iron, etc. The package cover 134 can be metallized with a coating such as nickel and / or gold. The package cover 134 protects the package component 70 and forms a thermal path to conduct heat from the package component 70. The package cover 134 has a main portion 134M and a protruding portion 134P. The main portion 134M is disposed above the reinforcement ring 122 and is attached to the reinforcement ring 122 by an adhesive 132. Insert the protruding portion 134P into the opening 126 (see Figure 8 ) and is attached to the package component 70 by the thermal interface material 128. Thus, the protrusion 134P extends through the adhesive 132 and into / through the stiffener ring 122. The width of the protrusion 134P can be less than the width of the package component 70 and less than the width of the opening 126. In this embodiment, the protrusion 134P extends into the thermal interface material 128, but is spaced apart from the package component 70 and does not extend through the thermal interface material 128. In other embodiments (described later with respect to Figure 15-19 134P extends through the thermal interface material 128 to physically contact the package assembly 70. Advantageously, the stiffener ring 122 is not in the thermal path between the package lid 134 and the package assembly 70. The package lid 134 can be attached to the stiffener ring 122 by clamping the package lid 134 with the adhesive 132 at an elevated temperature and curing the adhesive 132.

[0060] Adhesive 132 at least partially fills the area where package lid 134 overlaps stiffener ring 122. Thermal interface material 128 is disposed in area 140 between package lid 134 and package assembly 70, stiffener ring 122, adhesive 120, and adhesive 132. Area 140 includes the remaining portion of opening 126 not occupied by protruding portion 134P of package lid 134 (see FIG. Figure 8 The thermal interface material 128 in region 140 may extend along the top surface of the package component 70, the bottom surface of the protrusion 134P of the package lid 134, the sidewalls of the reinforcement ring 122, and / or the sidewalls of the protrusion 134P of the package lid 134. The thermal interface material 128 in region 140 may also extend along the sidewalls of the adhesive 132.

[0061] The integrated circuit package 100 also includes a channel 142 of thermal interface material 128. At least a portion of the thermal interface material 128 can be disposed in at least a portion of the channel 142. In this embodiment, the channel 142 is a groove in the package cover 134. In another embodiment (subsequently described with reference to FIG. Figure 11-12), the channel 142 is a groove in the reinforcement ring 122. In yet another embodiment (later for Figure 13-14 ), the channel 142 is a groove in the adhesive 132.

[0062] Figure 10 is a top view showing package cover 134 and channel 142 in greater detail, while other features are omitted or shown in phantom for clarity of illustration. Figure 9 It is along Figure 10 1. As shown in cross section AA' of FIG. 1, channel 142 extends from the edge of package assembly 70 to the edge of integrated circuit package 100. Channel 142 is open to the exterior of integrated circuit package 100 and to region 140. Thus, channel 142 connects region 140 to the exterior of integrated circuit package 100. In this embodiment, channel 142 connects the exterior of package lid 134 to region 140. Channel 142 is a groove in main portion 134M of package lid 134 that extends from the outer sidewall of protrusion 134P of package lid 134 to the outer sidewall of main portion 134M.

[0063] The channels 142 extend along at least one side of the package assembly 70 in a top view, and may extend along multiple sides of the package assembly 70 in a top view. In the illustrated embodiment, the channels 142 extend along three sides of the package assembly 70. The number of sides of the package assembly 70 along which the channels 142 extend may be determined based on the amount of thermal interface material 128 expected to flow out of the area 140.

[0064] Return to reference Figure 9 , channel 142 in package lid 134 has a width W1 and a height H1. Width W1 and height H1 can be determined based on the amount of thermal interface material 128 expected to flow out of area 140. Width W1 of channel 142 is less than width W2 of the upper portion of stiffener ring 122. Height H1 of channel 142 is less than height H2 of main portion 134M of package lid 134. In some embodiments, width W1 ranges from 500 μm to 10,000 μm, width W2 ranges from 10,000 μm to 50,000 μm, height H1 ranges from 500 μm to 1,000 μm, and height H2 ranges from 1,000 μm to 3,000 μm.

[0065] Adhesive 132 can be formed on stiffener ring 122 in a pattern based on the shape of channel 142. In embodiments where channel 142 is a groove in package cover 134 or stiffener ring 122, this helps prevent adhesive 132 from squeezing into channel 142. Adhesive 132 can squeeze over / under channel 142 but not into channel 142. Additionally, this allows channel 142 to be defined in embodiments where channel 142 is a groove in adhesive 132.

[0066] As previously mentioned, the thermal interface material 128 may be a liquid metal. During processing or operation of the integrated circuit package 100, the liquid metal may melt and expand due to increased temperature. Figure 9 ), so when the thermal interface material 128 expands, the thermal interface material 128 in the region 140 can flow into the channel 142. In addition, because the channel 142 connects the interior of the integrated circuit package 100 to the exterior of the integrated circuit package 100, the channel 142 can act as a vent to help equalize the pressure within the integrated circuit package 100 during processing or operation. The formation or redistribution of voids in the thermal interface material 128 can be reduced, which can help prevent the thermal interface material 128 from penetrating into undesirable areas of the integrated circuit package 100 (such as the void 124) and can also reduce thermal resistance and increase the coverage of the thermal interface material 128. Increasing the coverage of the thermal interface material 128 can reduce the formation of hot spots. As a result, the reliability and / or performance of the integrated circuit package 100 can be improved.

[0067] Figure 11-12 is a view of an integrated circuit package 100 according to some other embodiments. Figure 11 It is a cross-sectional view. Figure 12 is a top view showing the reinforcement ring 122 and the channel 142 in greater detail, while other features are omitted or shown in phantom for clarity of illustration. Figure 11 It is along Figure 12 Except that the channel 142 is a groove in the reinforcement ring 122, this embodiment is the same as Figure 9-10 Thus, channel 142 connects the exterior of reinforcement ring 122 to region 140 .

[0068] Reference Figure 11 , the channel 142 in the reinforcement ring 122 has a width W3 and a height H3. The width W3 and height H3 can be determined based on the amount of thermal interface material 128 expected to flow out of the area 140. The width W3 of the channel 142 is less than the width W2 of the upper portion of the reinforcement ring 122. The height H3 of the channel 142 is less than the height H4 of the upper portion of the reinforcement ring 122. In some embodiments, the width W2 ranges from 10,000 μm to 50,000 μm, the width W3 ranges from 500 μm to 10,000 μm, the height H3 ranges from 500 μm to 1,000 μm, and the height H4 ranges from 1,000 μm to 3,000 μm.

[0069] Figure 13-14 is a view of an integrated circuit package 100 according to some other embodiments. Figure 13 It is a cross-sectional view. Figure 14is a top view showing adhesive 132 and channel 142 in greater detail, while other features are omitted or shown in phantom for clarity of illustration. Figure 13 It is along Figure 14 Except that the channel 142 is a groove in the adhesive 132, this embodiment is similar to Figure 9-10 Thus, channel 142 connects the exterior of adhesive 132 to region 140.

[0070] Reference Figure 13 , channel 142 in adhesive 132 has a width W5. Width W5 can be determined based on the amount of thermal interface material 128 expected to flow out of area 140. Width W5 of channel 142 is less than width W2 of the upper portion of reinforcement ring 122. In some embodiments, width W2 ranges from 10,000 μm to 50,000 μm, and width W5 ranges from 500 μm to 10,000 μm.

[0071] Figure 15 1 is a view of an integrated circuit package 100 according to some other embodiments. This embodiment is different from FIG. 1 except that the protruding portion 134P of the package lid 134 extends through the thermal interface material 128 to physically contact the package component 70. Figure 9 Specifically, protrusion 134P contacts the top surface of package component 70 , which is the same surface of package component 70 on which thermal interface material 128 is disposed.

[0072] During processing or operation of the integrated circuit package 100, the package component 70 may warp due to increased temperature. The physical contact between the protrusion 134P of the package lid 134 and the package component 70 helps to reduce this warping. Specifically, the protrusion 134P presses against the package component 70 to reduce the amount it may warp. Reducing the warping of the package component 70 can help to avoid the thermal interface material 128 from penetrating into undesirable areas (such as the pores 124) of the integrated circuit package 100. As a result, the bond line thickness (BLT) of the thermal interface material 128 can have increased uniformity. As used herein, "bond line thickness" is the thickness of the thermal interface material 128 above the package component 70.

[0073] In this embodiment, the protrusion 134P of the package lid 134 is annular in a top view (not separately shown). Therefore, a first portion 140A of the region 140 between the package lid 134 and the package component 70 is surrounded by the protrusion 134P, while a second portion 140B of the region 140 between the package lid 134 and the package component 70 is between the protrusion 134P and the stiffener 122. Some thermal interface material 128 is confined within the first portion 140A of the region 140, which can further reduce leakage of the thermal interface material 128.

[0074] The protruding portion 134P of the package cover 134 has a height H5 and a width W6. Figure 9-14 Compared to the embodiment of the present invention, the height H5 of the protrusion 134P, as measured from the top surface of the package assembly 70, is greater than the height H6 of the stiffening ring 122. The width W6 of the protrusion 134P is less than or equal to the width W7 of the opening in the stiffening ring 122. The stiffening ring 122 has a height H7, as measured from the top surface of the package substrate 102. The height H7 of the stiffening ring 122, as measured from the top surface of the package substrate 102, is greater than the height H8 of the package assembly 70. In some embodiments, the height H5 ranges from 1000 μm to 2500 μm, the height H6 ranges from 500 μm to 2000 μm, the height H7 ranges from 1100 μm to 3000 μm, the height H8 ranges from 600 μm to 1000 μm, the width W6 ranges from 300 μm to 3000 μm, and the width W7 ranges from 9000 μm to 59000 μm.

[0075] Figure 16 is a view of an integrated circuit package 100 according to some embodiments. This embodiment is similar to FIG. 1 except that the channel 142 is a groove in the reinforcement ring 122. Figure 15 Thus, channel 142 connects the exterior of reinforcement ring 122 to region 140 .

[0076] Figure 17 is a view of an integrated circuit package 100 according to some embodiments. This embodiment is similar to FIG. 1 except that the channel 142 is a groove in the adhesive 132. Figure 15 Thus, channel 142 connects the exterior of adhesive 132 to region 140.

[0077] Figure 18 is a diagram of an integrated circuit package 100 according to some embodiments. This embodiment is similar to FIG. 1 except that the channel 142 is omitted. Figure 15 The embodiment is similar.

[0078] Figure 19 is a diagram of an integrated circuit package 100 according to some embodiments. This embodiment is similar to FIG. 1 except that the stiffening ring 122 is omitted. Figure 18. In contrast, in addition to the main portion 134M and the protruding portion 134P, the package lid 134 also includes a ring portion 134R. The ring portion 134R is attached to the package substrate 102 and disposed around the package component 70. Thus, the ring portion 134R functions similarly to a stiffener ring. In this embodiment, the adhesive 120 seals the area between the package substrate 102 and the package lid 134 to form an aperture 124.

[0079] Ring portion 134R of package cap 134 has a height H9 measured from the top surface of package substrate 102. Height H5 of protrusion 134P is less than height H9 of ring portion 134R. Furthermore, width W6 of protrusion 134P is less than or equal to width W8 of package assembly 70. In some embodiments, height H9 ranges from 1200 μm to 3100 μm, and width W8 ranges from 10,000 μm to 60,000 μm.

[0080] Embodiments may achieve advantages. Using liquid metal as the thermal interface material 128 within the integrated circuit package 100 may improve heat dissipation of the integrated circuit package 100. Including the channel 142 provides a location into which the thermal interface material 128 may flow at elevated temperatures (e.g., during processing or operation of the integrated circuit package 100). As a result, the thermal interface material 128 may penetrate controlled areas, thereby reducing the risk of the thermal interface material 128 penetrating undesirable areas. Additionally, the formation or redistribution of voids in the thermal interface material 128 may be reduced. Furthermore, the contact between the protruding portion 134P of the package cap 134 and the package component 70 may help reduce warping of the package component 70 at elevated temperatures. Consequently, the reliability and / or performance of the integrated circuit package 100 may be improved.

[0081] In the above-described embodiment, the integrated circuit package 100 includes the package assembly 70 attached to the package substrate 102. However, the integrated circuit package 100 may include any type of integrated circuit device (e.g., an integrated circuit die, a die stack, a package assembly, etc.) attached to the package substrate 102. The package lid 134 is attached to the integrated circuit device.

[0082] Other features and processes may also be included. For example, test structures may be included to assist in verifying the testing of 3D packages or 3DIC devices. The test structures may include, for example, test pads formed in a redistribution layer or on a substrate, which allow the 3D package or 3DIC to be tested using probes and / or probe cards. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with testing methods that incorporate intermediate verification of known-good dies to increase yield and reduce costs.

[0083] In one embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a stiffener ring surrounding the integrated circuit device and attached to the package substrate; a lid attached to the stiffener ring; a channel connected to a region between the lid and the integrated circuit device, the channel extending along at least one side of the integrated circuit device in a top view; and a thermal interface material in the channel and in the region between the lid and the integrated circuit device. In some embodiments of the device, the channel is a groove in the stiffener ring, and the channel connects an exterior portion of the stiffener ring to the region between the lid and the integrated circuit device. In some embodiments of the device, the channel is a groove in the lid, and the channel connects an exterior portion of the lid to the region between the lid and the integrated circuit device. In some embodiments of the device, the device further includes an adhesive attaching the lid to the stiffener ring, the channel being a groove in the adhesive, and the channel connecting an exterior portion of the adhesive to the region between the lid and the integrated circuit device. In some embodiments of the device, the channel extends along multiple sides of the integrated circuit device in a top view. In some embodiments of the device, the thermal interface material is liquid metal. In some embodiments of the device, a main portion of the lid is disposed above the stiffener ring, a protruding portion of the lid extends through the stiffener ring, and the protruding portion is spaced apart from the integrated circuit device. In some embodiments of the device, a main portion of the cover is disposed above the stiffener ring, a protruding portion of the cover extends through the stiffener ring, and the protruding portion physically contacts the integrated circuit device. In some embodiments, the device further includes a passive device attached to the package substrate, the stiffener ring overlapping the passive device.

[0084] In one embodiment, a device includes: a package substrate; an integrated circuit device attached to the package substrate; a thermal interface material on a top surface of the integrated circuit device; and a cover having a main portion on the thermal interface material and a protrusion extending through the thermal interface material, the protrusion surrounding a portion of the thermal interface material, the protrusion physically contacting the top surface of the integrated circuit device. In some embodiments, the device also includes a reinforcement ring surrounding the integrated circuit device and attached to the package substrate, the cover attached to the reinforcement ring. In some embodiments of the device, the ring portion of the cover surrounds the integrated circuit device and is attached to the package substrate. In some embodiments of the device, the thermal interface material is liquid metal. In some embodiments, the device also includes a channel connected to an area between the cover and the integrated circuit device, the thermal interface material being disposed in the channel and in the area between the cover and the integrated circuit device.

[0085] In one embodiment, a method includes attaching an integrated circuit device and a stiffener ring to a package substrate, the stiffener ring being disposed around the integrated circuit device, the integrated circuit device being exposed by an opening in the stiffener ring; forming a thermal interface material in the opening and on the integrated circuit device; forming an adhesive on the stiffener ring in a pattern corresponding to channels in the thermal interface material, the channels extending along at least one side of the integrated circuit device in a top view; and clamping a cover to the adhesive, with a main portion of the cover disposed over the stiffener ring and a protruding portion of the cover extending through the stiffener ring and into the thermal interface material. In some embodiments of the method, the channels are grooves in the stiffener ring. In some embodiments of the method, the channels are grooves in the cover. In some embodiments of the method, the channels are grooves in the adhesive. In some embodiments of the method, forming the thermal interface material includes dispensing liquid metal in the opening. In some embodiments of the method, forming the thermal interface material includes placing a sheet of liquid metal in the opening.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the embodiments of the present invention have been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An integrated circuit package, characterized in that: include: Package substrate; an integrated circuit device attached to the package substrate; a stiffener ring surrounding the integrated circuit device and attached to the package substrate; a cover body attached to the reinforcement ring; a channel connected to a region between the cover and the integrated circuit device, wherein the channel extends along at least one side of the integrated circuit device in a top view; as well as A thermal interface material is provided in the channel and in the region between the cover and the integrated circuit device.

2. The integrated circuit package according to claim 1, wherein: The channel is a groove in the reinforcement ring, and the channel connects the exterior of the reinforcement ring to the area between the cover and the integrated circuit device.

3. The integrated circuit package according to claim 1, wherein: The channel is a groove in the cover, and the channel connects the exterior of the cover to the area between the cover and the integrated circuit device.

4. The integrated circuit package according to claim 1, wherein: Also includes: An adhesive attaches the cover to the stiffener ring, the channel being a groove in the adhesive connecting an exterior of the adhesive to the area between the cover and the integrated circuit device.

5. The integrated circuit package according to claim 1, wherein: In the top view, the channel extends along multiple side surfaces of the integrated circuit device.

6. The integrated circuit package according to claim 1, wherein: The main portion of the cover is disposed above the reinforcement ring, the protruding portion of the cover extends through the reinforcement ring, and the protruding portion is spaced apart from the integrated circuit device or in physical contact with the integrated circuit device.

7. The integrated circuit package according to claim 1, wherein: Also includes: A passive device is attached to the package substrate, and the stiffener ring overlaps the passive device.

8. An integrated circuit package, characterized in that: include: Package substrate; an integrated circuit device attached to the package substrate; a thermal interface material on a top surface of the integrated circuit device; as well as A cover has a main portion on the thermal interface material and a protruding portion extending through the thermal interface material, the protruding portion surrounding a portion of the thermal interface material, the protruding portion physically contacting the top surface of the integrated circuit device.

9. The integrated circuit package according to claim 8, wherein: Also includes: A stiffening ring surrounds the integrated circuit device and is attached to the package substrate, and the cover is attached to the stiffening ring.

10. The integrated circuit package according to claim 8, wherein: The ring portion of the cover surrounds the integrated circuit device and is attached to the package substrate.

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