Power device frame and power device
Patent Information
- Application Number
- CN202422686791.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-04
- Publication Date
- 2025-09-09
- Estimated Expiration
- 2034-11-04
AI Technical Summary
Existing power device products are at risk of delamination failure during the silver plating process, resulting in poor product quality and low pass rate.
The silver-plated area of the power device frame is designed to be 0.5-1.2 times the chip area, and the thickness of the silver-plated area is 2.5um-10um. The area and thickness of the silver-plated area are controlled to ensure that the chip is firmly fixed and reduce the risk of delamination failure.
It significantly reduces the risk of delamination failure of power device products and improves the packaging quality and qualification rate of products.
Smart Images
Figure CN223321269U_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a power device frame and a power device. Background Art
[0002] Power devices are key components used in electronic devices for power conversion and circuit control. They are capable of handling high voltages and large currents. Common power devices include diodes, MOSFETs (metal oxide semiconductor field effect transistors), and IGBTs (insulated gate bipolar transistors).
[0003] Manufacturing a power device requires not only the chip but also a variety of other materials, including a frame plate, adhesives, bonding components, and encapsulation materials, all undergoing numerous meticulous manufacturing processes. The core function of the power device frame is to provide a stable carrier support for the chip and to provide solder pins for reliable circuit connections. Silver plating is applied to the carrier stage of the power device frame to facilitate precise wire bonding in designated areas and further enhance the chip's heat dissipation.
[0004] However, the existing silver plating process is also accompanied by the potential risk of delamination failure of power device products, resulting in poor quality and low pass rate of power device products. Utility Model Content
[0005] The purpose of the embodiments of the present application is to provide a power device frame and a power device, which can reduce the risk of delamination failure of power device products, improve the packaging quality of power devices, and increase the product qualification rate.
[0006] To address the aforementioned technical issues, embodiments of the present application provide a power device frame, comprising a frame plate, a silver-plated area, and a pin area. The frame plate is a conductive and heat-conducting sheet, with a wafer carrier positioned on its front. The silver-plated area is positioned on the wafer carrier to secure the chip, with the area of the silver-plated area being 0.5-1.2 times the chip area. The pin area is positioned on one side of the front of the frame plate.
[0007] An embodiment of the present application further provides a power device, comprising the above-mentioned power device frame and a chip, wherein a bonding component is connected between the chip and the pin area.
[0008] The power device frame and power device provided in the embodiments of the present application greatly reduce the area of the silver-plated area while ensuring that the chip is firmly fixed by designing the area of the silver-plated area to be 0.5-1.2 times the area of the chip, thereby reducing the risk of delamination failure of the power device product, improving the packaging quality of the power device, and increasing the product qualification rate.
[0009] In some embodiments, the length and width of the chip are 3.85 mm*3.85 mm, and the size of the silver-plated area is 3 mm*3 mm.
[0010] In some embodiments, the pin area is provided with a plurality of pins.
[0011] In some embodiments, the silver-plated area is provided with a silver-plated layer, the length and width of the silver-plated layer are the same as those of the silver-plated area, and the thickness of the silver-plated layer is 2.5um-10um.
[0012] In some embodiments, the power device further includes a package body, which covers the front surface of the frame plate, the chip, and the pin area.
[0013] In some embodiments, the package model of the package body is DFN8*8. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.
[0015] Figure 1 This is a schematic diagram of the front structure of an existing power device frame;
[0016] Figure 2 This is a schematic diagram of the power device framework structure provided by some embodiments of the present application;
[0017] Figure 3 This is a schematic diagram of the connection structure of the power device frame bonding component provided in some embodiments of the present application;
[0018] Figure 4 This is a schematic diagram of the side structure of a power device provided by some embodiments of the present application;
[0019] Figure 5 This is an ultrasonic scan of an existing power device frame before pretreatment;
[0020] Figure 6 This is an ultrasonic scan of the existing power device frame after pre-processing;
[0021] Figure 7 This is an ultrasonic scan of a power device frame before pretreatment provided by some embodiments of the present application;
[0022] Figure 8 This is an ultrasonic scan of a power device frame after pre-processing provided in some embodiments of the present application.
[0023] Explanation of the reference numerals: 11 - frame plate; 12 - wafer carrier; 13 - silver-plated area; 14 - pin area; 15 - silver-plated layer; 16 - chip; 17 - pin; 18 - bonding part; 19 - package body. DETAILED DESCRIPTION
[0024] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, each embodiment of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in each embodiment of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present application. The various embodiments can be combined with each other and referenced to each other under the premise of no contradiction.
[0025] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are for the purpose of describing specific embodiments only and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.
[0026] In the description of the embodiments of this application, the technical terms "first" and "second" are used only to distinguish different objects and should not be understood to indicate or imply relative importance or implicitly specify the quantity, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, the meaning of "plurality" is more than two, unless otherwise clearly and specifically defined.
[0027] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, or electrical connections; direct connections, or indirect connections through an intermediate medium; and can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.
[0028] Power devices are key components used in electronic devices for power conversion and circuit control. They are capable of handling high voltages and large currents. Common power devices include diodes, MOSFETs (metal oxide semiconductor field effect transistors), and IGBTs (insulated gate bipolar transistors).
[0029] Manufacturing a power device requires not only the chip but also a variety of other materials, including a frame plate, adhesives, bonding components, and encapsulation materials, all undergoing numerous meticulous manufacturing processes. The core function of the power device frame is to provide a stable carrier support for the chip, and it also features solder pins 17 for reliable circuit connections. Silver plating on the carrier stage of the power device frame facilitates precise wire bonding in designated areas and further enhances the chip's heat dissipation.
[0030] However, the existing silver plating process is also accompanied by the potential risk of delamination failure of power device products, resulting in poor quality and low pass rate of power device products.
[0031] To address the problems of high risk of delamination failure, poor product quality, and low pass rate in existing power device products, some embodiments of the present application provide a power device frame. By designing the silver-plated area to be 0.5-1.2 times the chip area and the thickness of the silver-plated area to be 2.5um-10um, the area of the silver-plated area is greatly reduced while ensuring that the chip is firmly fixed, thereby reducing the risk of delamination failure in power device products and improving the product pass rate.
[0032] The following combination Figures 1 to 8 The power device framework provided by some embodiments of the present application is described.
[0033] The power device frame provided in some embodiments of the present application includes a frame plate 11, a silver-plated area 13, and a pin area 14. The frame plate 11 is a conductive and heat-conducting plate, with a wafer stage 12 disposed on the front of the frame plate 11. The silver-plated area 13 is disposed on the wafer stage 12 and is used to secure a chip 16. The area of the silver-plated area 13 is 0.5-1.2 times the area of the chip 16. The pin area 14 is disposed on one side of the front of the frame plate 11.
[0034] It should be noted that the frame plate 11 provides insulation and heat dissipation functions. It can be single-layer, double-layer, or triple-layer. The three-layer structure separates the mounting, insulation, and heat dissipation functions, with each layer performing different functions, ensuring the stability of the power device frame. The main body of the frame plate 11 can be made of copper, which provides excellent thermal conductivity. The front of the frame plate 11 is the functional area, with a large area in the center serving as the wafer carrier 12. A suitable area on the wafer carrier 12 is suitable for silver plating, known as the silver-plated area 13. The wafer carrier 12 and the silver-plated area 13 provide mechanical support for the chip 16 during the packaging process. After silver plating, the silver-plated area 13 is reflow soldered to secure the chip 16. The specific location of the silver-plated area 13 depends on the size, shape, structure, and function of the chip 16. A pin area 14 is located on one side of the front edge of the frame plate 11. Multiple pins 17 are embedded or mounted therein to transmit signals from the chip 16. The area of the silver-plated area 13 is 0.5-1.2 times the area of the chip 16. In existing power device frames, the dimensions of the wafer stage 12 are 7.2mm*4.35mm, the dimensions of the silver-plated area 13 are 5.38mm*3.35mm, and the dimensions of the chip 16 are 3.85mm*3.85mm. The reduced dimensions of the wafer stage 12 in the power device frame proposed in this application are 7.2mm*4.35mm, the dimensions of the silver-plated area 13 are 3mm*3mm, and the dimensions of the chip 16 are 3.85mm*3.85mm. The provision of this size for the silver-plated area 13 improves the adhesion of the chip 16, enhances the solderability of the bonding element 18, and enhances the heat dissipation function of the chip 16.
[0035] Figure 1 1 is a structural diagram of an existing power device frame. The area surrounded by dotted lines in the figure is the silver-plated area 13 . The size of the silver-plated area 13 occupies a large area of the entire base plate and is also larger than the area of the chip 16 . Figure 2 This is a structural diagram of a power device frame provided by an embodiment of the present application. The black portion in the figure is the silver-plated area 13, and the silver-plated area 13 is greatly reduced.
[0036] Figure 5 and Figure 6 The ultrasonic scanning diagrams before and after the pretreatment of the existing power device frame (the pretreatment process is: first baked at 125℃ for 24h, then baked at 30℃ and 60% relative humidity for 192h, and finally reflowed at 260℃ for 3 times) are shown. By comparing them, it can be clearly seen that the pretreatment Figure 6 The red part after more delamination is shown in the figure, indicating that the delamination failure phenomenon is serious after the chip 16 is welded to the power device frame of the existing structure.
[0037] Figure 7 and Figure 8The ultrasonic scanning diagrams are respectively of the power device frame provided in some embodiments of the present application before and after being pre-treated at 125°C for 24 hours, constant temperature and humidity at 30°C and 60% RH for 192 hours, and 260°C for 3 times (the pre-treatment process is: first baking at 125°C for 24 hours, then baking at 30°C and 60% relative humidity for 192 hours, and finally reflowing at 260°C for 3 times). By comparing, it can be clearly seen that the pre-treatment before and after Figure 7 and Figure 8 The power device frame has hardly changed, the structure is stable and strong, and delamination failure will not occur.
[0038] Tests have shown that when using existing fully silver-plated frame plates, the product's delamination rate is as high as 0.5%. This rate rises sharply to 45.5% after conventional reliability pre-processing. The power device frame provided in this application successfully achieves the goal of zero delamination, significantly improving the product's structural stability and overall quality.
[0039] Some embodiments of the present application provide a power device frame, which reduces the risk of delamination failure of power device products and improves the product qualification rate by designing the area of the silver-plated area 13 to be 0.5-1.2 times the area of the chip 16 and the thickness of the silver-plated area 13 to be 2.5um-10um while ensuring that the chip 16 is firmly fixed. By limiting the area of the silver-plated area 13 and controlling the thickness of the silver-plated layer 15, the product quality rate is improved.
[0040] In some embodiments of the present application, the length and width of the chip 16 are 3.85 mm*3.85 mm, and the size of the silver-plated area 13 is 3 mm*3 mm.
[0041] It should be noted that when the chip 16 is 3.85 mm long and 3.85 mm wide, setting the size of the silver-plated area 13 to 3 mm by 3 mm is a preferred embodiment. In this case, the area of the silver-plated area 13 is 0.6 times the area of the chip 16, which is significantly smaller than the area of the existing silver-plated area 13.
[0042] In some embodiments of the present application, the pin area 14 is provided with a plurality of pins 17 .
[0043] It should be noted that the pin 17 can be a built-in pin 17 flush with the frame plate 11, or a soldered pin 17 led out from the pin area 14. The pin 17 is electrically connected to the chip 16 and plays the role of transmitting the chip 16 signal.
[0044] In some embodiments of the present application, the silver-plated area 13 is provided with a silver-plated layer 15 . The length and width of the silver-plated layer 15 are the same as those of the silver-plated area 13 . The thickness of the silver-plated layer 15 is 2.5 μm-10 μm.
[0045] It should be noted that the silver-plated area 13 is used to secure the chip 16. After a layer of silver is electroplated on the silver-plated area 13, a reflow soldering operation is performed in a soldering device, securing the chip 16 and the frame plate 11 via the silver-plated layer 15. The thickness of the silver-plated layer 15 should be neither too thin nor too thick, as this would result in a weak fixation, while too thick could increase the risk of delamination failure. A suitable thickness for the silver-plated layer 15 has been found to be 2.5 μm to 10 μm.
[0046] Some embodiments of the present application further provide a power device, including the above-mentioned power device frame and a chip 16 , wherein a bonding component 18 is connected between the chip 16 and the pin area 14 .
[0047] It should be noted that if Figure 3 and Figure 4 As shown, chip 16 is fixed to the power device frame. Bonding elements 18 electrically connect chip 16 to pins 17, transmitting signals from chip 16 to external devices via pins 17. The frame board 11, chip 16, pins 17, and bonding elements 18 together form the most basic power device. Bonding elements 18 can take the form of bonding wires, bonding wires, or copper sheet bonding, and transmit signals from chip 16 to pins 17.
[0048] In some embodiments of the present application, the power device further includes a package body 19 , which covers the front surfaces of the frame plate 11 , the chip 16 , and the pin area 14 .
[0049] It should be noted that after the leads of frame plate 11, chip 16, and pin area 14 are connected and fixed according to the designed positions to form a structure with a certain function, the entire structure is packaged to achieve a more stable and aesthetically pleasing overall appearance. The packaged structure is then placed in a packaging mold and poured with epoxy resin to form the appearance of the power device. Pins 17 can extend outside of package body 19, or only one side can be exposed outside of package body 19 to facilitate signal transmission from chip 16.
[0050] In some embodiments of the present application, the package model of the package body 19 is DFN8*8.
[0051] It should be noted that DFN8*8 is a power device package, the full name of which is Dual Flat No-leads, which is a dual-flat no-lead 17 package. This type of package is characterized by a very small footprint and is suitable for installation on printed circuit boards (PCBs). DFN packages are commonly used for semiconductor devices such as integrated circuits (ICs) and transistors. The size of the DFN8*8 package usually refers to the length and width of the package being 8mm*8mm. This package provides good electrical and heat dissipation performance. The DFN package is highly flexible, can effectively improve user production efficiency and significantly reduce application problems caused by manual intervention, and can improve the stability of the user's overall product.
[0052] In addition, the packaging method of power devices includes the following steps:
[0053] (1) Slicing: Using a high-speed rotating dicing blade, the wafer is precisely cut according to the size and layout of the grains in the wafer, aiming to ensure the integrity of the grains and meet the requirements of the subsequent mounting process.
[0054] (2) Mounting: The separated chips 16 dies are placed one by one on the silver-plated area of the power device frame and firmly bonded using silver glue or reflow soldering. The power device frame not only provides an attachment point for the chips 16 dies, but also pre-designed pin areas for extending the circuits of the chips 16 dies, laying the foundation for subsequent operations.
[0055] (3) Bonding: One end of the bonding element 18 is connected to the die of chip 16, and the other end is connected to the pin 17 of the power device frame, in order to establish an electrical connection between the die of chip 16 and the external circuit. Specifically, this step uses a bonding wire or bonding wire to connect the contact point on the die of chip 16 to the internal pin 17 on the power device frame, thereby enabling the external transmission of the internal circuit signal of the die of chip 16.
[0056] (4) Packaging: By using epoxy molding compound, high temperature and high pressure are applied to the corresponding mold, and the power device components to be packaged are placed in the mold to achieve effective packaging processing of the bonded products.
[0057] (5) Printing: Fonts are printed on the front and back of the package. The main purpose is to clearly mark the product's specifications, manufacturer and other key information.
[0058] (6) Cutting: Divide the overall frame board into independent product units to form power device products.
[0059] (7) Appearance inspection: After completing the packaging process, a comprehensive appearance inspection of the product is carried out to ensure product quality.
[0060] Those skilled in the art will appreciate that the above-mentioned embodiments are specific examples for implementing the present application, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.
Claims
1. A power device frame, characterized in that: include: The frame plate is a conductive and heat-conducting mounting plate, and a wafer stage is provided on the front of the frame plate; A silver-plated area is provided on the wafer stage and is used to fix the chip. The area of the silver-plated area is 0.5-1.2 times the area of the chip. The pin area is arranged on one side of the front surface of the frame plate.
2. The power device frame according to claim 1, characterized in that: The length and width of the chip are 3.85mm*3.85mm, and the size of the silver-plated area is 3mm*3mm.
3. The power device frame according to claim 1, characterized in that: The pin area is provided with a plurality of pins.
4. The power device frame according to claim 1, wherein: The silver-plated area is provided with a silver-plated layer, the length and width of the silver-plated layer are the same as those of the silver-plated area, and the thickness of the silver-plated layer is 2.5um-10um.
5. A power device, characterized in that: It comprises the power device frame according to any one of claims 1 to 4 and the chip, wherein a bonding component is connected between the chip and the pin area.
6. The power device according to claim 5, characterized in that The invention also includes a package body, which covers the front surface of the frame plate, the chip, and the pin area.
7. The power device according to claim 6, characterized in that: The package model of the package body is DFN8*8.