Package structure

Abstract

The utility model provides a packaging structure. The packaging structure comprises a chip assembly; the adapter plate stacking structure is arranged on one side of the chip assembly in the first direction perpendicular to the main surface of the chip assembly and is electrically connected with the chip assembly, the adapter plate stacking structure comprises a plurality of adapter plates which are stacked in the first direction, and the adapter plates are electrically connected with the chip assembly. The plurality of pinboards are electrically connected to each other and have sidewalls aligned in the first direction, wherein each pinboard includes a capacitor assembly having one or more capacitors. According to the packaging structure, the total capacitance of the packaging structure can be greatly improved through the arrangement of the adapter plate stacking structure, and then the power supply integrity and the signal integrity are improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor packaging technology, and in particular to a packaging structure. Background Art

[0002] Chip on Wafer on Substrate (CoWoS) packaging is an advanced packaging technology that enables high-density interconnection of multiple chips and high-speed data transmission. In the power distribution network of packaging structures like CoWoS, fluctuating currents can generate power noise due to impedance in the electrical paths, adversely affecting power integrity and signal integrity. Optimizing power and signal integrity in packaging structures is a key research topic. Utility Model Content

[0003] According to at least one embodiment of the present disclosure, a packaging structure is provided, comprising: a chip component; and an adapter plate stacking structure, which is arranged on one side of the chip component in a first direction perpendicular to the main surface of the chip component and is electrically connected to the chip component, wherein the adapter plate stacking structure includes a plurality of adapter plates stacked in the first direction, the plurality of adapter plates are electrically connected to each other and have side walls aligned in the first direction, wherein each adapter plate includes a capacitor component having one or more capacitors.

[0004] In the packaging structure provided according to at least one embodiment of the present disclosure, the multiple capacitors in the multiple adapter boards are connected in parallel.

[0005] In the packaging structure provided according to at least one embodiment of the present disclosure, two adjacent transfer boards among the plurality of transfer boards are bonded to each other via a bonding structure to be electrically connected.

[0006] In the packaging structure provided according to at least one embodiment of the present disclosure, the bonding structure includes a hybrid bonding structure.

[0007] In the packaging structure provided according to at least one embodiment of the present disclosure, the adapter plate stacking structure includes: a first adapter plate, including a first substrate, a first capacitor component and a first bonding layer, the first capacitor component is embedded in the first substrate; and a second adapter plate, located on a side of the first adapter plate away from the chip component, and including a second substrate, a second capacitor component and a second bonding layer, the second capacitor component is embedded in the second substrate, the first bonding layer and the second bonding layer are bonded to each other and together constitute a bonding structure located between the first substrate and the second substrate, and the bonding structure includes a bonding dielectric portion and a bonding conductive portion embedded in the bonding dielectric portion.

[0008] In the packaging structure provided according to at least one embodiment of the present disclosure, the first adapter plate further includes: a chip interconnection structure, located on a side of the first substrate close to the chip component, and electrically connected to the chip component and the first capacitor component; and a first substrate through-hole, embedded in the first substrate, and electrically connected to the chip interconnection structure and the bonding conductive portion; the second adapter plate further includes: a capacitor interconnection structure, located between the second substrate and the bonding structure, and electrically connected to the second capacitor component and the bonding conductive portion; and a second substrate through-hole, embedded in the second substrate, and electrically connected to the capacitor interconnection structure.

[0009] In the packaging structure provided according to at least one embodiment of the present disclosure, the chip assembly includes multiple chips, and the multiple chips are interconnected with each other through the chip interconnection structure, the first capacitor assembly and the second capacitor assembly are connected to each other through the chip interconnection structure, the first substrate through-hole, the bonding conductive portion and the capacitor interconnection structure, and are connected to the chip assembly.

[0010] In the packaging structure provided according to at least one embodiment of the present disclosure, the number of capacitors of the second capacitor assembly that can be accommodated in the second adapter board is greater than the number of capacitors of the first capacitor assembly that can be accommodated in the first adapter board.

[0011] In the packaging structure provided according to at least one embodiment of the present disclosure, the first capacitor component includes a plurality of first capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the second capacitor component includes a plurality of second capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the number of the plurality of second capacitors is greater than the number of the plurality of first capacitors.

[0012] In the packaging structure provided according to at least one embodiment of the present disclosure, the first capacitor component and the second capacitor component at least partially overlap in the first direction.

[0013] In the packaging structure provided according to at least one embodiment of the present disclosure, the first capacitor component and the second capacitor component each include a deep trench capacitor.

[0014] In the packaging structure provided according to at least one embodiment of the present disclosure, the orthographic projection of the chip component on a reference plane parallel to the main surface of the chip component is located within the orthographic projection of each adapter board in the adapter board stacking structure on the reference plane, and the area of ​​the orthographic projection of each adapter board is larger than the area of ​​the orthographic projection of the chip component.

[0015] In the packaging structure provided according to at least one embodiment of the present disclosure, the orthographic projection areas of the plurality of adapter plates in the adapter plate stacking structure on the reference plane are equal to each other.

[0016] The packaging structure provided according to at least one embodiment of the present disclosure further includes: an encapsulation layer, which is arranged on the adapter plate stacking structure and encapsulates the chip component, wherein the side walls of the encapsulation layer are aligned with the side walls of the multiple adapter plates in the adapter plate stacking structure in the first direction.

[0017] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a first conductive terminal, which is arranged on a side of the adapter board stacking structure away from the chip component; a packaging substrate, which is arranged on a side of the first conductive terminal away from the adapter board stacking structure and is electrically connected to the adapter board stacking structure through the first conductive terminal; and a second conductive terminal, which is arranged on a side of the packaging substrate away from the adapter board stacking structure and is electrically connected to the packaging substrate.

[0018] The packaging structure provided according to at least one embodiment of the present disclosure further includes: a bottom filling layer, which at least fills the gap between the adapter plate stacking structure and the packaging substrate and surrounds the first conductive terminal.

[0019] In the packaging structure provided according to at least one embodiment of the present disclosure, the bottom filling layer further covers side walls of one or more adapter boards in the adapter board stacking structure.

[0020] The packaging structure provided according to the embodiment of the present disclosure can significantly increase its total capacitance by providing the adapter board stacking structure, thereby improving power integrity and signal integrity. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0022] Figure 1 A schematic cross-sectional view illustrating a package structure according to some embodiments of the present disclosure is shown.

[0023] Figure 2 A schematic cross-sectional view illustrating a stacked structure of interposers in a packaging structure according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0024] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0026] Capacitors can be added to a package to reduce the capacitive reactance and impedance of the electrical paths in the power distribution network, thereby reducing power noise and improving power integrity and signal integrity. Capacitor capacitance is inversely proportional to capacitive reactance, so increasing the overall capacitance of the capacitors in the package can help improve both power integrity and signal integrity.

[0027] The CoWoS package generally includes a package substrate and a chip on wafer (CoW) package consisting of a chip component and an adapter plate. The adapter plate is arranged between the chip component and the package substrate in a direction perpendicular to the main surface of the chip component and is electrically connected to the chip component and the package substrate. Capacitors may be provided in the adapter plate, for example, deep trench capacitors (DTC); capacitors may also be provided on the package substrate, for example, ceramic capacitors; the provision of these capacitors may help solve the power integrity and signal integrity problems of the chip component. Compared with the capacitors provided on the package substrate, the capacitors embedded in the adapter plate are closer to the chip component, and therefore can be more conducive to improving the power integrity and signal integrity of the chip component. That is, increasing the total capacitance of the capacitors in the adapter plate can enable the chip component of the package structure to have excellent power integrity and signal integrity.

[0028] For example, the overall capacitance of the adapter board can be increased by increasing the depth and structure of the DTC grooves. However, due to the limited dimensions of the adapter board (e.g., horizontal area, substrate thickness, etc.), the number of capacitors that can be installed in a single adapter board is limited, and the capacitance that can be increased by optimizing the groove depth and structure is limited. In other words, the total capacitance of the DTC in the adapter board is limited, making it difficult to increase the total capacitance of the package structure.

[0029] For example, the total capacitance of the package structure may be increased by increasing the number of capacitors on the package substrate, but this may increase the overall size of the package structure in the horizontal direction, which is not conducive to the miniaturization of the package structure.

[0030] To address the above issues, the embodiments of the present disclosure provide a packaging structure that can significantly increase the total capacitance of the adapter board assembly, thereby significantly reducing power supply noise, and thus enabling the chip assembly in the packaging structure to have excellent power integrity and signal integrity.

[0031] For example, the packaging structure of an embodiment of the present disclosure includes a chip component; and an adapter plate stacking structure, which is arranged on one side of the chip component in a first direction perpendicular to the main surface of the chip component and is electrically connected to the chip component, wherein the adapter plate stacking structure includes a plurality of adapter plates stacked in the first direction, the plurality of adapter plates are electrically connected to each other and have side walls aligned in the first direction, wherein each adapter plate includes a capacitor component having one or more capacitors.

[0032] In the packaging structure of the embodiment of the present disclosure, by setting up an adapter plate stacking structure including multiple stacked adapter plates, and each adapter plate includes a capacitor component, the limitation of the capacitance of a single adapter plate can be broken, thereby greatly improving the overall capacitor number and total capacitance of the adapter plate stacking structure, thereby greatly reducing power supply noise and optimizing the power integrity and signal integrity in the packaging structure.

[0033] Figure 1 shows a schematic cross-sectional view of a package structure according to some embodiments of the present disclosure, Figure 2 A schematic cross-sectional view of a stacked structure of transfer plates according to some embodiments of the present disclosure is shown, and is for example Figure 1 The schematic enlarged cross-sectional view of region A of the transfer board stacking structure in the package structure shown. It should be understood that Figure 1 Some incomplete components in region A (for example, part of the first conductive terminal 110 located at the edge of region A) are not Figure 2 Specifically shown in .

[0034] refer to Figure 1 and Figure 2In some embodiments, the package structure 500 includes an adapter plate stacking structure 100 and a chip assembly 200. The adapter plate stacking structure 100 is arranged on one side of the chip assembly 200 in a first direction D1 perpendicular to the main surface of the chip assembly and is electrically connected to the chip assembly 200. In some embodiments, the adapter plate stacking structure 100 includes a plurality of adapter plates stacked in the first direction D1, for example, including a first adapter plate 100a and a second adapter plate 100b; the plurality of adapter plates are electrically connected to each other, and each adapter plate includes a capacitor assembly having one or more capacitors. For example, the first adapter plate 100a may include a first capacitor assembly having one or more first capacitors C1; the second adapter plate 100b may include a second capacitor assembly having one or more second capacitors C2. It should be understood that the number of adapter plates included in the adapter plate stacking structure shown in the figure and the number of capacitors included in each adapter plate are for illustrative purposes only, and the present disclosure is not limited thereto. Corresponding configurations and adjustments can be made according to product design and requirements.

[0035] In some embodiments, the plurality of interposers in the interposer stack structure 100 have sidewalls that are substantially aligned in the first direction D1. For example, the dimensions (e.g., width, area, etc.) of the plurality of interposers in a direction parallel to the main surface of the chip assembly (e.g., a horizontal direction including the second direction D2) may be substantially the same.

[0036] In some embodiments, multiple capacitors in multiple adapter plates are connected in parallel. For example, one or more first capacitors C1 of the first adapter plate 100a and one or more second capacitors C2 of the second adapter plate 100b are connected in parallel, thereby increasing the total capacitance of the adapter plate stack structure 100.

[0037] In some embodiments, two adjacent adapter plates in the plurality of adapter plates are electrically connected by bonding to each other via a bonding structure. For example, the bonding structure includes a hybrid bonding structure. For example, the first adapter plate 300a and the second adapter plate 300b are electrically connected by bonding to each other via the bonding structure 30.

[0038] In some embodiments, each of the plurality of adapter plates includes a substrate, a capacitor component embedded in the substrate, and a bonding layer, and adjacent adapter plates are bonded to each other and electrically connected via corresponding bonding layers. The top adapter plate closest to the chip component among the plurality of adapter plates may be provided with a chip interconnect structure for providing interconnection between the plurality of chips in the chip component, and the other adapter plates located on the side of the top adapter plate away from the chip component among the plurality of adapter plates may each be provided with a capacitor interconnect structure for providing connection between the plurality of capacitors in their capacitor components.

[0039] For example, the adapter plate stacking structure includes a first adapter plate and a second adapter plate; the first adapter plate includes a first substrate, a first capacitor component and a first bonding layer, and the first capacitor component is embedded in the first substrate; the second adapter plate is located on the side of the first adapter plate away from the chip component, and includes a second substrate, a second capacitor component and a second bonding layer, and the second capacitor component is embedded in the second substrate; the first bonding layer and the second bonding layer are bonded to each other and together constitute a bonding structure located between the first substrate and the second substrate, and the bonding structure includes a bonding dielectric part and a bonding conductive part embedded in the bonding dielectric part.

[0040] For example, the first adapter plate further includes: a chip interconnect structure, located on a side of the first substrate adjacent to the chip assembly, and electrically connected to the chip assembly and the first capacitor assembly; and a first substrate through-hole, embedded in the first substrate, and electrically connected to the chip interconnect structure and the bonding conductive portion. The second adapter plate further includes: a capacitor interconnect structure, located between the second substrate and the bonding structure, and electrically connected to the second capacitor assembly and the bonding conductive portion; and a second substrate through-hole, embedded in the second substrate, and electrically connected to the capacitor interconnect structure.

[0041] refer to Figure 1 and Figure 2 For example, the first riser board 100a and the second riser board 100b are stacked and adjacent to each other in the first direction D1, and the second riser board 100b is located on a side of the first riser board 100a away from the chip assembly 200. For example, the first riser board 100a may be the one closest to the chip assembly 200 among the multiple riser boards in the riser board stack structure 100 and may also be referred to as the top riser board.

[0042] For example, the first transfer board 100a includes a first substrate 10, a first capacitor component, a first substrate through-hole 11, a chip interconnect structure 15, and a first bonding layer 18. The first capacitor component and the first substrate through-hole 11 are embedded in the first substrate 10, and the chip interconnect structure 15 and the first bonding layer 18 are located on opposite sides of the first substrate 10 in the first direction D1.

[0043] The first capacitor component may include one or more first capacitors C1. For example, a plurality of first capacitors C1 may be arranged side by side in a direction parallel to the main surface of the first substrate (for example, a horizontal direction including the second direction D2). In some embodiments, the first capacitor component may include a deep trench capacitor. For example, a deep trench is provided in the first substrate 10, and the first capacitor C1 may include a first electrode layer, an inter-electrode dielectric layer, and a second electrode layer, at least part of the first electrode layer, the electrode layer dielectric layer, and the second electrode layer are located in the deep trench, and in some embodiments may further have a portion located on the top surface of the first substrate 10; the first electrode layer and the second electrode layer may be electrically connected to corresponding conductive lines in the chip interconnect structure 15, respectively. It should be understood that for the sake of simplicity of the figure, the specific structure of each electrode layer and the inter-electrode dielectric layer in the first capacitor C1 is not specifically shown in the figure.

[0044] The first through-substrate via 11 extends through the first substrate 10 in a first direction D1, that is, from a side surface of the first substrate 10 proximate to the chip assembly to a side surface of the first substrate 10 proximate to the second interposer, and can be electrically connected to the chip interconnect structure 15 and the conductive components in the first bonding layer 18. For example, the first through-substrate via 11 and one or more first capacitors C1 are arranged side by side and spaced apart in a direction parallel to the main surface of the substrate.

[0045] For example, the chip interconnection structure 15 is arranged on a side of the first substrate 10 close to the chip component 200, and is electrically connected to the chip component 200, the first capacitor component and the first substrate through-hole 11. For example, the chip interconnection structure 15 may include a first dielectric structure 12 and a first conductive structure 13, at least a portion of the first conductive structure 13 is embedded in the first dielectric structure 12, and is electrically connected to the chip component 200, the first capacitor C1 and the first substrate through-hole 11. The first conductive structure 13 may include one or more layers of conductive wires and / or conductive through-holes (not shown). For example, the chip component 200 may include multiple chips, and the chip interconnection structure 15 may provide interconnection between the multiple chips, interconnection between the multiple first capacitors C1, connection between the multiple chips and the multiple first capacitors, and connection between the chips and the first capacitors and the first substrate through-hole.

[0046] The first bonding layer 18 is located on a side of the first substrate 10 away from the chip assembly and may include a first bonding dielectric layer 16 and a first bonding pad 17. The first bonding pad 17 is embedded in the first bonding dielectric layer 16 and is electrically connected to the first substrate through-hole 11. For example, a plurality of first substrate through-holes 11 may be provided in a one-to-one correspondence with a plurality of first bonding pads 17. In some embodiments, the surface of the plurality of first bonding pads 17 away from the first substrate 10 may be substantially flush with the surface of the first bonding dielectric layer 16 away from the first substrate 10 in a direction parallel to the main surface of the first substrate, so as to facilitate bonding with the second transfer board.

[0047] Continue to refer Figure 1 and Figure 2 In some embodiments, the second interposer 100b includes a second substrate 20, a second capacitor component, a second substrate through-hole 21, a capacitor interconnect structure 25, and a second bonding layer 28. The second capacitor component and the second substrate through-hole 21 are embedded in the second substrate 20, the capacitor interconnect structure 25 and the second bonding layer 28 are located on a side of the second substrate 20 close to the first interposer 100a, and the capacitor interconnect structure 25 is located between the second bonding layer 28 and the second substrate 20.

[0048] The second capacitor component may include one or more second capacitors C2; for example, a plurality of second capacitors C2 may be arranged side by side in a direction parallel to the main surface of the substrate (for example, a horizontal direction including the second direction D2). In some embodiments, the second capacitor component may include a deep trench capacitor. For example, a deep trench is provided in the second substrate 20, and the second capacitor C2 may include a first electrode layer, an inter-electrode dielectric layer and a second electrode layer, at least part of the first electrode layer, the electrode layer dielectric layer and the second electrode layer are located in the deep trench, and may also have a portion located on the top surface of the second substrate 20; the first electrode layer and the second electrode layer may be electrically connected to the corresponding conductive lines in the capacitor interconnect structure 25, respectively. It should be understood that for the sake of simplicity of the figure, the specific structure of each electrode layer and the inter-electrode dielectric layer in the second capacitor C2 is not specifically shown in the figure.

[0049] The second through-substrate via 21 extends through the second substrate 20 in the first direction D1, i.e., from a side surface of the second substrate 20 proximal to the first interposer to a side surface of the second substrate 20 distal to the first interposer, and can be electrically connected to the capacitor interconnect structure. For example, the second through-substrate via 21 can be spaced side by side with one or more second capacitors of the second capacitor assembly in a direction parallel to the substrate's main surface.

[0050] The capacitor interconnect structure 25 is provided on one side of the second substrate 20 close to the first adapter plate 100 and is electrically connected to the second capacitor component. For example, the capacitor interconnect structure 25 may include a second dielectric structure 22 and a second conductive structure 23, the second conductive structure 23 being embedded in the second dielectric structure 22 and electrically connected to the second capacitor component and the second substrate through-hole 21. The second conductive structure 23 may include one or more layers of conductive wires and / or conductive vias (not shown). For example, the second capacitor component 23 includes a plurality of second capacitors C2, and the plurality of second capacitors C2 can be electrically connected to each other through the capacitor interconnect structure 25, for example, connected in parallel with each other.

[0051] The second bonding layer 28 is located on a side of the second substrate 20 and the capacitor interconnect structure 25 that is close to the first interposer 100a and may include a second bonding dielectric layer 26 and a second bonding pad 27. The second bonding pad 27 is embedded in the second bonding dielectric layer 26 and is electrically connected to the second conductive structure 23 in the capacitor interconnect structure 25. For example, a plurality of second bonding pads 27 may be provided in a one-to-one correspondence with a plurality of first bonding pads 17. In some embodiments, the surface of the plurality of second bonding pads 27 away from the second substrate 20 may be substantially flush with the surface of the second bonding dielectric layer 26 away from the second substrate 20 in a direction parallel to the main surface of the substrate to facilitate bonding with the first interposer.

[0052] For example, the first bonding layer 18 of the first adapter plate 100a and the second bonding layer 28 of the second adapter plate 100b are arranged facing each other and bonded to each other to jointly form a bonding structure 30 located between the first substrate 10 and the second substrate 20. For example, the bonding structure 30 can be a hybrid bonding structure and can include a metal-metal bonding interface and a dielectric-dielectric bonding interface. For example, the first bonding dielectric layer 16 and the second bonding dielectric layer 26 are bonded to each other and jointly form a bonding dielectric portion 30a, and a dielectric-dielectric bonding interface is formed therebetween; the first bonding pad 17 and the second bonding pad 27 are bonded to each other and electrically connected, and jointly form a bonding conductive portion 30b, and a metal-metal bonding interface is formed therebetween. That is, the bonding structure 30 includes a bonding dielectric portion 30a and a bonding conductive portion 30b. The bonding conductive portion 30b is embedded in the bonding dielectric portion 30a and is electrically connected to the first substrate through-hole 11 and the second conductive structure 23 of the capacitor interconnect structure 25, and is electrically connected to the second substrate through-hole 21 through the second conductive structure 23.

[0053] In some embodiments, the first substrate 10 and the second substrate 20 may each be a semiconductor substrate, which may be or include a silicon substrate, or may also include other semiconductor materials such as germanium. The first dielectric structure 12, the second dielectric structure 22, the first bonding dielectric layer 16, and the second bonding dielectric layer 26 may each include a suitable dielectric material, such as an inorganic dielectric material such as silicon oxide or silicon nitride. The first conductive structure 13, the second conductive structure 23, the first bonding pad 17, the second bonding pad 27, the first through-substrate via 11, and the second through-substrate via 21 may each include a conductive material such as metal, such as copper, titanium, or tungsten.

[0054] In one embodiment, the chip assembly includes multiple chips, and the multiple chips are interconnected with each other through the chip interconnection structure. The first capacitor assembly and the second capacitor assembly are connected to each other and to the chip assembly through the chip interconnection structure, the first substrate through-hole, the bonding conductive portion and the capacitor interconnection structure.

[0055] In some embodiments, the number of capacitors of the second capacitor assembly that can be accommodated in the second adapter plate is greater than the number of capacitors of the first capacitor assembly that can be accommodated in the first adapter plate.

[0056] In some embodiments, the first capacitor component includes a plurality of first capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the second capacitor component includes a plurality of second capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the number of the plurality of second capacitors is greater than the number of the plurality of first capacitors.

[0057] In some embodiments, the first capacitive component and the second capacitive component at least partially overlap in the first direction.

[0058] refer to Figure 1 and Figure 2 Chip assembly 200 may include one or more chips, or may be or include a chiplet module. For example, chip assembly 200 may include a first chip 201, a second chip 202, and a third chip 203. It should be understood that the number of chips shown in the figure is for illustration only, and the number and type of chips included in chip assembly 200 may be selected based on product requirements.

[0059] For example, the chips in the chip assembly 200 may be selected from one or more of a system on chip (SoC), a digital signal processor (DSP), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), a memory chip such as a high bandwidth memory chip (HBM), a central processing unit (CPU), a tensor processing unit (TPU), a neural network processing unit (NPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), and a general-purpose computing on graphics processing unit (GPGPU). For example, in some examples, the first chip 201 may be an SoC, and at least one of the second chip 202 and the second chip 203 may be an HBM, but the present disclosure is not limited thereto.

[0060] In some embodiments, the multiple chips in the chip assembly 200 are interconnected with each other via a chip interconnect structure 15 and are electrically connected to the first capacitor assembly via the chip interconnect structure 15. For example, the multiple first capacitors C1 of the first capacitor assembly may also be electrically connected to each other via the chip interconnect structure 15, for example, connected in parallel.

[0061] In some embodiments, the capacitor interconnect structure 25 provides an electrical connection between the second capacitor component and the bonding conductive portion, and when the second capacitor component includes multiple second capacitors, provides an electrical connection between the multiple second capacitors (e.g., in parallel). For example, the multiple first capacitors C1 and second capacitors C2 of the first capacitor component and the second capacitor component can be electrically connected to each other through the chip interconnect structure 15, the first substrate through-via 11, the bonding conductive portion 30b, and the capacitor interconnect structure 25, for example, in parallel with each other and electrically connected to the chip component 200.

[0062] In some embodiments, the interconnections between the multiple chips in the chip assembly 200 that require interconnection through the interposer stack structure 100 can all be provided by the chip interconnect structure 15, and the capacitor interconnect structure 25 is primarily used to provide interconnections between the multiple second capacitors C2, and may not provide interconnections between the multiple chips in the chip assembly. In some embodiments, disposing the conductive traces used to interconnect the multiple chips in the chip assembly in the interposer stack structure within the chip interconnect structure 15 of the top interposer can minimize the connection paths between the multiple chips, thereby reducing signal loss.

[0063] In some embodiments, the number of conductive line layers of the first conductive structure 13 of the chip interconnect structure 15 may be greater than the number of conductive line layers of the second conductive structure 13 of the capacitor interconnect structure 25; and / or the number or density of lines in the chip interconnect structure 15 may be greater than the number or density of lines in the capacitor interconnect structure 25.

[0064] In some embodiments, part of the first capacitor (for example, part of the electrode plate) is located on a side of the first substrate 10 away from the second adapter plate, and can be arranged in the same layer as part of the conductive circuit in the first conductive structure 13; part of the second capacitor (for example, part of the electrode plate) is located on a side of the second substrate 20 close to the first electrode plate, and can be arranged in the same layer as the conductive circuit in the second conductive structure 13. In some embodiments, since the number or density of circuits in the first conductive structure 13 may be greater than the number or density of circuits in the second conductive structure 23, for example, it may be inconvenient to set capacitors at the upper part of the first substrate 10 where the density of circuits is greater; therefore, the space in which capacitors can be set in the second substrate 20 is relatively larger than the space in which capacitors can be set in the first substrate. For example, under the same area, the number of capacitors of the second capacitor component that can be accommodated in the second adapter plate 100b is greater than the number of capacitors of the first capacitor component that can be accommodated in the first adapter plate 100a.

[0065] In some embodiments, the capacitors required for the adapter plate stacking structure can be first set in the first adapter plate. When the number of capacitors in the first capacitor assembly reaches the upper limit of the number of capacitors that the first adapter plate can accommodate, other required capacitors are set in other adapter plates such as the second adapter plate, and the multiple capacitors of the multiple adapter plates are made to reach the required total capacitance. It should be understood that the number of adapter plates in the adapter plate stacking structure can be set according to the required total capacitance. For example, one or more other adapter plates can be further bonded to the side of the second adapter plate away from the first adapter plate to further increase the total capacitance of the adapter plate stacking structure; wherein every two adjacent adapter plates can be bonded to each other through a bonding structure and connected, and the specific bonding method is similar to the bonding method of the first adapter plate and the second adapter plate mentioned above, and will not be repeated here.

[0066] In some embodiments, as Figure 1 and Figure 2As shown, the number of second capacitors C2 included in the second capacitor assembly in the second riser board 100b can be greater than the number of first capacitors C1 included in the first capacitor assembly in the first riser board 100a. However, in other examples, the number of second capacitors C2 in the second riser board 100b can also be less than or equal to the number of first capacitors C1 in the first riser board 100a.

[0067] In some embodiments, as Figure 1 and Figure 2 As shown, the first capacitor component and the second capacitor component may at least partially overlap in the first direction D1. For example, one or more of the plurality of first capacitors C1 may overlap with one or more of the plurality of second capacitors C2 in the first direction D1. Overlapping the capacitor components of multiple adapter plates can help optimize circuit layout. In this article, overlapping multiple components in a certain direction means that the orthographic projections of the multiple components on a reference plane perpendicular to the direction overlap.

[0068] In some embodiments, a method for forming an adapter plate stacking structure 100 may include bonding a plurality of adapter plate wafers to each other to form a wafer stacking structure, and then performing a cutting process on the wafer stacking structure to form a plurality of independent adapter plate stacking structures. For example, a first adapter plate wafer and a second adapter plate wafer are provided, wherein each wafer includes a plurality of device regions and a cutting region, the plurality of device regions are spaced apart by the cutting region, and each device region is formed with an adapter plate; that is, the first adapter plate wafer includes a plurality of first adapter plates respectively located in the plurality of device regions, and the second adapter plate wafer includes a plurality of second adapter plates respectively located in the plurality of device regions; the first adapter plate wafer and the second adapter plate wafer are aligned and bonded to each other to form a wafer stacking structure, wherein the wafer stacking structure includes a plurality of adapter plate stacking structures, each adapter plate stacking structure including a first adapter plate and a second adapter plate bonded to each other; and a cutting process is performed on the wafer stacking structure along the cutting region to cut the plurality of adapter plate stacking structures apart, thereby forming an adapter plate stacking structure. In this way, in the formed adapter plate stacking structure, the side walls of the multiple adapter plates are roughly aligned with each other in the first direction D1, and the dimensions (for example, width, area, etc.) of the multiple adapter plates in the direction parallel to the main surface of the adapter plate (for example, the horizontal direction including the second direction D2) can be roughly equal to each other.

[0069] For example, the side walls of the first adapter plate 100a and the side walls of the second adapter plate 100b are roughly aligned in the first direction D1; specifically, the side walls of the first substrate 10, the chip interconnection structure 15 and the first bonding layer 18 of the first adapter plate 100a and the side walls of the second substrate 20, the capacitor interconnection structure 25 and the second bonding layer 28 of the second adapter plate 100b are roughly aligned with each other in the first direction D1.

[0070] In some embodiments, the orthographic projection of the chip assembly on a reference plane parallel to a major surface of the chip assembly is located within the orthographic projection of each adapter board in the adapter board stack structure on the reference plane, and the orthographic projection of each adapter board has an area greater than the orthographic projection of the chip assembly. In some embodiments, the orthographic projection areas of multiple adapter boards in the adapter board stack structure on the reference plane are equal.

[0071] For example, the orthographic projection of the chip assembly 200 on a reference plane parallel to a major surface of the chip assembly (e.g., a major surface of the package substrate 300 described below) is located within the orthographic projection of each interposer (e.g., the first interposer 100a or the second interposer 100b) in the interposer stack 100 on the reference plane, and the area of ​​the orthographic projection of each interposer is greater than the area of ​​the orthographic projection of the chip assembly 200. For example, the orthographic projection of the first interposer 100a on the reference plane and the orthographic projection of the second interposer 100b on the reference plane overlap with each other, e.g., may substantially coincide with each other. The area of ​​the orthographic projection of the first interposer 100a may be substantially equal to the area of ​​the orthographic projection of the second interposer 100b.

[0072] In some embodiments, the packaging structure further includes: an encapsulation layer disposed on the adapter plate stacking structure and encapsulating the chip component, wherein a sidewall of the encapsulation layer is aligned with the sidewall of the adapter plate stacking structure in the first direction.

[0073] In some embodiments, the packaging structure also includes: a first conductive terminal, arranged on a side of the adapter board stacking structure away from the chip component; a packaging substrate, arranged on a side of the first conductive terminal away from the adapter board stacking structure, and electrically connected to the adapter board stacking structure through the first conductive terminal; and a second conductive terminal, arranged on a side of the packaging substrate away from the adapter board stacking structure, and electrically connected to the packaging substrate.

[0074] In some embodiments, the package structure further includes an underfill layer that fills at least a gap between the interposer stack and the package substrate and surrounds the first conductive terminal. For example, the underfill layer also covers sidewalls of one or more interposers in the interposer stack.

[0075] refer to Figure 1For example, the chip assembly 200 is electrically connected to the interposer stack structure 100 via the conductive connector 205. The package structure 500 may further include an underfill layer 206 to fill the space between the chip assembly 200 and the interposer stack structure 100 and surround the conductive connector 205 in a direction parallel to the main surface of the chip assembly. In some embodiments, an encapsulation layer 207 is disposed on the interposer stack structure 100 to encapsulate the chip assembly 200 and the underfill layer 206. The encapsulation layer 207 may include a molding compound, such as an epoxy molding compound (EMC).

[0076] For example, the encapsulation layer 207 may encapsulate the sidewalls of the chip assembly 200 and the underfill layer 206, and the surface of the encapsulation layer 207 away from the interposer stack structure 100 may be substantially flush with the surface of the chip assembly 200 away from the interposer stack structure 100 in a direction parallel to the main surface of the chip assembly. In other examples, the encapsulation layer 207 may further encapsulate the surface of the chip assembly 200 away from the interposer stack structure 100.

[0077] In some embodiments, sidewalls of the encapsulation layer 207 may be substantially aligned with sidewalls of the interposer stack structure 100 (ie, sidewalls of the first interposer and the second interposer, etc.) in the first direction D1.

[0078] Continue to refer Figure 1 In some embodiments, the package substrate 500 further includes a first conductive terminal 110, a package substrate 300 and a second conductive terminal 310. Figure 1 and Figure 2 As shown, the first conductive terminal 110 is disposed on a side of the interposer stack 100 away from the chip assembly 200 and is electrically connected to the interposer stack 100. For example, it can be electrically connected to the substrate through-hole of the interposer farthest from the chip assembly in the interposer stack 100 (i.e., the bottom-most interposer shown in the figure). For example, the first conductive terminal 110 can be or include a conductive material such as metal and / or solder; for example, the first conductive terminal 110 can be or include a controlled collapsed chip connection (C4) bump.

[0079] For example, Figure 1 and Figure 2As shown, first conductive terminal 110 is electrically connected to second through-substrate via 21, and is electrically connected to chip assembly 200, first capacitor assembly, and second capacitor assembly via second through-substrate via 21, capacitor interconnect structure 25, bonding conductive portion 30b, first through-substrate via 11, and chip interconnect structure 15. In some embodiments, chip assembly 200, interposer stack structure 100, underfill layer 206, encapsulation layer 207, and first conductive terminal 110 collectively constitute a chip-on-wafer (CoW) package.

[0080] In some embodiments, the chip-on-wafer package is further disposed on a packaging substrate 300 and can be electrically connected to the packaging substrate 300 via the first conductive terminals 110. The chip-on-wafer package and the packaging substrate 300 together constitute a chip-on-wafer-on-substrate (CoWoS) package. For example, the chip-on-wafer package is flip-chip disposed on the packaging substrate 300, and the CoWoS package can also be referred to as a flip chip ball grid array (FCBGA) package.

[0081] For example, the packaging substrate 300 is disposed on a side of the first conductive terminal 110 away from the adapter plate stacking structure 100 , and is electrically connected to the adapter plate stacking structure 100 through the first conductive terminal 110 , and further electrically connected to the chip assembly 200 through the adapter plate stacking structure 110 .

[0082] In some embodiments, the package structure 500 further includes an underfill layer 120. The underfill layer 120 may at least fill the gap between the interposer stack 100 and the package substrate 300 and surround the first conductive terminal 110 in a direction parallel to the main surface of the package substrate. In some embodiments, the underfill layer 120 may also extend to cover the sidewalls of the CoW package. For example, the underfill layer 120 may also cover the sidewalls of one or more interposers in the interposer stack 100. The underfill layer may include, for example, an organic dielectric material such as epoxy resin.

[0083] In some embodiments, the second conductive terminal 310 is disposed on a side of the package substrate 300 away from the interposer stack structure 100 and is electrically connected to the package substrate 300 and electrically connected to the CoW package through the package substrate 300. The second conductive terminal 310 may include a conductive material such as metal and / or solder; for example, the second conductive terminal 310 may be or include a ball grid array (BGA). The second conductive terminal 310 may serve as an external connection point for the package structure 500; for example, the package structure 500 may be further connected to other package components, such as a printed circuit board (PCB), via the second conductive terminal 310.

[0084] refer to Figure 1 In some embodiments, the package structure 500 may further include a reinforcement structure 302, and the reinforcement structure 302 and the CoW package are disposed on the same side of the package substrate 300. For example, the reinforcement structure 302 is disposed on the edge of the package substrate 300 and may be attached to the package substrate 300 via an adhesive layer 301. The CoW package may be located in an area surrounded by the reinforcement structure 302 in a direction parallel to the main surface of the package substrate. The reinforcement structure 302 may be beneficial in controlling and reducing the warping of the package substrate and the overall package structure. In some embodiments, the reinforcement structure 302 may be a reinforcement ring; in an alternative embodiment, the reinforcement structure 302 may also be a reinforcement cover, that is, it may also include a cover portion located on the side of the chip assembly 200 away from the adapter plate stacking structure.

[0085] In some embodiments, additional capacitors 303 can be selectively provided on the package substrate based on product requirements. Additional capacitors 303 can be, for example, ceramic capacitors. For example, in some embodiments, in addition to providing multiple capacitor components within the multiple adapter plates of the adapter plate stack, additional capacitors can also be provided on the package substrate 300. In other embodiments, additional capacitors can be omitted, which can help reduce the overall size of the package structure. Figure 1 The additional capacitor 303 is shown in dashed lines, indicating that the additional capacitor may be optionally disposed on the package substrate and may be omitted in some examples.

[0086] In the disclosed embodiment, since the interposer stack structure includes a plurality of stacked interposers, and each interposer is provided with a capacitor component to increase the overall capacitance of the interposer stack structure and the package structure, the number of additional capacitors on the package substrate 300 can be reduced, or even omitted. This can help reduce the overall size of the package structure in a direction parallel to the main surface of the package substrate (i.e., the horizontal direction shown in the figure).

[0087] In the embodiments of the present disclosure, by stacking multiple adapter plates, the capacitance limitations of a single adapter plate can be overcome, thereby significantly increasing the total capacitance of the adapter plate stack structure. For example, the total capacitance of the adapter plate stack structure can be increased by two times or more compared to that of a conventional adapter plate, thereby significantly reducing power supply noise and improving the power integrity and signal integrity of the chip assembly and packaging structure. Moreover, the multiple adapter plates are stacked in a direction perpendicular to the main surface of the chip assembly (i.e., the vertical direction shown in the figure), and thus substantially do not occupy additional horizontal space. That is, the adapter plate stack structure can overcome the capacitance limitations within a plane and significantly increase the total capacitance of the adapter plate stack structure without increasing the horizontal area.

[0088] In addition, since the adapter board stacking structure has an increased total capacitance, the additional capacitance on the packaging structure can be reduced or omitted, which can help reduce the overall size of the packaging structure, or the packaging area saved by reducing or omitting the additional capacitance can be used to set up components with other functions.

[0089] There are a few points to note:

[0090] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0091] (2) Unless there is any conflict, the features of the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0092] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A packaging structure, characterized in that: include: Chip components; as well as an adapter plate stacking structure, arranged on one side of the chip assembly in a first direction perpendicular to the main surface of the chip assembly and electrically connected to the chip assembly, wherein the adapter plate stacking structure includes a plurality of adapter plates stacked in the first direction, the plurality of adapter plates being electrically connected to each other and having side walls aligned in the first direction, Each adapter board includes a capacitor component having one or more capacitors.

2. The packaging structure according to claim 1, wherein: The plurality of capacitors in the plurality of adapter plates are connected in parallel.

3. The packaging structure according to claim 1, wherein: Two adjacent transfer boards among the plurality of transfer boards are bonded to each other through a bonding structure to be electrically connected.

4. The packaging structure according to claim 3, wherein: The bonding structure includes a hybrid bonding structure.

5. The packaging structure according to claim 1, wherein: The adapter plate stacking structure includes: a first transfer board, comprising a first substrate, a first capacitor component and a first bonding layer, wherein the first capacitor component is embedded in the first substrate; and The second adapter plate is located on a side of the first adapter plate away from the chip assembly and includes a second substrate, a second capacitor assembly and a second bonding layer, wherein the second capacitor assembly is embedded in the second substrate. The first bonding layer and the second bonding layer are bonded to each other and together constitute a bonding structure located between the first substrate and the second substrate, and the bonding structure includes a bonding dielectric portion and a bonding conductive portion embedded in the bonding dielectric portion.

6. The packaging structure according to claim 5, wherein: The first adapter plate further includes: a chip interconnect structure located on a side of the first substrate adjacent to the chip assembly and electrically connected to the chip assembly and the first capacitor assembly; and a first substrate through-hole embedded in the first substrate and electrically connected to the chip interconnect structure and the bonding conductive portion; The second adapter plate also includes: a capacitor interconnect structure located between the second substrate and the bonding structure and electrically connected to the second capacitor component and the bonding conductive portion; and a second substrate through-hole embedded in the second substrate and electrically connected to the capacitor interconnect structure.

7. The packaging structure according to claim 6, wherein: The chip assembly includes multiple chips, and the multiple chips are interconnected with each other through the chip interconnection structure. The first capacitor assembly and the second capacitor assembly are connected to each other and to the chip assembly through the chip interconnection structure, the first substrate through-hole, the bonding conductive portion and the capacitor interconnection structure.

8. The packaging structure according to any one of claims 5 to 7, characterized in that: The number of capacitors of the second capacitor assembly that can be accommodated in the second adapter plate is greater than the number of capacitors of the first capacitor assembly that can be accommodated in the first adapter plate.

9. The packaging structure according to any one of claims 5 to 7, characterized in that: The first capacitor component includes a plurality of first capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the second capacitor component includes a plurality of second capacitors arranged side by side in a second direction parallel to the main surface of the chip component, and the number of the plurality of second capacitors is greater than the number of the plurality of first capacitors.

10. The packaging structure according to any one of claims 5 to 7, characterized in that: The first capacitor component and the second capacitor component at least partially overlap in the first direction.

11. The packaging structure according to any one of claims 5 to 7, characterized in that: The first capacitor component and the second capacitor component each include a deep trench capacitor.

12. The packaging structure according to any one of claims 1 to 7, wherein: The orthographic projection of the chip component on a reference plane parallel to the main surface of the chip component is located within the orthographic projection of each adapter board in the adapter board stacking structure on the reference plane, and the area of ​​the orthographic projection of each adapter board is larger than the area of ​​the orthographic projection of the chip component.

13. The packaging structure according to claim 12, wherein: The orthographic projection areas of the plurality of adapter plates in the adapter plate stacking structure on the reference plane are equal to each other.

14. The packaging structure according to any one of claims 1 to 7, wherein: The packaging structure further includes: An encapsulation layer is disposed on the adapter plate stack structure and encapsulates the chip component. The sidewalls of the encapsulation layer are aligned with the sidewalls of the plurality of adapter plates in the adapter plate stacking structure in the first direction.

15. The packaging structure according to any one of claims 1 to 7, characterized in that: The packaging structure further includes: A first conductive terminal is provided on a side of the transfer board stack structure away from the chip assembly; a packaging substrate, disposed on a side of the first conductive terminal away from the transfer board stack structure, and electrically connected to the transfer board stack structure through the first conductive terminal; and The second conductive terminal is disposed on a side of the packaging substrate away from the transfer board stacking structure and is electrically connected to the packaging substrate.

16. The packaging structure according to claim 15, wherein: The packaging structure further includes: The bottom filling layer at least fills the gap between the transfer board stack structure and the packaging substrate and surrounds the first conductive terminal.

17. The packaging structure according to claim 16, wherein: The bottom filling layer also covers the sidewalls of one or more interposers in the interposer stack structure.

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