Display substrate and display device

Abstract

At least one embodiment of the utility model provides a display substrate and a display device. The display substrate comprises a substrate; the pixel driving circuit and the light-emitting elements are arranged on the substrate; the pixel driving circuit comprises a first conductive metal layer, a first insulating layer and a second conductive metal layer, and the second conductive metal layer comprises an initialization signal connecting line, an anode connecting electrode and a power supply voltage signal line which are arranged in the first direction. The initialization signal connecting line, the anode connecting electrode and the power supply voltage signal line extend along a second direction intersected with the first direction, and the anode connecting electrode is electrically connected with the second conductive metal layer through a first via hole structure arranged in the first insulating layer; the multiple light-emitting elements comprise the first light-emitting element, the first light-emitting element comprises the first anode, the orthographic projection of the first anode on the substrate and the orthographic projection of the first via hole structure on the substrate are not overlapped, the display substrate can improve the flatness of the anodes, and the risk of anode collapse is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] With the continuous development of display technology, consumers are increasingly demanding narrow-border designs for display devices. Therefore, how to further reduce the width of display device borders has become a key research focus and hot topic for researchers in the display field. Compared with traditional liquid crystal display devices, organic light-emitting diodes (OLEDs), which are commonly used in narrow-border designs, have been widely used in the display technology field due to their advantages such as lightness, high brightness, low power consumption, fast response, high clarity, good flexibility, and high luminous efficiency. They are widely used in electronic devices such as mobile phones and tablets.

[0003] An OLED display panel comprises a substrate, a pixel driver circuit, and a light-emitting element. The pixel driver circuit includes a conductive metal layer, which can be a multi-layer structure. An insulating layer is provided between the different conductive metal layers of the pixel driver circuit, and between the pixel driver circuit and the anode of the light-emitting element. This insulating layer provides insulation and flattening, improving the surface flatness of the pixel driver circuit. Utility Model Content

[0004] At least one embodiment of the present disclosure provides a display substrate and a display device, which includes: a base substrate; a pixel driving circuit and a plurality of light-emitting elements on the base substrate; the pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer, the second conductive metal layer includes an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged in a first direction, the initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extend along a second direction intersecting with the first direction, and the anode connection electrode is electrically connected to the second conductive metal layer through a first via structure provided in the first insulating layer; the plurality of light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, the orthographic projection of the first anode on the base substrate and the orthographic projection of the first via structure on the base substrate do not overlap, and the orthographic projection of the first anode on the base substrate and the orthographic projection of the first via structure on the base substrate in the display substrate do not overlap, so that the anode does not need to cover the corresponding via structure, thereby improving the flatness of the first anode surface, thereby reducing the color deviation difference of the display panel, and reducing the risk of anode collapse.

[0005] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a pixel driving circuit on the base substrate, and a plurality of light-emitting elements located on a side of the pixel driving circuit away from the base substrate; the pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer arranged in a stacked manner, the second conductive metal layer includes an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged in a first direction, the initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extend along a second direction intersecting with the first direction, the anode connection electrode is electrically connected to the second conductive metal layer through a first via structure provided in the first insulating layer; the plurality of light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and the orthographic projection of the first anode on the base substrate and the orthographic projection of the first via structure on the base substrate do not overlap.

[0006] For example, in the display substrate provided in at least one embodiment of the present disclosure, the plurality of light-emitting elements include a second light-emitting element, the second light-emitting element includes a second anode, and the orthographic projection of the second anode on the base substrate partially overlaps with the orthographic projection of the first via structure on the base substrate.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the overlapping area of ​​the orthographic projection of the second anode on the base substrate and the orthographic projection of the first via structure on the base substrate is 0% to 20% of the area of ​​the first via structure.

[0008] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a third gate metal layer arranged on a side of the first conductive metal layer away from the second conductive metal layer, wherein the first conductive metal layer includes a first data fan-out line extending along the first direction, and the second conductive metal layer includes a second data fan-out line extending along the second direction; the third gate metal layer includes a third initialization signal line extending along the first direction; the orthographic projection of the first data fan-out line on the base substrate and the orthographic projection of the third initialization signal line on the base substrate overlap.

[0009] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a first gate metal layer arranged on a side of the third gate metal layer away from the first conductive metal layer, wherein the first gate metal layer includes a first initialization signal line extending along the first direction, and the third gate metal layer also includes a second initialization signal line spaced apart from the third initialization signal line and extending along the second direction, and the orthographic projection of the first data fan-out line on the base substrate and the orthographic projections of the first initialization signal line and the second initialization signal line on the base substrate are spaced apart from each other.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first conductive metal layer includes a first initialization signal transfer line and a second initialization signal transfer line; the initialization signal connection line is electrically connected to the first initialization signal transfer line through a second via structure provided in the first insulating layer, and is electrically connected to the second initialization signal transfer line through another second via structure provided in the first insulating layer.

[0011] For example, in the display substrate provided in at least one embodiment of the present disclosure, in the second direction, the second via structure and the first via structure are respectively arranged on both sides of the first data fan-out line.

[0012] For example, in the display substrate provided in at least one embodiment of the present disclosure, the initialization signal connection line and the first initialization signal line are electrically connected through the first initialization signal adapter line, the initialization signal connection line and the second initialization signal line are electrically connected through the second initialization signal adapter line, and the initialization signal connection line and the third initialization signal line are electrically connected to each form a mesh initialization signal structure.

[0013] For example, in the display substrate provided in at least one embodiment of the present disclosure, the second conductive metal layer further includes a data signal line extending in the second direction, and the second data fan-out line is arranged between two adjacent data signal lines.

[0014] For example, in the display substrate provided in at least one embodiment of the present disclosure, two adjacent initialization signal connection lines, two adjacent anode connection electrodes, two adjacent power supply voltage signal lines and two adjacent data signal lines are all axially symmetrical about the second data fan-out line.

[0015] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first gate metal layer also includes a first reset control signal line, and the positive projection of the first data fan-out line on the base substrate, the positive projection of the third initialization signal line on the base substrate and the first reset control signal line overlap.

[0016] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a second gate metal layer arranged between the third gate metal layer and the first gate metal layer, wherein the second gate metal layer includes a second plate of the storage capacitor extending in the first direction, a first shielding line and a second shielding line, and the orthographic projections of the second plate of the storage capacitor, the first shielding line and the second shielding line on the base substrate are spaced apart from the orthographic projection of the first data fan-out line on the base substrate.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the third gate metal layer also includes a third scanning signal line and a first scanning signal line arranged on a side of the third initialization signal line close to the second initialization signal line, the orthographic projection of the third scanning signal line on the base substrate and the orthographic projection of the second shielding line on the base substrate overlap, and the orthographic projection of the first scanning signal line on the base substrate and the orthographic projection of the first shielding line on the base substrate overlap.

[0018] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a seventh transistor and an eighth transistor, the first electrode of the eighth transistor is connected to the third initialization signal line, the second electrode of the eighth transistor is connected to the first electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initialization signal line, and the second electrode of the seventh transistor is connected to the first electrode of the first light-emitting element; the display substrate also includes: a first active layer, located between the base substrate and the first gate metal layer, the first active layer includes a seventh active portion and an eighth active portion, the seventh active portion is used to form a channel region of the seventh transistor, and the eighth active portion is used to form a channel region of the eighth transistor; the orthographic projection of the first reset control signal line on the base substrate covers the orthographic projection of the eighth active portion on the base substrate and the orthographic projection of the seventh active portion on the base substrate, a partial structure of the first reset control signal line is used to form the gate of the seventh transistor, and a partial structure of the first reset control signal line is used to form the gate of the eighth transistor.

[0019] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit further includes a fourth transistor and a sixth transistor, the first electrode of the fourth transistor is connected to the data signal line, and the second electrode of the fourth transistor is electrically connected to the second electrode of the eighth transistor; the first electrode of the sixth transistor is electrically connected to the second electrode of the seventh transistor; the first active layer further includes a third active portion, a fourth active portion and a sixth active portion, the third active portion is configured to form a channel region of the driving transistor, the fourth active portion is connected to the eighth active portion, and the sixth active portion is connected to the seventh active portion.

[0020] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a second transistor, the first electrode of the first transistor is connected to the first initialization signal line, the second electrode of the first transistor is connected to the second electrode of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, and the second electrode of the second transistor is connected to the second electrode of the driving transistor; the display substrate further includes a second active layer between the first active layer and the third gate metal layer, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

[0021] For example, in the display substrate provided in at least one embodiment of the present disclosure, the pixel driving circuit further includes a first transistor, a second transistor and a ninth transistor, the first electrode of the first transistor being connected to the first initialization signal line, the second electrode of the first transistor being connected to the second electrode of the ninth transistor, the first electrode of the second transistor being connected to the second electrode of the driving transistor, and the second electrode of the second transistor being connected to the second electrode of the ninth transistor; the display substrate further includes a second active layer between the first active layer and the third gate metal layer, the second active layer including a first active portion and a second active portion, the first active portion being used to form a channel region of the first transistor, and the second active portion being used to form a channel region of the second transistor.

[0022] At least one embodiment of the present disclosure further provides a display device, which includes any of the display substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0024] Figure 1A schematic diagram of a planar structure of a display substrate provided in at least one embodiment of the present disclosure;

[0025] Figure 2 A schematic cross-sectional structure diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0026] Figure 3 A schematic diagram of an equivalent circuit of a pixel driving circuit provided in at least one embodiment of the present disclosure;

[0027] Figure 4 for Figure 3 A driving timing diagram of the pixel driving circuit shown;

[0028] Figure 5 for Figure 3 Another driving timing diagram of the pixel driving circuit shown;

[0029] Figure 6 A schematic diagram of an equivalent circuit of another pixel driving circuit provided by at least one embodiment of the present disclosure;

[0030] Figure 7 A schematic diagram of the planar structure of a light-shielding layer in a display substrate provided by at least one embodiment of the present disclosure;

[0031] Figure 8 A schematic diagram of the planar structure of a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0032] Figure 9 A schematic planar structure diagram of a stack of a light shielding layer and a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 10 A schematic diagram of the planar structure of a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0034] Figure 11 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0035] Figure 12 A schematic diagram of the planar structure of a second gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0036] Figure 13 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0037] Figure 14A schematic diagram of the planar structure of a second semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0038] Figure 15 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0039] Figure 16 A schematic diagram of the planar structure of a third gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0040] Figure 17 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0041] Figure 18 A schematic planar structural diagram of an interlayer insulating layer of a display substrate provided by at least one embodiment of the present disclosure;

[0042] Figure 19 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure;

[0043] Figure 20 A schematic diagram of a planar structure of an etching stop layer in a display substrate provided by at least one embodiment of the present disclosure;

[0044] Figure 21 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etching stop layer in a display substrate provided by at least one embodiment of the present disclosure;

[0045] Figure 22 A schematic diagram of the planar structure of a first conductive metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0046] Figure 23 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, and a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 24 A schematic diagram of the planar structure of a passivation layer in a display substrate provided by at least one embodiment of the present disclosure;

[0048] Figure 25 A schematic diagram of the planar structure of a first planarization layer in a display substrate provided by at least one embodiment of the present disclosure;

[0049] Figure 26 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate provided by at least one embodiment of the present disclosure;

[0050] Figure 27 A schematic diagram of the planar structure of a second conductive metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0051] Figure 28 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0052] Figure 29 A schematic diagram of the planar structure of a second planarization layer in a display substrate provided by at least one embodiment of the present disclosure;

[0053] Figure 30 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0054] Figure 31 A schematic diagram of the planar structure of an anode layer in a display substrate provided by at least one embodiment of the present disclosure;

[0055] Figure 32 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0056] Figure 33 A schematic diagram of an equivalent circuit of another pixel driving circuit provided in at least one embodiment of the present disclosure;

[0057] Figure 34 for Figure 33 The driving timing diagram of the pixel driving circuit shown;

[0058] Figure 35 A schematic diagram of the planar structure of a light-shielding layer in a display substrate provided by at least one embodiment of the present disclosure;

[0059] Figure 36 A schematic diagram of the planar structure of a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0060] Figure 37 A schematic planar structure diagram of a stack of a light shielding layer and a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0061] Figure 38 A schematic diagram of the planar structure of a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0062] Figure 39 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0063] Figure 40 A schematic diagram of the planar structure of a second gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0064] Figure 41 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0065] Figure 42 A schematic diagram of the planar structure of a second semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure;

[0066] Figure 43 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0067] Figure 44 A schematic diagram of the planar structure of a third gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0068] Figure 45 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate provided by at least one embodiment of the present disclosure;

[0069] Figure 46 A schematic planar structural diagram of an interlayer insulating layer of a display substrate provided by at least one embodiment of the present disclosure;

[0070] Figure 47 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure;

[0071] Figure 48 A schematic diagram of a planar structure of an etching stop layer in a display substrate provided by at least one embodiment of the present disclosure;

[0072] Figure 49 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etching stop layer in a display substrate provided in at least one embodiment of the present disclosure;

[0073] Figure 50 A schematic planar structural diagram of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0074] Figure 51 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, and a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0075] Figure 52 A schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure;

[0076] Figure 53 A schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0077] Figure 54 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0078] Figure 55 A schematic diagram of the planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0079] Figure 56A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0080] Figure 57 A schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0081] Figure 58 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0082] Figure 59 A schematic diagram of the planar structure of an anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0083] Figure 60 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarizing layer, a second conductive metal layer, a second planarizing layer, and an anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0084] Figure 61 An equivalent circuit diagram of another pixel driving circuit provided in at least one embodiment of the present disclosure;

[0085] Figure 62 A schematic diagram of a planar structure of a light shielding layer in a display substrate provided in at least one embodiment of the present disclosure;

[0086] Figure 63 A schematic diagram of a planar structure of a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0087] Figure 64 A schematic planar structure diagram of a stack of a light-shielding layer and a first semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0088] Figure 65 A schematic planar structural diagram of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0089] Figure 66A schematic planar structural diagram of a stack of a light-shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0090] Figure 67 A schematic planar structural diagram of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0091] Figure 68 A schematic planar structural diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0092] Figure 69 A schematic diagram of the planar structure of a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0093] Figure 70 A schematic planar structural diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0094] Figure 71 A schematic planar structural diagram of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0095] Figure 72 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0096] Figure 73 A schematic diagram of a planar structure of an interlayer insulating layer of a display substrate provided in at least one embodiment of the present disclosure;

[0097] Figure 74 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure;

[0098] Figure 75 A schematic diagram of a planar structure of an etching stop layer in a display substrate provided in at least one embodiment of the present disclosure;

[0099] Figure 76 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etching stop layer in a display substrate provided in at least one embodiment of the present disclosure;

[0100] Figure 77 A schematic planar structural diagram of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0101] Figure 78 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, and a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0102] Figure 79 A schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure;

[0103] Figure 80 A schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0104] Figure 81 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0105] Figure 82 A schematic diagram of the planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0106] Figure 83 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure;

[0107] Figure 84 A schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0108] Figure 85 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure;

[0109] Figure 86 A schematic diagram of the planar structure of an anode layer in a display substrate provided in at least one embodiment of the present disclosure;

[0110] Figure 87 A schematic planar structure diagram of a stack of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer, and an anode layer in a display substrate provided for at least one embodiment of the present disclosure; and

[0111] Figure 88 A block diagram of a display device provided in accordance with at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0112] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0113] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0114] Unless otherwise defined, the features such as “parallel”, “perpendicular” and “same” used in the embodiments of the present invention include the cases of “parallel”, “perpendicular” and “same” in a strict sense, as well as the cases of “approximately parallel”, “approximately perpendicular” and “approximately the same” that contain a certain error. For example, the above-mentioned “approximately” may mean that the difference between the compared objects is within 10% or 5% of the average value of the compared objects. When the number of a component or element is not specifically indicated below in the embodiments of the present invention, it means that the component or element may be one or more, or may be understood as at least one. “At least one” means one or more, and “multiple” means at least two. The “same-layer arrangement” in the embodiments of the present invention refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The “same layer” here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0115] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0116] In the drawings of the embodiments of the present disclosure, the thickness of the layers and the area of ​​the regions are exaggerated in order to more clearly describe the layer structures in the display substrate and the display device. Therefore, it is conceivable that changes in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances do not affect the essential characteristics of the display substrate and the display device. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown in the embodiments of the present disclosure, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Therefore, the areas shown in the drawings of the embodiments of the present disclosure are schematic in nature, and their shapes are not intended to illustrate the actual shape of an area of ​​a device or apparatus, and are not intended to limit the scope of the exemplary embodiments.

[0117] For example, in pixel driving circuits, Low Temperature Polycrystalline + Oxide (LTPO) technology, which uses both low-temperature polysilicon transistors and oxide transistors, can be applied to organic light-emitting diode display panels. This LTPO technology can reduce the power consumption of the display panel. The power consumption of a display panel includes driving power and luminous power. Display panels based on LTPO technology have lower driving power than display panels based on LTPS technology. Display panels based on LTPS technology require 60 Hz when displaying still images, but display panels based on LTPO technology can reduce this to 1 Hz when displaying still images, thereby significantly reducing driving power.

[0118] For example, based on LTPO technology, some transistors in display panels are oxide transistors (e.g., N-type oxide transistors). Oxide transistors have lower leakage current, allowing the voltage (charge) on the capacitor to be maintained for one second, thus achieving a 1Hz refresh rate. LTPS transistors have higher leakage current, requiring 60Hz to drive even static pixels; otherwise, brightness would be significantly reduced. Therefore, LTPO technology has been widely used in display substrates.

[0119] The conductive metal layer of the pixel driving circuit may include a multi-layer structure, such as a 2SD structure or a 3SD structure. The 2SD structure includes a first conductive metal layer (SD1 layer) and a second conductive metal layer (SD2 layer), and the SD1 layer and the SD2 layer are stacked in sequence in a direction away from the substrate. The SD1 layer can serve as the source and drain of each transistor in the pixel driving circuit, and the first data fan-out line (FIP1) extending in the row direction. Signal lines such as data signal lines, power supply voltage signal lines, and second data fan-out lines (FIP2) extending in the column direction can be arranged in the SD2 layer. This is only an example, and the embodiments of the present application are not limited to this.

[0120] For example, an insulating layer can be provided between the SD1 layer and the SD2 layer, and the insulating layer can play the role of insulation and flattening. A via structure can be provided on the insulating layer, and the SD1 layer and the SD2 layer can be electrically connected through the via structure. Due to the dense wiring of the OLED display panel, a large number of via structures will be provided in the insulating layer between adjacent conductive metal layers, and the via structure is used to connect the conductive metal layers on both sides thereof. The inventors of the present disclosure have noticed that some light-emitting elements have a via structure on one side of the anode and no via structure on the other side, that is, the position of the via structure is asymmetrical, which causes the anode to tilt toward the side with the via structure, so that the anode collapses, causing the anode as a whole to tilt toward the collapsed side, thereby affecting the flatness of the anode, and further causing the color deviation difference of the display panel to increase and the display effect to deteriorate.

[0121] The inventors of the present disclosure also noted that in the FIP (Fanout In Panel) narrow-frame technology, a 2SD FIP or 3SD FIP process is used. FIP technology can integrate the edge wiring area of ​​the display panel into the display area, greatly reducing the area of ​​the non-display area and achieving an extremely narrow frame, such as a frame of about 1 mm. The display area of ​​the display panel includes a fan-out area and a normal display area outside the fan-out area. Data fan-out lines are provided in the fan-out area. In FIP products with two conductive metal layers, the FIP horizontal traces are located in the first conductive metal layer, and the FIP vertical traces are located in the second conductive metal layer. As the resolution of the display panel increases, the FIP horizontal traces will overlap with the GOA (Gate on Array) signal lines. If DC signal shielding is required for overlap, for pixel circuits using new low-temperature polysilicon transistors and oxide transistors (LTPO) technology, as well as currently mass-produced LTPO pixel circuits, at high resolution, the FIP lateral routing is routed between the source and drain of the first transistor T1 or between the source and drain of the seventh transistor T7 and the eighth transistor T8, so that adjacent initialization signal lines can be used for shielding to meet current design requirements.

[0122] At least one embodiment of the present disclosure provides a display substrate, which includes: a base substrate; a pixel driving circuit on the base substrate, and a plurality of light-emitting elements located on a side of the pixel driving circuit away from the base substrate; the pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer stacked together, the second conductive metal layer includes an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged in sequence in a first direction, the initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extend along a second direction intersecting with the first direction, and the anode connection electrode is electrically connected to the first conductive layer through a first via structure provided in the first insulating layer; the plurality of light-emitting elements includes a first light-emitting element, the first light-emitting element includes a first anode, the orthographic projection of the first anode on the base substrate and the orthographic projection of the first via structure on the base substrate do not overlap, so that the anode does not need to cover the corresponding via structure, thereby improving the flatness of the surface of the first anode to reduce the color deviation difference of the display panel.

[0123] For example, in the embodiments of the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode and the source electrode, and current can flow through the drain electrode, the channel region, and the source electrode. It should be noted that in the embodiments of the present disclosure, the channel region refers to the region through which current mainly flows.

[0124] For example, in the embodiments of the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be reversed.

[0125] For example, in the embodiments of the present disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the reception of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having various functions.

[0126] For example, Figure 1 This is a schematic diagram of a planar structure of a display substrate provided by at least one embodiment of the present disclosure. Figure 1 As shown, the display area of ​​the display substrate may include a plurality of pixel units P arranged in a matrix, each pixel unit P including a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel includes a circuit unit and a light-emitting unit. The circuit unit includes at least a pixel driving circuit, which is respectively connected to a scan signal line, a data signal line, and a light-emitting control signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting control signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit includes a light-emitting element, which is connected to the pixel driving circuit of the sub-pixel in which it is located. The light-emitting element is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0127] For example, in at least one embodiment of the present disclosure, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 and the fourth subpixel P4 may be green subpixels (G) that emit green light, and the third subpixel P3 may be a blue subpixel (B) that emits blue light. In exemplary embodiments, the subpixels may be rectangular, rhombus, pentagonal, hexagonal, or diamond-shaped, and the first subpixel P1, second subpixel P2, third subpixel P3, and fourth subpixel P4 may be arranged horizontally, vertically, or in a square, etc., although this is not limited in the present disclosure.

[0128] For example, in another embodiment of the present disclosure, each pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or triangular pattern, which is not limited in the embodiment of the present disclosure.

[0129] For example, Figure 2 A schematic cross-sectional view of a display substrate according to at least one embodiment of the present disclosure is shown. Figure 2 As shown, the display substrate 100 includes a base substrate 101, which is divided into a display area and a peripheral area surrounding the display area. Figure 2 The cross-sectional structure diagram shown in FIG shows the structure of four sub-pixels in the display area. Figure 2 As shown, on a plane perpendicular to the display substrate, the display substrate 100 may include a driving circuit layer 102 disposed on a base substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the base substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the base substrate 101. For example, in other embodiments, the display substrate may further include other film layers, such as a touch structure layer, etc., which is not limited in the embodiments of the present disclosure.

[0130] For example, in an embodiment of the present disclosure, the peripheral region includes a lead region and a binding region. The lead region includes a plurality of leads, and the binding region is used to bind to an external driver circuit or driver chip. In this case, the plurality of leads can be electrically connected to a plurality of signal lines and extend to the binding region, thereby binding the pixel structure to the external driver circuit or driver chip.

[0131] For example, in at least one embodiment of the present disclosure, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting element, the light-emitting element including at least an anode, an organic light-emitting layer and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, and the organic light-emitting layer emitting light of a corresponding color under the drive of the anode and the cathode. The encapsulation structure layer 104 includes a first encapsulation layer, a second encapsulation layer and a third encapsulation layer arranged in a stacked manner, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form a three-layer stacked structure of inorganic material / organic material / inorganic material, thereby ensuring that external water vapor and oxygen cannot enter the light-emitting structure layer 103 to protect the light-emitting element.

[0132] For example, in an embodiment of the present disclosure, when the substrate is a rigid substrate, the rigid substrate includes one of a glass substrate and a quartz substrate. When the substrate is a flexible substrate, the material of the flexible substrate includes one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber.

[0133] For example, in an embodiment of the present disclosure, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked. The first flexible material layer and the second flexible material layer may be made of polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the first inorganic material layer and the second inorganic material layer may be made of silicon nitride (SiNx) or silicon oxide (SiOx) to improve the waterproof and oxygen permeability of the substrate. The first inorganic material layer and the second inorganic material layer may also be referred to as barrier layers, and the semiconductor layer may be made of amorphous silicon (a-Si), etc.

[0134] For example, in an embodiment of the present disclosure, a driving circuit layer 102, a light-emitting structure layer 103, and an encapsulation structure layer 104 are provided on the main surface of the substrate. In a plane parallel to the main surface of the substrate, the driving circuit layer 102 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, each circuit unit including a pixel driving circuit configured to output a corresponding current to a light-emitting element connected thereto. The light-emitting structure layer 103 may include a plurality of light-emitting units, each light-emitting unit including a light-emitting element, the light-emitting element being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting element being configured to emit light of corresponding brightness in response to the current output by the connected pixel driving circuit.

[0135] It should be noted that the circuit unit in the embodiments of the present disclosure refers to an area divided according to the pixel driving circuit, and the light-emitting unit in the embodiments of the present disclosure refers to an area divided according to the light-emitting element. In the embodiments of the present disclosure, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0136] For example, Figure 3 This is a schematic diagram of an equivalent circuit of a pixel driving circuit provided by at least one embodiment of the present disclosure, such as Figure 3As shown, the pixel driving circuit has a 9T1C structure, which includes nine transistors (first transistor T1 to ninth transistor T9) and one storage capacitor C. Each pixel driving circuit is connected to 12 signal lines, including a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a fourth scan signal line S4, a fifth scan signal line S5, a first light-emitting control signal line EM1, a second light-emitting control signal line EM2, a first initialization signal line INIT1, a second initialization signal line INIT2, a third initialization signal line INIT3, a data signal line DATA, and a power supply voltage signal line VDD. The fourth scan signal line is also the first reset control signal line.

[0137] For example, in at least one embodiment of the present disclosure, each pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is respectively connected to the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the first electrode of the light-emitting element EL, and the fifth node N5 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9.

[0138] For example, in at least one embodiment of the present disclosure, a first plate of a storage capacitor C in a pixel driving circuit is connected to a first node N1, and a second plate of the storage capacitor C is connected to a power supply voltage signal line VDD. For example, the first plate and the second plate are disposed opposite each other, and an orthographic projection of the first plate on the main surface of the base substrate at least partially overlaps with an orthographic projection of the second plate on the main surface of the base substrate.

[0139] For example, in at least one embodiment of the present disclosure, the first transistor T1 is a first initialization transistor, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor T1 is connected to the fifth node N5 and also connected to the second electrode of the driving transistor.

[0140] For example, in at least one embodiment of the present disclosure, the second transistor T2 is a compensation transistor, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the fifth node N5 and is also connected to the gate of the driving transistor, and the second electrode of the second transistor T2 is connected to the third node N3 and is also connected to the second electrode of the driving transistor.

[0141] For example, in at least one embodiment of the present disclosure, the third transistor T3 is a driving transistor, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0142] For example, in at least one embodiment of the present disclosure, the fourth transistor T4 is a data writing transistor, the gate electrode of the fourth transistor T4 is connected to the second scan signal line S2, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2, that is, it is also electrically connected to the second electrode of the eighth transistor.

[0143] For example, in at least one embodiment of the present disclosure, the fifth transistor T5 is a first light-emitting control transistor, the gate electrode of the fifth transistor T5 is connected to the first light-emitting control signal line EM1, the first electrode of the fifth transistor T5 is connected to the power supply voltage signal line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0144] For example, the second electrode of the first light-emitting control transistor T5 and the second electrode of the third initialization transistor T8 are connected to the first electrode of the driving transistor T3, the second node electrode N2 is respectively connected to the first electrode of the driving transistor T3, the second electrode of the first light-emitting control transistor T5 and the second electrode of the third initialization transistor T8, and the orthographic projection of the second node electrode N2 on the substrate at least partially overlaps with the orthographic projection of the first initialization signal line INIT1 on the substrate.

[0145] For example, in at least one embodiment of the present disclosure, the sixth transistor T6 is a second light-emitting control transistor, the gate electrode of the sixth transistor T6 is connected to the second light-emitting control signal line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3 and is also electrically connected to the second electrode of the seventh transistor, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0146] For example, in at least one embodiment of the present disclosure, the seventh transistor T7 is a second initialization transistor, the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4, the first electrode of the seventh transistor T7 is connected to the second initialization signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4 and to the first electrode of the first light-emitting element.

[0147] For example, in at least one embodiment of the present disclosure, the eighth transistor T8 is a third initialization transistor, the gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5, the first electrode of the eighth transistor T8 is connected to the third initialization signal line INIT3, the second electrode of the eighth transistor T8 is connected to the second node N2, and is connected to the first electrode of the driving transistor T3.

[0148] For example, the first active layer is located between the base substrate and the first gate metal layer, and the first active layer includes a seventh active portion and an eighth active portion, the seventh active portion is used to form a channel region of the seventh transistor, and the eighth active portion is used to form a channel region of the eighth transistor; the orthographic projection of the first reset control signal line on the base substrate covers the orthographic projection of the eighth active portion on the base substrate and the orthographic projection of the seventh active portion on the base substrate, a partial structure of the first reset control signal line is used to form the gate of the seventh transistor, and a partial structure of the first reset control signal line is used to form the gate of the eighth transistor.

[0149] For example, the first active layer further includes a third active portion, a fourth active portion, a sixth active portion, and a ninth active portion, the third active portion is configured to form a channel region of the driving transistor, the fourth active portion and the eighth active portion are connected, and the sixth active portion and the seventh active portion are connected.

[0150] For example, the display substrate further includes a second active layer between the first active layer and the third gate metal layer, the second active layer includes a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

[0151] For example, in at least one embodiment of the present disclosure, the ninth transistor T9 is an isolation transistor, the gate electrode of the ninth transistor T9 is connected to the second scan signal line S2, the first electrode of the ninth transistor T9 is connected to the fifth node N5, and the second electrode of the ninth transistor T9 is connected to the first node N1.

[0152] For example, the second electrode of the first initialization transistor T1 is connected to the first electrode of the compensation transistor T2 and the first electrode of the isolation transistor T9. The second electrode of the isolation transistor T9 is connected to the gate electrode of the drive transistor T3. The second electrode of the compensation transistor T2 is connected to the second electrode of the drive transistor T3. The channel region of the isolation transistor T9 is located between the channel region of the compensation transistor T2 and the channel region of the data writing transistor T4.

[0153] For example, in at least one embodiment of the present disclosure, a first electrode of the light-emitting element EL is connected to the fourth node N4, and a second electrode of the light-emitting element EL is connected to the second power supply line VSS. In one example, the light-emitting element EL is an organic light-emitting diode (OLED), which includes a first electrode (anode), an organic light-emitting functional layer, and a second electrode (cathode) in a stacked arrangement. In another example, the light-emitting element EL is a quantum dot light-emitting diode (QLED), which includes a first electrode, a quantum dot light-emitting layer, and a second electrode in a stacked arrangement.

[0154] For example, in at least one embodiment of the present disclosure, the signal of the power voltage signal line VDD is a continuously provided high-level signal, and the signal of the second power line VSS is a continuously provided low-level signal.

[0155] For example, in some embodiments of the present disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may be a P-type transistor, or may be an N-type transistor. In other embodiments of the present disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may include a P-type transistor and an N-type transistor.

[0156] For example, in at least one embodiment of the present disclosure, the first transistor T1 to the ninth transistor T9 in the pixel driving circuit may be low-temperature polysilicon transistors, or metal oxide transistors, or both. The active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide). Low-temperature polysilicon transistors have advantages such as high mobility and fast charging, while metal oxide transistors have advantages such as low leakage current. Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form a display substrate using low-temperature polysilicon transistor and oxide transistor (LTPO) technology can utilize the advantages of both to achieve low-frequency driving, thereby reducing power consumption and improving the display quality of the display panel.

[0157] For example, Figure 3 As shown, the first transistor T1 and the second transistor T2 in the pixel driving circuit may be metal oxide transistors (N-type transistors), and the third transistor T3 to the ninth transistor T9 may be low temperature polysilicon transistors (P-type transistors).

[0158] For example, Figure 4 for Figure 3A driving timing diagram of the pixel driving circuit shown in FIG. Figure 4 As shown, the working process of the pixel driving circuit may include:

[0159] The first phase A1 can be referred to as a reset phase for the second node N2 and the fourth node N4. The signals on the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the fifth scan signal line S5 are low-level signals, and the signals on the second scan signal line S2, the first light-emission control signal line EM1, and the second light-emission control signal line EM2 are high-level signals, thereby turning on the seventh transistor T7 and the eighth transistor T8, and turning off the other transistors.

[0160] The seventh transistor T7 is turned on, causing the signal of the second initialization signal line INIT2 to be supplied to the fourth node N4, thereby initializing (resetting) the first electrode of the light-emitting element EL and clearing the existing charge in the first electrode of the light-emitting element EL, so that the potential of the fourth node N4 is Vinit2. The eighth transistor T8 is turned on, causing the signal of the third initialization signal line INIT3 to be supplied to the second node N2, thereby initializing (resetting) the second node N2 and causing the potential of the second node N2 to be Vinit3.

[0161] The second phase A2 can be referred to as the first node N1 reset phase. The signal on the first scan signal line S1 is a low-level signal. The signal on the second scan signal line S2 is a low-level signal twice and a high-level signal the rest of the time. The signals on the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emission control signal line EM1, and the second light-emission control signal line EM2 are high-level signals, thereby turning on the first transistor T1, turning on the fourth transistor T4 and the ninth transistor T9 twice, and turning off the other transistors.

[0162] When the first transistor T1 is turned on, the signal from the first initialization signal line INIT1 is supplied to the fifth node N5. When the fourth transistor T4 and the ninth transistor T9 are turned on, the signal from the first initialization signal line INIT1 is supplied to the first node N1 to initialize (reset) the first node N1 and clear any existing charge in the first node N1. The potential of the first node N1 is Vinit1. Because the ninth transistor T9 is a low-temperature polysilicon transistor, before the ninth transistor T9 is turned on for the first time, it is affected by the potential of the first node N1 and the gate bias. The potential of the first node N1 is related to the data voltage in the previous stage, and thus the characteristics of the ninth transistor T9 are affected by the previous stage. After the ninth transistor T9 is turned on for the first time, the potential of the first node N1 is reset to Vinit1. The gate voltage of the ninth transistor T9 remains relatively stable, whether high or low. Therefore, after the first turning on and off, the influence of the previous stage data on the characteristics of the ninth transistor T9 is cleared. When the ninth transistor T9 is turned on for the second time, the potential of the first node N1 is reset to Vinit1 again. The disclosed embodiments reset the first node N1 twice in succession, thereby effectively eliminating the effect of the data voltage in the previous stage on the characteristics of the ninth transistor T9, thereby improving afterimages and low grayscale image quality. Furthermore, due to the two conduction times of the fourth transistor T4 in this stage, the data signal line DATA writes the data voltages of the previous several cell rows to the second node N2, changing the potential of the second node N2 and, consequently, changing the gate-source voltage of the third transistor T3. This resets the characteristics of the third transistor T3, thereby improving afterimages.

[0163] The third phase A3, which can be referred to as a phase in which the third node N3 is reset, is characterized in that the signals on the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, the fourth scan signal line S4, the fifth scan signal line S5, the first light-emission control signal line EM1, and the second light-emission control signal line EM2 are high-level signals, thereby turning on the first transistor T1 and the second transistor T2 and turning off the other transistors.

[0164] The second transistor T2 is turned on, so that the third node N3 and the fifth node N5 are turned on, and the first transistor T1 is turned on so that the signal of the first initialization signal line INIT1 is provided to the third node N3, initializing (resetting) the third node N3, clearing the original charge in the third node N3, and making the potential of the third node N3 Vinit1.

[0165] The fourth phase A4 can be called a data writing phase. The signal on the third scan signal line S3 is a low-level signal, the signal on the second scan signal line S2 is a low-level signal for a short period of time, and the signals on the first scan signal line S1, the fourth scan signal line S4, the fifth scan signal line S5, the first emission control signal line EM1, and the second emission control signal line EM2 are high-level signals, turning on the second transistor T2, the fourth transistor T4, and the ninth transistor T9, while turning off the other transistors.

[0166] The second transistor T2 is turned on, thereby conducting the third node N3 and the fifth node N5. The ninth transistor T9 is turned on, thereby conducting the first node N1 and the fifth node N5. Since the third transistor T3 is continuously turned on during this stage, the fourth transistor T4 is turned on, causing the data signal output from the data signal line DATA to be provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, the turned-on second transistor T2, the fifth node N5, and the turned-on ninth transistor T9. The difference between the data voltage output from the data signal line DATA and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage at the first node N1 is Vd1-|Vth|, where Vd is the data voltage output from the data signal line DATA and Vth is the threshold voltage of the third transistor T3. When the ninth transistor T9 is turned off, the storage capacitor C holds the data voltage.

[0167] The fifth stage A5 can be referred to as a reset stage for the second node N2, the third node N3, and the fourth node N4. The signals on the first scan signal line S1 and the third scan signal line S3 are low-level signals. The signals on the fourth scan signal line S4 and the fifth scan signal line S5 are low-level signals in succession for a short period of time. The signals on the second scan signal line S2, the first emission control signal line EM1, and the second emission control signal line EM2 are high-level signals. This turns on the seventh transistor T7 and the eighth transistor T8, while turning off the other transistors.

[0168] The seventh transistor T7 is turned on, causing the signal of the second initialization signal line INIT2 to be supplied to the fourth node N4. Since the third transistor T3 is continuously turned on during this stage, the eighth transistor T8 is turned on, causing the signal of the third initialization signal line INIT3 to be supplied to the second node N2 and the third node N3, respectively resetting the second node N2, the third node N3, and the fourth node N4. The potentials of the second node N2 and the third node N3 are Vinit3, and the potential of the fourth node N4 is Vinit2. Resetting the second node N2, the third node N3, and the fourth node N4 in this stage can improve and reduce hysteresis deviation caused by grayscale differences between adjacent pixels. It can also periodically reset the OLED anode to reduce low-frequency flicker.

[0169] The sixth stage A6 can be referred to as a stage where the second node N2 and the third node N3 are reset. The signals on the first scan signal line S1, the third scan signal line S3, and the first light-emission control signal line EM1 are low-level signals, while the signals on the second scan signal line S2, the fourth scan signal line S4, the fifth scan signal line S5, and the second light-emission control signal line EM2 are high-level signals, turning on the fifth transistor T5 and turning off the other transistors.

[0170] The fifth transistor T5 is turned on so that the power supply voltage Vdd outputted by the power supply voltage signal line VDD is provided to the second node N2 and the third node N3, thereby resetting the second node N2 and the third node N3, that is, resetting the first electrode and the second electrode of the third transistor T3.

[0171] The seventh stage A7 can be called the light-emitting stage. The signals on the first scan signal line S1, the third scan signal line S3, the first light-emitting control signal line EM1, and the second light-emitting control signal line EM2 are low-level signals, and the signals on the second scan signal line S2, the fourth scan signal line S4, and the fifth scan signal line S5 are high-level signals, turning on the fifth transistor T5 and the sixth transistor T6, and turning off the other transistors.

[0172] The fifth transistor T5 and the sixth transistor T6 are turned on so that the power voltage output from the power voltage signal line VDD provides a driving voltage to the first electrode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the light emitting element EL to emit light.

[0173] During the pixel driving circuit's driving process, the driving current flowing through the third transistor T3 (driving transistor) of each pixel driving circuit is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage at the first node N1 is Vd-|Vth|, the driving current of the third transistor T3 is:

[0174] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0175] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light emitting element EL, K is a constant related to process and design, and Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3.

[0176] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor T3 of each pixel driving circuit is no longer affected by the threshold voltage of the third transistor T3, thereby eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0177] For example, Figure 5 for Figure 3 Another driving timing diagram of the pixel driving circuit shown. Figure 5 The working process of the pixel driving circuit shown is similar to Figure 4 The operation process of the pixel driving circuit shown is basically the same, with the only difference being that in the first phase A1, the signals on the fourth scan signal line S4 and the fifth scan signal line S5 are high-level signals, the seventh transistor T7 and the eighth transistor T8 are turned off, and the second node N2 and the fourth node N4 are not reset in this phase. In the fifth phase A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is low-level for a short period of time, and the fourth transistor T4 and the ninth transistor T9 are turned on again. The fourth transistor T4 is turned on, causing the data voltage of the next unit row to reset the second node N2 and the third node N3. The ninth transistor T9 is turned on, causing the first node N1 and the fifth node N5 to be conductive. After the charges on the two nodes are neutralized, there is no longer a potential difference between the two nodes.

[0178] For example, the following combines the planar structural schematic diagram of each film layer and the structural schematic diagram of multiple film layers stacked together, and takes the pixel driving circuit as an example, including a storage capacitor and multiple transistors, the storage capacitor includes a first electrode plate and a second electrode plate stacked together, the first transistor T1 among the multiple transistors serves as a first initialization transistor, the second transistor T2 serves as a compensation transistor, the third transistor T3 serves as a driving transistor, the fourth transistor T4 serves as a data writing transistor, the fifth transistor T5 serves as a first light-emitting control transistor, the sixth transistor T6 serves as a second light-emitting control transistor, the seventh transistor T7 serves as a second initialization transistor, the eighth transistor T8 serves as a third initialization transistor, the ninth transistor T9 serves as an isolation transistor, and the first transistor T1 and the second transistor T2 are metal oxide transistors, and the third transistor T3 to the ninth transistor T9 are low-temperature polysilicon transistors.

[0179] For example, in the display substrate provided by the embodiment of the present disclosure, the display substrate further includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit and a control signal line, and the control signal line is configured to provide a control signal to the pixel driving circuit. Figure 6 This is a schematic diagram of an equivalent circuit of another pixel driving circuit provided in at least one embodiment of the present disclosure. Figure 6 The pixel driving circuit of the n-1th unit row and the pixel driving circuit of the nth unit row are shown. The pixel driving circuit of the n-1th unit row and the pixel driving circuit of the nth unit row are arranged in sequence in the second direction Y. Figure 6 The direction intersecting the second direction Y is the first direction X. The structures of the pixel driving circuits of the n-1th unit row and the pixel driving circuits of the nth unit row can be referred to above. Figure 3 The pixel driving circuit structure diagram shown in FIG.

[0180] For example, the pixel driving circuit includes a driving transistor T3, a first control transistor T5 / T8, and a second control transistor T6 / T7. The first control transistor T5 / T8 and the second control transistor T6 / T7 are respectively connected to the driving transistor T3, and the first control transistor T5 / T8 and the second control transistor T6 / T7 connected to the same driving transistor T3 are respectively arranged on both sides of the driving transistor T3 in the column direction. The first control transistor T5 / T8 is electrically connected to the control signal line in the previous unit row, and the second control transistor T6 / T7 is electrically connected to the control signal line in the current unit row. The control signal line includes a scan control signal line, the first control transistor includes a third initialization transistor T8, the second control transistor T6 / T7 includes a second initialization transistor T7, the first electrode of the second initialization transistor T7 is connected to the second initialization signal line INT2, the second electrode of the second initialization transistor T7 is connected to the second electrode of the driving transistor T3 through the second light-emitting control transistor T6, the first electrode of the third initialization transistor T8 is connected to the third initialization signal line INT3, the second electrode of the third initialization transistor T8 is connected to the first electrode of the driving transistor T3, the gate electrode of the third initialization transistor T8 is connected to the scan signal line in the previous unit row, and the gate electrode of the second initialization transistor T7 is connected to the scan signal line in the current unit row.

[0181] For example, the second initialization transistor T7 and the third initialization transistor T8 connected to the same driving transistor T3 are respectively arranged on both sides of the driving transistor T3 in the unit column direction.

[0182] For example, in at least one embodiment of the present disclosure, the control signal line includes a light-emission control signal line, the first control transistor includes a first light-emission control transistor T5, the second control transistor includes a second light-emission control transistor T6, a first electrode of the first light-emission control transistor T5 is connected to a power supply voltage signal line, a second electrode of the first light-emission control transistor T5 is connected to a first electrode of the driving transistor T3, and a first electrode of the second light-emission control transistor T6 is connected to a second electrode of the driving transistor T3. For example, the gate electrode of the first light-emission control transistor T5 is connected to the light-emission control signal line in the previous cell row, and the gate electrode of the second light-emission control transistor T6 is electrically connected to the light-emission control signal line in the current cell row.

[0183] For example, in at least one embodiment of the present disclosure, the second initialization transistor T7 includes a second initialization active layer, and the third initialization transistor T8 includes a third initialization active layer; in at least one pixel driving circuit of at least one unit row, the third initialization active layer is set in the circuit unit of the previous unit row, and the second initialization active layer is set in the circuit unit of the current unit row.

[0184] For example, in at least one embodiment of the present disclosure, in at least one pixel driving circuit of at least one unit row, the third initialization active layer is arranged on one side of the second initialization active layer of the pixel driving circuit in the previous unit row in the unit row direction.

[0185] For example, in at least one embodiment of the present disclosure, the first region of the second initialization active layer is connected to the second initialization signal line INIT2 in the current cell row, and the first region of the third initialization active layer is connected to the third initialization signal line INIT2 in the previous cell row.

[0186] For example, Figure 6 As shown, the gate electrode of the fifth transistor T5 in the pixel driving circuit of the nth unit row is connected to the first light-emission control signal line EM1 of the unit row, and the gate electrode of the sixth transistor T6 is connected to the second light-emission control signal line EM2 of the unit row. The second light-emission control signal line EM2 of the n-1th unit row is interconnected with the first light-emission control signal line EM1 of the nth unit row, that is, the second light-emission control signal line EM2 of the n-1th unit row and the first light-emission control signal line EM1 of the nth unit row are the same light-emission control signal line. The sixth transistor T6 of the n-1th unit row and the fifth transistor T5 of the nth unit row share the same light-emission control signal line. The fourth scan signal line S4 of the n-1th unit row is interconnected with the fifth scan signal line S5 of the nth unit row, that is, the fourth scan signal line S4 of the n-1th unit row and the fifth scan signal line S5 of the nth unit row are the same scan signal line. The seventh transistor T7 of the n-1th unit row and the eighth transistor T8 of the nth unit row share the same scan signal line, and n is a positive integer greater than 1.

[0187] For example, in at least one embodiment of the present disclosure, in at least one pixel driving circuit, the fifth transistor T5 and the sixth transistor T6 connected to the same third transistor T3 can be respectively disposed on both sides of the third transistor T3 in the unit column direction (the second direction Y). For example, in a pixel driving circuit in the nth unit row, the fifth transistor T5 can be disposed on a side of the third transistor T3 that is opposite to the second direction Y, and the sixth transistor T6 can be disposed on a side of the third transistor T3 that is along the second direction Y.

[0188] For example, in another embodiment of the present disclosure, the fourth scan signal line S4 and the fifth scan signal line S5 of each unit row may not use a cascade signal, but may use the same control signal. The fourth scan signal line S4 and the fifth scan signal line S5 of each unit row may be the same control signal, and the embodiment of the present disclosure is not limited to this.

[0189] For example, in another embodiment of the present disclosure, the first scan signal line S1 and the third scan signal line S3 of each unit row may be provided by different gate driving circuits, or cascade signals may be used, which is not limited in the embodiment of the present disclosure.

[0190] For example, in at least one embodiment of the present disclosure, the fifth transistor T5 includes a fifth active layer, and the sixth transistor T6 includes a sixth active layer. The fifth active layer can serve as the first light-emitting control active layer in the embodiment of the present disclosure, and the sixth active layer can serve as the second light-emitting control active layer in the embodiment of the present disclosure. In at least one pixel driving circuit of at least one unit row, the fifth active layer can be set in the circuit unit of the previous unit row, and the sixth active layer can be set in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the fifth active layer can be set in the circuit unit of the n-1th unit row, and the sixth active layer can be set in the circuit unit of the nth unit row.

[0191] For example, in at least one embodiment of the present disclosure, in at least one pixel driving circuit in at least one unit row, the fifth active layer may be disposed on one side in the first direction X (unit row direction) of the sixth active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the fifth active layer may be disposed on one side in the first direction X of the sixth active layer of the pixel driving circuit in the (n-1)th unit row.

[0192] For example, in at least one embodiment of the present disclosure, in a pixel driving circuit, the gate electrode of the eighth transistor T8 is connected to the fifth scan signal line S5 in the current unit row. In the previous unit row, in at least one pixel driving circuit in at least one unit row, the gate electrode of the seventh transistor T7 is connected to the fourth scan signal line S4 in the current unit row. For example, the gate electrode of the eighth transistor T8 in the pixel driving circuit in the nth unit row is connected to the fifth scan signal line S5 in the nth unit row, and the gate electrode of the seventh transistor T7 in the pixel driving circuit in the (n-1)th unit row is connected to the fourth scan signal line 24 in the nth unit row. The fourth scan signal line S4 is connected to the fifth scan signal line S5.

[0193] For example, in at least one embodiment of the present disclosure, in a pixel driving circuit, the seventh transistor T7 and the eighth transistor T8 connected to the same third transistor T3 may be respectively disposed on both sides of the third transistor T3 along the second direction Y. For example, in a pixel driving circuit of an n-th unit row, the eighth transistor T8 may be disposed on a side opposite to the second direction Y of the third transistor T3, and the seventh transistor T7 may be disposed on a side of the third transistor T3 in the second direction Y.

[0194] For example, in at least one embodiment of the present disclosure, the seventh transistor T7 includes a seventh active layer, and the eighth transistor T8 includes an eighth active layer. The seventh transistor T7 can serve as the second initialization active layer in the embodiment of the present disclosure, and the eighth active layer can serve as the third initialization active layer in the embodiment of the present disclosure. In the pixel driving circuit, the eighth active layer can be set in the circuit unit of the previous unit row, and the seventh active layer can be set in the circuit unit of the current unit row. For example, in a pixel driving circuit of the nth unit row, the eighth active layer can be set in the circuit unit of the (n-1)th unit row, and the seventh active layer can be set in the circuit unit of the nth unit row.

[0195] For example, in at least one embodiment of the present disclosure, in a pixel driving circuit, the eighth active layer may be disposed on one side in the first direction X (unit row direction) of the seventh active layer of the pixel driving circuit in the previous unit row. For example, in a pixel driving circuit in the nth unit row, the eighth active layer may be disposed on one side in the first direction X of the seventh active layer of the pixel driving circuit in the (n-1)th unit row.

[0196] For example, in at least one embodiment of the present disclosure, in a pixel driving circuit, the first area of ​​the seventh active layer is connected to the second initialization signal line INIT2 in the current unit row, and the first area of ​​the eighth active layer is connected to the third initialization signal line INIT3 in the current unit row. For example, in a pixel driving circuit in the nth unit row, the first area of ​​the seventh active layer is connected to the second initialization signal line INIT2 in the nth unit row, and the first area of ​​the eighth active layer is connected to the third initialization signal line INIT3 in the (n-1)th unit row.

[0197] For example, the following briefly describes the structure of each layer of the display substrate in the embodiment of the present disclosure by taking four circuit units arranged in the same row as an example.

[0198] It should be noted that in some exemplary embodiments, the corresponding structure can be changed according to actual needs, and the embodiments of the present disclosure are not limited to this. The structure of the display substrate is described using the above-mentioned 9T1C pixel circuit as an example. In other exemplary embodiments, the pixel circuit can also be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure, and the embodiments of the present disclosure are not limited to this.

[0199] For example, Figure 7 This is a schematic diagram of the planar structure of a light shielding layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 7 As shown, the light shielding layer 201 may be a bottom light shielding metal (BSM) layer.

[0200] For example, Figure 7 As shown, the pattern of the light-shielding layer includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and a light-shielding electrode 2013, with the plurality of light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is roughly rectangular, and the corners of the rectangle may be chamfered. The first light-shielding connecting line 2011 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first light-shielding connecting line 2011 may be disposed on either side of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013. The second light-shielding connecting line 2012 may be in the shape of a straight line or a zigzag line extending along the first direction X. The second light-shielding connecting line 2012 may be disposed on either side of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013, thereby forming a mesh-like pattern on the light-shielding layer.

[0201] For example, Figure 7 As shown, in a unit row, the second light-shielding connection lines 2012 in two adjacent circuit units in the first direction X can be connected to form an interconnected integrated structure.

[0202] For example, in other embodiments of the present disclosure, in a unit column, the first shading connection lines 2011 in two adjacent circuit units in the second direction Y can be connected to form an integrated structure that is interconnected, that is, the shading layers in the unit row and the unit column are connected into one, thereby ensuring that the shading layers in the display substrate have the same electric potential, which is beneficial to improving the display uniformity of the subsequently formed display panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.

[0203] For example, forming the pattern of the light shielding layer includes: depositing a light shielding layer thin film on the base substrate, and patterning the light shielding layer thin film through a patterning process to form a light shielding layer pattern. The material of the light shielding layer can be a light shielding metal material.

[0204] It should be noted that the "patterning process" mentioned in the embodiments of the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes; for organic materials, it includes coating of organic materials, mask exposure and development and other processes. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition; coating can be carried out by any one or more of spraying, spin coating and inkjet printing; etching can be carried out by any one or more of dry etching and wet etching, and the embodiments of the present disclosure are not limited to this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". In the embodiments of the present disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the main surface of the display substrate. In the embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B. This will not be further described below.

[0205] For example, Figure 8 This is a schematic diagram of the planar structure of the first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 8 As shown, the first semiconductor layer 202 may form the third active layer 23 of the third transistor T3 to the ninth active layer 29 of the ninth transistor T9 .

[0206] For example, Figure 8 As shown, the third active layer 23 , the fourth active layer 24 , the fifth active layer 25 , the sixth active layer 26 and the seventh active layer 27 are interconnected as an integral structure, and the eighth active layer 28 and the ninth active layer 29 are separately provided.

[0207] For example, the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor), and the ninth active layer 29 is the channel region of the ninth transistor T9 (isolation transistor).

[0208] For example, Figure 9 This is a schematic diagram of a planar structure of a stack of a light shielding layer and a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 9 As shown, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the substrate. The light-shielding electrode 2013 serves as a light-shielding layer of the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0209] For example, in an embodiment of the present disclosure, in the pixel driving circuit of the present circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the present circuit unit in the first direction X, and the sixth active layer 26 is located on a side of the third active layer 23 in the present circuit unit in the opposite direction to the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the present circuit unit in the second direction Y. The ninth active layer 29 is located on a side of the fourth active layer 24 in the opposite direction to the second direction Y.

[0210] For example, Figure 8 and Figure 9 As shown, the shape of the third active layer 23 can be an inverted "Ω" shape, the shapes of the fourth active layer 24, the fifth active layer 25, the sixth active layer 26 and the ninth active layer 29 can be strip shapes with the main part extending along the second direction Y, the shape of the seventh active layer 27 can be an inverted "L" shape, and the shape of the eighth active layer 28 can be an "L" shape.

[0211] For example, Figure 8As shown, the third to ninth active layers 23 to 29 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 25a of the seventh active layer 27, the first region 28a of the eighth active layer 28, the second region 28b of the eighth active layer 28, the first region 29a of the ninth active layer 29, and the second region 29b of the ninth active layer 29 can be set separately.

[0212] For example, Figure 8 As shown, in a unit column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit unit can be set in the circuit unit of the previous unit row, and the third active layer 23, the fourth active layer 24, the sixth active layer 26, the seventh active layer 27 and the ninth active layer 29 can be set in this circuit unit.

[0213] For example, Figure 8 As shown, the fifth active layer 25 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the first direction X of the sixth active layer 26 of the pixel driving circuit in the circuit unit of the previous unit row, so that the fifth active layer 25 and the sixth active layer 26 of the pixel driving circuit in the two unit rows can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of the current unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the n-th unit row is arranged in the circuit unit of the n-1-th unit row, so that the fifth active layer 25 of the pixel driving circuit in the n-th unit row and the sixth active layer 26 of the pixel driving circuit in the n-1-th unit row can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the n-th unit row and the sixth transistor T6 of the n-1-th unit row.

[0214] For example, in at least one embodiment of the present disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the seventh active layer 28 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the current unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is arranged in the circuit unit of the n-1th unit row, so that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the n-1th unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the n-1th unit row and the eighth transistor T8 of the nth unit row.

[0215] For example, in at least one embodiment of the present disclosure, the first semiconductor layer 202 is formed of polycrystalline silicon (p-Si), that is, the third transistor T3 to the ninth transistor T9 are LTPS transistors.

[0216] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor film, and then patterning the first semiconductor film through a patterning process. For example, the process of patterning the first semiconductor film through the patterning process includes: first forming an amorphous silicon (A-Si) film, dehydrogenating the A-Si film, crystallizing the dehydrogenated A-Si film to form a polycrystalline silicon film, and then patterning the polycrystalline silicon film to form the pattern of the first semiconductor layer.

[0217] For example, Figure 10 A schematic diagram of the planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 11 This is a schematic planar structural diagram of a stack of a light shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 10 As shown, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scanning signal line 2031, a fourth scanning signal line 2032, a light emitting control signal line 2033, a first initialization signal line 2034 and a first plate 2035 of a storage capacitor.

[0218] For example, Figure 11 As shown, the first electrode plate 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode plate 2035 can simultaneously serve as a plate of the storage capacitor and the gate electrode of the third transistor T3.

[0219] For example, Figure 11 As shown, the orthographic projection of the first electrode plate 2035 on the base substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the base substrate.

[0220] For example, Figure 11 As shown, the shape of the second scanning signal line 2031 is a straight line or a broken line with the main part extending along the first direction X. The second scanning signal line 2031 is located on the side of the first electrode 2035 in the opposite direction of the second direction Y. The area where the second scanning signal line 2031 overlaps with the fourth active layer 24 can be used as the gate electrode of the fourth transistor T4, and the area where the second scanning signal line 2031 overlaps with the ninth active layer 29 can be used as the gate electrode of the ninth transistor T9.

[0221] For example, Figure 11 As shown, the fourth scan signal line 2032 is shaped as a straight line or a zigzag line with its main portion extending along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode 2035 in the second direction Y. The area where the fourth scan signal line 2032 of the current unit row overlaps with the seventh active layer 27 of the pixel driving circuit in the current unit row serves as the gate electrode of the seventh transistor T7 in the current unit row. The area where the fourth scan signal line 2032 of the current unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the (n)th unit row can serve as the gate electrode of the eighth transistor T8 in the (n)th unit row.

[0222] For example, Figure 11As shown, the light-emitting control signal line 2033 is in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode 2035 and the fourth scanning signal line 2032. The area where the light-emitting control signal line 2033 of the current unit row overlaps with the sixth active layer 26 of the pixel driving circuit in the current unit row can serve as the gate electrode of the sixth transistor T6 of the current unit row, and the area where the light-emitting control signal line 2033 of the current unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can serve as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the n-1th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the n-1th unit row can serve as the gate electrode of the sixth transistor T6 in the n-1th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the fifth transistor T5 in the nth unit row.

[0223] For example, Figure 11 As shown, the shape of the first initialization signal line 2034 is a straight line or a broken line with the main part extending along the first direction X. The first initialization signal line 2034 is located on the side of the second scanning signal line 2031 away from the first electrode 2035. The first initialization signal line 2031 is configured to be connected to the first area of ​​the first active layer mentioned later.

[0224] For example, Figure 11 As shown, the second scanning signal line 2031, the fourth scanning signal line 2032, the light-emitting control signal line 2033 and the first initialization signal line 2034 have different widths in the second direction Y. The second scanning signal line 2031, the fourth scanning signal line 2032, the light-emitting control signal line 2033 and the first initialization signal line 2034 only need to facilitate the layout of the pixel structure and reduce the parasitic capacitance between the signal lines. The embodiments of the present disclosure are not limited to this.

[0225] For example, Figure 11 As shown, the second scanning signal line 2031, the fourth scanning signal line 2032 and the light-emitting control signal line 2033 include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer. The width of the signal line in the area overlapping with the first semiconductor layer can be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0226] For example, Figure 11As shown, after the pattern of the first gate metal layer is formed, the first gate metal layer can be used as a blocking layer to conduct the first semiconductor layer. The first semiconductor layer in the area blocked by the first gate metal layer forms the channel area of ​​the third transistor T3 to the ninth transistor T9, and the first semiconductor layer in the area not blocked by the first gate metal layer is conducted, that is, the first electrode 2035 and the first and second areas of the third active layer 23 to the ninth active layer 29 are all conducted.

[0227] For example, in an embodiment of the present disclosure, the process of forming a first gate metal layer includes: depositing a second insulating layer film and a first conductive metal film in sequence on a base substrate on which a light-shielding layer and a first semiconductor layer are formed, patterning the first conductive metal film through a patterning process to form a second insulating layer covering the pattern of the first semiconductor layer, and a pattern of the first gate metal layer arranged on the second insulating layer. For example, the first gate metal layer can be referred to as a GATE1 layer.

[0228] For example, in an embodiment of the present disclosure, the material of the first gate metal layer 203 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate metal layer 203 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0229] For example, Figure 12 A schematic diagram of the planar structure of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 13 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the second gate metal layer may be referred to as a GATE2 layer.

[0230] For example, in at least one embodiment of the present disclosure, the pattern of the second gate metal layer 204 of each circuit unit includes: a second plate 2041 of the storage capacitor, a first shielding line 2042 and a second shielding line 2043 .

[0231] For example, Figure 12 and 13 As shown, the outline of the second plate 2041 is rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate 2041 on the substrate at least partially overlaps with the orthographic projection of the first plate 2035 on the substrate. The second plate 2041 can serve as another plate of the storage capacitor. The first plate 2035 and the second plate 2041 constitute the storage capacitor of the pixel driving circuit.

[0232] For example, Figure 12 and Figure 13 As shown, the second electrode plate 2041 is provided with an opening 2041a. The opening 2041a can be rectangular in shape and located in the middle region of the second electrode plate 2041, so that the second electrode plate 2041 forms a ring structure. The opening 2041a exposes the third insulating layer covering the first electrode plate 2035, and the orthographic projection of the first electrode plate 2035 on the base substrate covers the orthographic projection of the opening 2041a on the base substrate.

[0233] For example, Figure 12 and Figure 13 As shown, the second electrode plate 2041 includes an electrode block 2041b. The electrode block 2041b may be in the shape of a strip extending along the first direction X.

[0234] For example, Figure 12 and Figure 13 As shown, the shape of the first shielding line 2042 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding line 2042 can be located between the first electrode 2035 and the second scanning signal line 2031. The first shielding line 2042 is configured as a light shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2 whose active layer is formed by metal oxide, and is configured as a bottom gate electrode of the second transistor T2.

[0235] For example, Figure 12 and Figure 13 As shown, the shape of the second shielding line 2043 is a straight line or a broken line with the main part extending along the first direction X. The second shielding line 2043 is located between the second scanning signal line 2031 and the first initialization signal line 2034. The second shielding line 2043 is configured as a light shielding layer for the first transistor T1, shielding the channel region of the first transistor T1 to ensure the electrical performance of the first transistor T1 whose active layer is formed by metal oxide, and is also configured as a bottom gate electrode of the first transistor T1.

[0236] For example, Figure 12 and Figure 13 As shown, the first shielding line 2042 and the second shielding line 2043 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0237] For example, the process of forming the pattern of the second gate metal layer includes: depositing a third insulating film and a second metal conductive film in sequence on a base substrate on which a light-shielding layer, a first semiconductor layer and a first gate metal layer are formed with patterns, and patterning the second conductive metal film using a patterning process to form a third insulating layer covering the first gate metal layer, and a pattern of the second gate metal layer arranged on the third insulating layer.

[0238] For example, in an embodiment of the present disclosure, the material of the second gate metal layer 204 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second gate metal layer 204 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0239] For example, Figure 14 A schematic diagram of the planar structure of a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 15 This is a schematic plan view of the stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. For example, the first active layer of a first transistor T1 and the second active layer of a second transistor T2 are disposed on the second semiconductor layer.

[0240] For example, Figure 14 and Figure 15 As shown, the pattern of the second semiconductor layer 205 of each circuit unit includes at least a first active layer 21 of the first transistor T1 and a second active layer 22 of the second transistor T2.

[0241] For example, Figure 14 and Figure 15 As shown, the shape of the first active layer 21 and the second active layer 22 is a strip shape with the main part extending along the second direction Y, the orthographic projection of the first active layer 21 on the substrate at least partially overlaps with the orthographic projection of the second shading line 2043 on the substrate, and the orthographic projection of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the first shading line 2042 on the substrate.

[0242] For example, Figure 14 and Figure 15As shown, the first region 21a of the first active layer 21 is located on the side of the second shading line 2043 away from the second electrode 2041, the second region 22b of the second active layer 22 is located on the side of the first shading line 2042 close to the second electrode 2041, the second region 21b of the first active layer 21 is connected to the first region 22a of the second active layer 22, and the second region 21b of the first active layer 21 serves as the first region 22a of the second active layer 22.

[0243] For example, Figure 14 and Figure 15 As shown, the first active layer 21 and the second active layer 22 are an integrated structure connected to each other.

[0244] For example, Figure 15 As shown, the ninth active layer 29 is located between the second active layer 22 and the fourth active layer 24 , that is, the channel region of the ninth transistor T9 is located between the channel region of the second transistor T2 and the channel region of the fourth transistor T4 .

[0245] For example, Figure 15 As shown, the second semiconductor layer 205 is formed of a metal oxide material, that is, the first transistor T1 and the second transistor T2 are metal oxide thin film transistors. For example, in the embodiment of the present disclosure, the second semiconductor thin film can be formed of a metal oxide material such as indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0246] For example, the process of forming the pattern of the second semiconductor layer 205 includes: depositing an insulating layer film and a second semiconductor film in sequence on a base substrate having a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer, patterning the second semiconductor film through a patterning process to form an insulating layer covering the base substrate, and a pattern of the second semiconductor layer arranged on the insulating layer.

[0247] For example, Figure 16 A schematic planar structural diagram of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 17 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the third gate metal layer may be referred to as a GATE3 layer.

[0248] For example, Figure 16 and Figure 17 As shown, the pattern of the third gate metal layer 206 of each circuit unit includes at least: a first scanning signal line 2061, a third scanning signal line 2062, a second initialization signal line 2063 and a third initialization signal line 2064. Figure 17 As shown, the third gate metal layer 206 also includes a third scanning signal line 2062 and a first scanning signal line 2061 arranged on the side of the third initialization signal line 2064 close to the second initialization signal line 2063, the orthographic projection of the first scanning signal line 2061 on the substrate overlaps with the orthographic projection of the first shielding line 2042 on the substrate, and the orthographic projection of the third scanning signal line 2062 on the substrate overlaps with the orthographic projection of the second shielding line 2043 on the substrate.

[0249] For example, Figure 16 and Figure 17 As shown, the shape of the first scanning signal line 2061 is a straight line or a broken line with the main part extending along the first direction X. The first scanning signal line 2061 is located on the side of the first electrode 2035 away from the second scanning signal line 2031. The area where the first scanning signal line 2061 overlaps with the first active layer 21 can serve as the gate electrode of the first transistor T1.

[0250] For example, Figure 16 and Figure 17 As shown, the orthographic projection of the first scanning signal line 2061 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 2042 on the substrate, and the first scanning signal line 2061 and the first shielding line 2042 are connected to the same signal source, so that the first shielding line 2042 serves as the bottom gate electrode of the first transistor T1, and the first scanning signal line 2061 serves as the top gate electrode of the first transistor T1, so as to form a first transistor T1 with a dual-gate structure.

[0251] For example, Figure 16 and Figure 17 As shown, the shape of the third scanning signal line 2062 is a straight line or a broken line with the main part extending along the first direction X. The third scanning signal line 2062 is located on the side of the second scanning signal line 2031 away from the first scanning signal line 2061, and the area where the third scanning signal line 2062 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0252] For example, Figure 16 and Figure 17 As shown, the positive projection of the third scanning signal line 2062 on the substrate substrate at least partially overlaps with the positive projection of the second shielding line 2043 on the substrate substrate. The third scanning signal line 2062 and the second shielding line 2043 can be connected to the same signal source, so that the second shielding line 2043 serves as the bottom gate electrode of the second transistor T2, and the third scanning signal line 2062 serves as the top gate electrode of the second transistor T2, thereby forming a second transistor T2 with a dual-gate structure.

[0253] For example, Figure 16 and Figure 17 As shown, the shape of the second initialization signal line 2063 is a straight line or a broken line with the main part extending along the first direction X. The second initialization signal line 2063 is located on the side of the third scanning signal line 2062 away from the second electrode 2041. The second initialization signal line 2063 of this unit row is configured to be connected to the first area 27a of the seventh active layer 27 of the pixel driving circuit in the circuit unit of this unit row.

[0254] For example, Figure 17 As shown, the positive projection of the third initialization signal line 2064 on the substrate at least partially overlaps with the positive projection of the fourth scanning signal line 2032 on the substrate, so that the third initialization signal line 2064 with a constant potential can effectively shield the influence of the voltage jump of the fourth scanning signal line 2032 on the pixel driving circuit.

[0255] For example, Figure 17 As shown, the second initialization signal line 2063 is in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The second initialization signal line 2063 is located between the second electrode plate 2041 and the third initialization signal line 2064. The third initialization signal line 2064 of the current unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the next unit row. For example, the third initialization signal line 2064 of the (n-1)th unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the nth unit row.

[0256] For example, in an embodiment of the present disclosure, the process of forming a pattern of the third gate metal layer 206 includes: on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer is formed, depositing an insulating layer film and a third gate metal film in sequence, and patterning the third gate metal film using a patterning process to form an insulating layer covering the second semiconductor layer, and a pattern of the third gate metal layer arranged on the insulating layer.

[0257] For example, in an embodiment of the present disclosure, the material of the third gate metal layer 206 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third gate metal layer 206 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0258] For example, Figure 16 and Figure 17As shown, the third gate metal layer 206 is disposed between the first conductive metal layer mentioned later and the first gate metal layer 203 , and is also disposed on a side of the first conductive metal layer mentioned later away from the second conductive metal layer.

[0259] For example, Figure 18 A schematic diagram of the planar structure of an interlayer insulating layer of a display substrate provided in at least one embodiment of the present disclosure. Figure 19 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure.

[0260] For example, Figure 18 and Figure 19 As shown, a plurality of first-type via structures are provided in the interlayer insulating layer 207 , and the first conductive metal layer and the first semiconductor layer 202 involved subsequently are electrically connected through the first-type via structures.

[0261] It should be noted that although the term "interlayer insulating layer" is used to represent multiple first-type via structures, the interlayer insulating layer actually represents a portion of the via structures that pass through multiple insulating layers disposed between adjacent layers among the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the insulating layers between the adjacent layers and the interlayer insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The insulating layers and interlayer insulating layer may be single-layer, multi-layer, or composite layers.

[0262] For example, Figure 18 As shown, the multiple first-class via structures in each circuit unit include at least: a first-class fourth via structure V74, a first-class fifth via structure V75, a first-class sixth via structure V76, a first-class seventh via structure V77, a first-class eighth via structure V78, a first-class ninth via structure V79, a first-class tenth via structure V710, a first-class eleventh via structure V711, a first-class twelfth via structure V712, a first-class thirteenth via structure V713, a first-class fourteenth via structure V714, a first-class fifteenth via structure V715, a first-class sixteenth via structure V716 and a first-class seventeenth via structure V717.

[0263] For example, Figure 18 and 19As shown, the orthographic projection of the first-type fourth via structure V74 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer) on the substrate, and the first-type fourth via structure V74 exposes the surface of the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer), and the first-type fourth via structure V74 is configured to connect the subsequently formed first conductive metal layer with the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer).

[0264] For example, Figure 18 and 19 As shown, the orthographic projection of the first-type fifth via structure V75 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the first-type fifth via structure V75 exposes the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer). The first-type fifth via structure V75 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the third active layer (also the first area of ​​the sixth active layer).

[0265] For example, Figure 18 and 19 As shown, the orthographic projection of the first type sixth via structure V76 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the first type sixth via structure V76 exposes the surface of the first area of ​​the fourth active layer, and the first type sixth via structure V76 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the fourth active layer.

[0266] For example, Figure 18 and 19 As shown, the orthographic projection of the first-type seventh via structure V77 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the first-type seventh via structure V77 exposes the surface of the first area of ​​the fifth active layer, and the first-type seventh via structure V77 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the fifth active layer.

[0267] For example, Figure 18 and 19 As shown, the pixel driving circuits of two adjacent circuit units in the first direction X can share a first-type seventh via structure V77.

[0268] For example, Figure 18 and 19As shown, the orthographic projection of the first-type eighth via structure V78 on the main surface of the substrate is located within the range of the orthographic projection of the second area of ​​the fifth active layer on the main surface of the substrate, the first-type eighth via structure V78 exposes the surface of the second area of ​​the fifth active layer, and the first-type eighth via structure V78 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the fifth active layer.

[0269] For example, Figure 18 and 19 As shown, the orthographic projection of the first-type ninth via structure V79 on the main surface of the substrate substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the main surface of the substrate substrate, the first-type ninth via structure V79 exposes the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the first-type ninth via structure V79 is configured to connect the subsequently formed first conductive metal layer with the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer).

[0270] For example, Figure 18 and 19 As shown, the orthographic projection of the first type tenth via structure V710 on the main surface of the substrate is located within the range of the orthographic projection of the first area of ​​the seventh active layer on the main surface of the substrate, the first type tenth via structure V710 exposes the surface of the first area of ​​the seventh active layer, and the first type tenth via structure V710 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the seventh active layer.

[0271] For example, Figure 18 and 19 As shown, the orthographic projection of the first-type eleventh via structure V711 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the first-type eleventh via structure V711 exposes the surface of the first region of the eighth active layer, and the first-type eleventh via structure V711 is configured to connect the structure in the subsequently formed first conductive metal layer with the first region of the eighth active layer.

[0272] For example, Figure 18 and 19 As shown, the orthographic projection of the first type twelfth via structure V712 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the first type twelfth via structure V712 exposes the surface of the second region of the eighth active layer, and the first type twelfth via structure V712 is configured to connect the structure in the subsequently formed first conductive metal layer with the second region of the eighth active layer.

[0273] For example, Figure 18 and 19As shown, the orthographic projection of the first type thirteenth via structure V713 on the substrate is located within the range of the orthographic projection of the first area of ​​the ninth active layer on the substrate, the first type thirteenth via structure V713 exposes the surface of the first area of ​​the ninth active layer, and the first type thirteenth via structure V713 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the ninth active layer.

[0274] For example, Figure 18 and 19 As shown, the orthographic projection of the first type fourteenth via structure V714 on the substrate is located within the range of the orthographic projection of the second area of ​​the ninth active layer on the substrate, the first type fourteenth via structure V714 exposes the surface of the second area of ​​the ninth active layer, and the first type fourteenth via structure V714 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the ninth active layer.

[0275] For example, Figure 18 and 19 As shown, the orthographic projection of the first type fifteenth via structure V715 on the substrate is located within the range of the orthographic projection of the opening 2041a on the substrate, and the first type fifteenth via structure V715 exposes the surface of the first electrode 2035. The first type fifteenth via structure V715 is configured to connect the structure in the subsequently formed first conductive metal layer to the first electrode 2035.

[0276] For example, Figure 18 and 19 As shown, the orthographic projection of the first type sixteenth via structure V716 on the base substrate is located within the range of the orthographic projection of the second electrode 2041 on the base substrate, the first type sixteenth via structure V716 exposes the surface of the second electrode 2041, and the first type sixteenth via structure V716 is configured to connect the structure in the subsequently formed first conductive metal layer to the second electrode 2041.

[0277] For example, Figure 18 and 19 As shown, the orthographic projection of the first type seventeenth via structure V717 on the base substrate is located within the range of the orthographic projection of the first initialization signal line 2034 on the base substrate, the first type seventeenth via structure V717 exposes the surface of the first initialization signal line 2034, and the first type seventeenth via structure V717 is configured to connect the structure in the subsequently formed first conductive metal layer to the first initialization signal line 2034.

[0278] For example, Figure 20 A schematic diagram of the planar structure of an etching stop layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 21A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etching stop layer in a display substrate provided in at least one embodiment of the present disclosure.

[0279] For example, Figure 20 and Figure 21 As shown, a plurality of second-type via structures are provided in the etch stop layer 208 , and the first conductive metal layer and the second semiconductor layer 205 involved subsequently are electrically connected through the second-type via structures.

[0280] It should be noted that although the term "etch stop layer" is used to represent multiple second-type via structures, the etch stop layer actually represents another portion of the via structure that passes through the insulating layer disposed between adjacent layers among the light shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the insulating layer and the etch stop layer between the adjacent layers can be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The insulating layer and the etch stop layer can be single-layer, multi-layer, or composite layers. For example, the interlayer insulating layer and the etch stop layer can be disposed on the same layer.

[0281] For example, Figure 20 and 21 As shown, the multiple second-type via structures in each circuit unit include: a second-type first via structure V81, a second-type second via structure V82, a second-type third via structure V83, a second-type eighteenth via structure V818 and a second-type nineteenth via structure V819.

[0282] For example, combined with Figure 19 、 Figure 20 and Figure 21 As shown, the orthographic projection of the second-type first via structure V81 on the substrate is located within the range of the orthographic projection of the first area of ​​the first active layer on the substrate, the second-type first via structure V81 exposes the surface of the first area of ​​the first active layer, and the second-type first via structure V81 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the first active layer.

[0283] For example, combined with Figure 19 、 Figure 20 and Figure 21As shown, the orthographic projection of the second-type second via structure V82 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, and the second-type second via structure V82 exposes the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second-type second via structure V82 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the first active layer (also the first area of ​​the second active layer).

[0284] For example, combined with Figure 19 、 Figure 20 and Figure 21 As shown, the orthographic projection of the second-type third via structure V83 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the second-type third via structure V83 exposes the surface of the second region of the second active layer, and the second-type third via structure V83 is configured to connect the structure in the subsequently formed first conductive metal layer with the second region of the second active layer.

[0285] For example, combined with Figure 19 、 Figure 20 and Figure 21 As shown, the orthographic projection of the second type eighteenth via structure V818 on the base substrate is located within the range of the orthographic projection of the second initialization signal line 2063 on the base substrate, the second type eighteenth via structure V818 exposes the surface of the second initialization signal line 2063, and the second type eighteenth via structure V818 is configured to connect the structure in the subsequently formed first conductive metal layer to the second initialization signal line 2063.

[0286] For example, combined with Figure 19 、 Figure 20 and Figure 21 As shown, the positive projection of the second-type nineteenth via structure V819 on the base substrate is located within the range of the positive projection of the third initialization signal line 2064 on the base substrate, the second-type nineteenth via structure V819 exposes the surface of the third initialization signal line 2064, and the second-type nineteenth via structure V819 is configured to connect the structure in the subsequently formed first conductive metal layer to the third initialization signal line 2064.

[0287] For example, Figure 22 A schematic diagram of the planar structure of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 23 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, and a first conductive metal layer in a display substrate provided for at least one embodiment of the present disclosure.

[0288] For example, Figure 22 and Figure 23 As shown, the first conductive metal layer 209 of each circuit unit can be referred to as a first source-drain metal layer (SD1). The first conductive metal layer 209 of each circuit unit includes at least a first connection electrode 91, a second connection electrode 92, a third connection electrode 93, a fourth connection electrode 94, a fifth connection electrode 95, a sixth connection electrode 96, a seventh connection electrode 97, an eighth connection electrode 98, a ninth connection electrode 99, a tenth connection electrode 910, and an eleventh connection electrode 911. The first source-drain metal layer also includes a first data fan-out line 51, a first connection structure 56, a second connection structure 57, and a third connection structure 55.

[0289] For example, in an embodiment of the present disclosure, the material of the first conductive metal layer 209 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first conductive metal layer 209 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The first conductive metal layer 209 can also be a multi-layer alloy structure, such as a multi-layer TiAlTi structure.

[0290] For example, Figure 22 and Figure 23 As shown, the first end of the first connection electrode 91 is connected to the second region of the ninth active layer via a fourteenth first-type via structure V714. The second end of the first connection electrode 91 extends along the second direction Y and is connected to the first electrode plate 2035 via a fifteenth first-type via structure V715. For example, because the first electrode plate 2035 also serves as the gate electrode of the third transistor T3, the first connection electrode 91 causes the gate electrode of the third transistor T3, the second electrode of the ninth transistor T9, and the first electrode plate 2035 to have the same potential, thereby forming a first node N1 in the pixel driving circuit.

[0291] For example, Figure 22 and Figure 23 As shown, the second connection electrode 92 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the second connection electrode 92 is connected to the second region of the second active layer via a second-type third via structure V83. The second end of the second connection electrode 92 extends along the second direction Y and is connected to the second region of the third active layer (also the first region of the sixth active layer) via a first-type fifth via structure V75. For example, the second connection electrode 92 causes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0292] For example, Figure 22 and Figure 23 As shown, the third connection electrode 93 is in a block shape, and is connected to the first region of the fourth active layer through the first type sixth via structure V76 . The third connection electrode 93 is configured to be connected to a subsequently formed data signal line.

[0293] For example, Figure 22 and Figure 23 As shown, the first end of the fourth connection electrode 94 is connected to the first region of the fifth active layer through the first-type seventh via structure V77 .

[0294] For example, Figure 22 and Figure 23 As shown, the fourth connection electrodes 94 of two adjacent circuit units in the first direction X are interconnected as an integral structure, and are connected to the first regions of the fifth active layers of the two circuit units through a shared first-type seventh via structure V77 .

[0295] For example, Figure 22 and Figure 23 As shown, since the fifth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 94 in the current unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 94 is connected to the second electrode plate 2041 of the pixel driving circuit in the current unit row. For example, the fourth connecting electrode 94 in the (n-1)th unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the (n)th unit row, and a second end connected to the second electrode plate 2041 of the pixel driving circuit in the (n-1)th unit row.

[0296] For example, Figure 22 and Figure 23 As shown, the fifth connection electrode 95 is shaped like a strip with a main portion extending along the second direction Y. The first end of the fifth connection electrode 95 is connected to the second region of the fifth active layer via the first-type eighth via structure V78. The second end of the fifth connection electrode 95 extends along the second direction Y and is connected to the second region of the eighth active layer via the first-type eleventh via structure V711. For example, the fifth connection electrode 95 enables the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3 to have the same potential, forming the second node N2 of the pixel driving circuit. In exemplary embodiments, the fifth connection electrode 95 can serve as the second node electrode in the embodiments of the present disclosure.

[0297] For example, Figure 22 and Figure 23As shown, the sixth connecting electrode 96 is in the shape of an elongated strip and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a first-type ninth via structure V79. For example, the sixth connecting electrode 96 is configured to connect to a subsequently formed anode connecting electrode to form a fourth node N4 of the pixel driving circuit.

[0298] For example, Figure 22 and Figure 23 As shown, the seventh connection electrode 97 is in the shape of a strip with a main portion extending along the first direction X. A first end of the seventh connection electrode 97 is connected to the first region of the first active layer via a first-type via structure V81 of the second type, and a second end of the seventh connection electrode 97 is connected to the first initialization signal line 2034 via a seventeenth-type via structure V717 of the first type. For example, the seventh connection electrode 97 connects the first initialization signal line 2034 to the first electrode of the first transistor T1, and the first initialization signal line 2034 can write the transmitted first initialization signal into the first electrode of the first transistor T1.

[0299] For example, Figure 22 and Figure 23 As shown, the eighth connection electrode 98 is in the shape of a strip with a main portion extending along the second direction Y. A first end of the eighth connection electrode 98 is connected to the first region of the seventh active layer via a tenth via structure V710 of the first type, and a second end of the eighth connection electrode 98 is connected to the second initialization signal line 2063 via an eighteenth via structure V818 of the second type. For example, the eighth connection electrode 98 connects the second initialization signal line 2063 to the first electrode of the seventh transistor T7, and the second initialization signal line 2063 can write the transmitted second initialization signal into the first electrode of the seventh transistor T7.

[0300] For example, Figure 22 and Figure 23 As shown, the ninth connection electrode 99 is in a strip shape with a main portion extending along the second direction Y. The ninth connection electrode 99 is connected to the third initialization signal line 2064 through a second-type nineteenth via structure V819.

[0301] For example, Figure 22 and Figure 23As shown, since the eighth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the ninth connecting electrode 99 in the current unit row is connected to the first region of the eighth active layer of the pixel driving circuit in the next unit row, and the second end of the ninth connecting electrode 99 is connected to the third initialization signal line 2064 in the current unit row. For example, for the ninth connecting electrode 99 in the (n-1)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the (n)th unit row, and its second end is connected to the third initialization signal line 2064 in the (n-1)th unit row.

[0302] For example, Figure 22 and Figure 23 As shown, the tenth connection electrode 910 is in the shape of a strip with its main portion extending along the second direction Y. A first end of the tenth connection electrode 910 is connected to the second region of the first active layer (also the first region of the second active layer) via a second-type second via structure V82, and a second end of the tenth connection electrode 910 is connected to the first region of the ninth active layer via a thirteenth-type first via structure V713. For example, the tenth connection electrode 910 connects the second electrode of the first transistor T1, the first electrode of the second transistor T2, and the first electrode of the ninth transistor T9, forming a fifth node N5 of the pixel driving circuit.

[0303] For example, Figure 22 and Figure 23 As shown, the third connection structure 55 can serve as a first initialization signal transfer line. The initialization signal connection line and the first initialization signal line 2034 provided on the second conductive metal layer 212 mentioned later are electrically connected via the first initialization signal transfer line 55.

[0304] For example, Figure 22 and Figure 23 As shown, the first conductive metal layer 209 further includes a second initialization signal adapter line 913 , and the initialization signal connection line and the second initialization signal line 2063 provided on the second conductive metal layer 212 mentioned later are electrically connected via the second initialization signal adapter line 913 .

[0305] For example, the initialization signal connection line is also electrically connected to the third initialization signal line 2064 , so that the initialization signal connection line and the first initialization signal line 2034 , the second initialization signal line 2063 , and the third initialization signal line 2064 are electrically connected to form a mesh initialization signal structure.

[0306] For example, Figure 22 and Figure 23 As shown, the orthographic projection of the first data fan-out line 51 on the base substrate and the orthographic projections of the first initialization signal line 2034 and the second initialization signal line 2063 on the base substrate are spaced apart from each other.

[0307] For example, Figure 22 and Figure 23 As shown, the first data fan-out line 51 covers the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8. The orthographic projection of the first data fan-out line 51 on the substrate overlaps with the orthographic projection of the third initialization signal line 2064 on the substrate. Therefore, the third initialization signal line 2064 can be used to shield the first data fan-out line 51. This routing method avoids the overlap of the first data fan-out line 51 with the first scanning signal line, the light-emitting control signal line, the first initialization signal line, etc., and can reduce the influence of signal jumps on these signal lines on the data signal. Although this routing method has the phenomenon of the third initialization signal line 2064 and the first data fan-out line 51 overlapping, the third initialization signal line 2064 will be used to shield the first data fan-out line 51, thereby minimizing the influence of signal jumps on the third initialization signal line 2064 on the data signal.

[0308] For example, Figure 23 As shown, the fourth scan signal line 2032 is also the first reset control signal line, and the positive projection of the first data fan-out line 51 on the base substrate, the positive projection of the third initialization signal line 2064 on the base substrate and the first reset control signal line 2032 overlap.

[0309] For example, Figure 23 As shown, the orthographic projections of the second plate 2041 of the storage capacitor, the first shielding line 2042 and the second shielding line 2043 on the substrate are spaced apart from the orthographic projection of the first data fan-out line 51 on the substrate, thereby avoiding the first shielding line 2042 and the second shielding line 2043 from affecting the jump of the data signal.

[0310] For example, Figure 24 A schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 25 A schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 26 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate provided for at least one embodiment of the present disclosure.

[0311] For example, Figure 24 and Figure 25 As shown, a plurality of third-type via structures are provided in the passivation layer 210 and the first planarization layer 211 , and the second conductive metal layer and the first conductive metal layer involved subsequently are electrically connected through the third-type via structures.

[0312] For example, Figures 24-26 As shown, the multiple third-type via structures in each circuit unit include: the third-type twenty-second via structure V922, the third-type twenty-third via structure V923, the third-type twenty-fourth via structure V924, the third-type twenty-fifth via structure V925, the third-type twenty-sixth via structure V926 and the third-type twenty-eighth via structure V928.

[0313] For example, Figures 24-26 As shown, the orthographic projection of the third type twenty-second via structure V922 on the base substrate is located within the range of the orthographic projection of the fourth connecting electrode 94 on the base substrate, the first flat layer of the passivation layer in the third type twenty-second via structure V922 is etched away to expose the surface of the fourth connecting electrode 94, and the third type twenty-second via structure V922 is configured to connect the subsequently formed power supply voltage signal line to the fourth connecting electrode 94.

[0314] For example, Figures 24-26 As shown, the orthographic projection of the twenty-third via structure V923 of the third type on the substrate is located within the range of the orthographic projection of the third connecting electrode 93 on the substrate, the passivation layer and the first flat layer in the twenty-third via structure V923 of the third type are etched away to expose the surface of the third connecting electrode 93, and the twenty-third via structure V923 of the third type is configured to connect the subsequently formed data signal line to the third connecting electrode 93.

[0315] For example, Figures 24-26 As shown, the orthographic projections of the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category on the substrate are located within the range of the orthographic projections of the eleventh connecting electrode 911 on the substrate, the passivation layer and the first flat layer within the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category are etched away to expose the surface of the eleventh connecting electrode 911, and the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category are configured to connect the subsequently formed second conductive metal layer to the eleventh connecting electrode 911.

[0316] For example, Figures 24-26 As shown, the orthographic projection of the twenty-sixth via structure V926 of the third type on the substrate is located within the range of the orthographic projection of the twelfth connecting electrode 912 on the substrate, the passivation layer and the first flat layer within the twenty-sixth via structure V926 of the third type are etched away to expose the surface of the twelfth connecting electrode 912, and the twenty-sixth via structure V926 of the third type is configured to connect the subsequently formed second conductive metal layer to the twelfth connecting electrode 912.

[0317] For example, Figures 24-26 As shown, the orthographic projection of the twenty-eighth via structure V928 of the third type on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 96 on the substrate, the passivation layer and the first flat layer within the twenty-eighth via structure V928 of the third type are etched away to expose the surface of the sixth connecting electrode 96, and the twenty-eighth via structure V928 of the third type is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 96.

[0318] For example, the process of forming the pattern of the passivation layer and the first planarization layer includes: coating a passivation layer film and a first planarization layer film on a substrate substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer and a first conductive metal layer is formed, patterning the passivation layer film and the first planarization layer film using a patterning process to form a passivation layer and a first planarization layer covering the pattern of the first conductive metal layer, and a plurality of third-type via structures are arranged on the passivation layer and the first planarization layer.

[0319] For example, the first planarization layer may be formed of an organic material, such as resin, etc. The passivation layer may be formed of an inorganic insulating material, such as silicon nitride, silicon oxynitride, or silicon dioxide.

[0320] For example, Figure 27 A schematic diagram of the planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 28 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate provided for at least one embodiment of the present disclosure.

[0321] For example, Figure 27 and Figure 28 As shown, the second conductive metal layer 212 of each circuit unit includes: a power supply voltage signal line 212a, a data signal line 212b, an anode connection electrode 212c, an initialization signal connection line 212d and a second data fan-out line 212e. The second conductive metal layer 212 can serve as a second source and drain metal (SD2) layer.

[0322] For example, Figure 27 and Figure 28As shown, the shape of the power supply voltage signal line 212a is a straight line or a broken line with the main part extending along the second direction Y. The power supply voltage signal line 212a is connected to the fourth connection electrode 94 through the third type twenty-second via structure V922. The fourth connection electrode 94 is respectively connected to the first electrode of the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor, thereby realizing that the power supply voltage signal line 212a writes the first power supply signal into the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor.

[0323] For example, Figure 27 and Figure 28 As shown, the power supply voltage signal line 212a can be a zigzag line with non-uniform width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the power supply voltage signal line and the data signal line.

[0324] For example, Figure 27 and Figure 28 As shown, the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the power supply voltage signal line 212a can cover the first active layer and the second active layer, and can block the light emitted by the light-emitting element and the light reflected by the film layer from irradiating the first transistor T1 and the second transistor T2 of the oxide, thereby preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0325] For example, Figure 27 and Figure 28 As shown, the positive projection of the power supply voltage signal line 212a on the base substrate at least partially overlaps with the positive projection of the first connection electrode 91 on the base substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby avoiding the influence of data voltage jumps and other signals on the potential of the first node N1, and improving the driving performance of the pixel driving circuit.

[0326] For example, Figure 27 and Figure 28 As shown, the positive projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the positive projections of the second connection electrode 92 and the tenth connection electrode 910 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on various nodes in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the node potential, and improve the driving performance of the pixel driving circuit.

[0327] For example, Figure 27 and Figure 28 As shown, the data signal line 212b can be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y. The data signal line 212b is connected to the third connection electrode 93 via a twenty-third via structure V923 of the third type. Since the third connection electrode 93 is connected to the first region of the fourth active layer through the via, the data signal line 212b is connected to the first electrode of the fourth transistor T4. The data signal line 212b can write a data signal into the first electrode of the fourth transistor T4.

[0328] For example, Figure 27 and Figure 28 As shown, the anode connection electrode 212c is in the shape of an elongated strip and is connected to the sixth connection electrode 96 via the third type twenty-eighth via structure V928. The anode connection electrode 212c is configured to be connected to a subsequently formed anode. Because the sixth connection electrode 96 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting element to emit light.

[0329] For example, the process of forming the second conductive metal layer includes: depositing a second conductive metal film on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer and a first planarization layer is formed, and patterning the second conductive metal film using a patterning process to form a second conductive metal layer arranged on the first planarization layer.

[0330] For example, the material of the second conductive metal layer 212 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second conductive metal layer 212 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The second conductive metal layer 212 can also be a multi-layer alloy structure, such as a multi-layer TiAlTi structure.

[0331] For example, Figure 27 and Figure 28As shown, the initialization signal connection line 212d is electrically connected to the first initialization signal transfer line 55 through a second via structure V926 provided in the first insulating layer, and is electrically connected to the second initialization signal transfer line 913 through another second via structure V926 provided in the first insulating layer. For example, the first insulating layer includes a passivation layer and a first planarization layer, and the second via structure is a hole structure that penetrates the passivation layer and the first planarization layer. For example, in the second direction Y, the second via structure V926 and the first via structure V928 mentioned later are respectively provided on both sides of the first data fan-out line 51. This can increase the distance between the first via structure V928 and the second via structure V926, thereby reducing the length of the connection line connecting the first initialization signal line and the second initialization signal line to the network, which is beneficial to reducing the load of the first initialization signal line and the second initialization signal line. In addition, due to the downward position of the first via structure, the first via structure corresponding to the N4 node can be moved outward, thereby increasing the distance between the first via structure and the corresponding anode, thereby improving the flatness of the anode in the corresponding sub-pixel.

[0332] For example, Figure 27 and Figure 28 As shown, the second data fan-out line 212e is disposed between two adjacent data signal lines 212b.

[0333] For example, Figure 27 and Figure 28 As shown, two adjacent initialization signal connection lines 212d, two adjacent anode connection electrodes 212c, two adjacent power supply voltage signal lines 212a, and two adjacent data signal lines 212b are all axially symmetrical about the second data fan-out line 212e.

[0334] For example, Figure 29 A schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 30 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate provided for at least one embodiment of the present disclosure.

[0335] For example, Figure 29 and Figure 30As shown, a second planarization layer 213 is disposed over the entire substrate. The second planarization layer 213 has a plurality of fourth-type via structures 213a / 213b / 213c / 213d. The fourth-type via structures 213a / 213b / 213c / 213d expose anode connection electrodes. These fourth-type via structures 213a / 213b / 213c / 213d enable subsequent anodes to be connected to the anode connection electrodes in the second conductive metal layer.

[0336] For example, the second planarization layer may be formed of an organic material, such as a resin.

[0337] For example, the fourth type via structure 213 a / 213 b / 213 c / 213 d may serve as an anode connection hole. The first insulating layer includes the second planarization layer 212 , and the fourth type via structure 213 a / 213 b / 213 c / 213 d is disposed in the second planarization layer 212 .

[0338] For example, Figure 31 A schematic diagram of the planar structure of an anode layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 32 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer and an anode layer in a display substrate provided for at least one embodiment of the present disclosure.

[0339] For example, Figure 31 and Figure 32 As shown, an anode layer 214 is disposed on the second planarization layer 213. The anode layer 214 includes a plurality of anode electrodes 214a / 214b / 214c / 214d. Anode electrode 214a may be an electrode corresponding to the first subpixel P1, anode electrode 214b may be an electrode corresponding to the second subpixel P2, anode electrode 214c may be an electrode corresponding to the third subpixel P3, and anode electrode 214d may be an electrode corresponding to the fourth subpixel P4. Anode electrode 214a, anode electrode 214b, anode electrode 214c, and anode electrode 214d are connected to the anode connection electrode in the second conductive metal layer through fourth-type via structures 213a, 213b, 213c, and 213d, respectively.

[0340] For example, in one example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 are green sub-pixels (G) that emit green light, and the third sub-pixel P3 is a blue sub-pixel (B) that emits blue light. The embodiments of the present disclosure are not limited to this.

[0341] For example, combined with Figures 2 to 32 The display substrate includes: a base substrate 101, a driving circuit layer 102 on the base substrate 101, the driving circuit layer 102 including a pixel driving circuit, and a plurality of light-emitting elements are arranged on the side of the pixel driving circuit away from the base substrate 101; the pixel driving circuit includes a first conductive metal layer 209, a first insulating layer 210 / 211, and a second conductive metal layer 212 arranged in a stacked manner, the second conductive metal layer 212 including an initialization signal connection line 212d, an anode connection electrode 212c, and a power supply electrode arranged in a first direction X. The voltage signal line 212a, the initialization signal connection line 212d, the anode connection electrode 212c and the power supply voltage signal line 212a all extend along the second direction Y intersecting the first direction X, and the anode connection electrode 212c is electrically connected to the first conductive metal layer 209 through a first via structure provided in the first insulating layer 210 / 211; the plurality of light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and the orthographic projection of the first anode on the base substrate 101 does not overlap with the orthographic projection of the first via structure on the base substrate 101. The first via structure is Figure 25 The twenty-eighth via structure V928 of the third type in the third type via structure in the first planarization layer.

[0342] For example, the first anode can be the anode corresponding to the red sub-pixel, and the orthographic projection of the anode corresponding to the red sub-pixel on the base substrate 101 does not overlap with the orthographic projection of the first via structure V928 on the base substrate 101, that is, the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the red sub-pixel.

[0343] For example, in one embodiment, the plurality of light-emitting elements includes a second light-emitting element, the second light-emitting element includes a second anode, and the orthographic projection of the second anode on the base substrate partially overlaps with the orthographic projection of the first via structure V928 on the base substrate. For example, the second anode may be the anode corresponding to the blue sub-pixel, and the orthographic projection of the anode corresponding to the blue sub-pixel on the base substrate 101 partially overlaps with the orthographic projection of the first via structure V928 on the base substrate 101, that is, a portion of the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the blue sub-pixel.

[0344] For example, in one example, the area where the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the first via structure V928 on the substrate is 5% to 20% of the area of ​​the first via structure, that is, the area covered by the second anode on the first via structure V928 does not exceed 1 / 5 of the area of ​​the first via structure V928.

[0345] For example, the second conductive metal layer 212 also includes a second data fan-out line 212e, which extends along the second direction Y and has a break in the middle area. The second data fan-out line 212e is connected to the eleventh connecting electrode 911 at one end of the break through the third type twenty-fourth via structure V924 and the eleventh connecting electrode 911 at the other end of the break through the third type twenty-fifth via structure V925 and the eleventh connecting electrode 911.

[0346] Figure 33 This is a schematic diagram of an equivalent circuit of another pixel driving circuit provided in at least one embodiment of the present disclosure. Figure 34 for Figure 33 The driving timing diagram of the pixel driving circuit is shown in FIG. Figure 33 As shown, the pixel driving circuit has an 8T1C structure and may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C. Each pixel driving circuit is respectively connected to 12 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a fifth scanning signal line S5, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a power supply voltage signal line VDD).

[0347] For example, in an embodiment of the present disclosure, Figure 33 The connection structure of the first transistor T1 to the eighth transistor T8 and the storage capacitor C in the pixel driving circuit shown is similar to Figure 4 The structure of the pixel driving circuit shown is basically the same, except that Figure 33 The ninth transistor is not provided in the pixel driving circuit shown, and thus the first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3 and the first end of the storage capacitor C, that is, the second electrode of the first transistor T1 is connected to the first node N1, and the first electrode of the second transistor T2 is connected to the first node N1.

[0348] For example, Figure 33 As shown, in the embodiment of the present disclosure, the first transistor T1 and the second transistor T2 in the pixel driving circuit can be oxide transistors (N-type transistors), and the third transistor T3 to the eighth transistor T8 can be low-temperature polysilicon transistors (P-type transistors).

[0349] For example, Figure 34 for Figure 33 The driving timing diagram of the pixel driving circuit shown in FIG. Figure 34 The working process of the pixel driving circuit shown is similar to Figure 4The working process of the pixel driving circuit shown is basically the same, except that Figure 34 During the operation of the pixel driving circuit shown, in the second phase A2, the second scan signal line S2 is a high-level signal. The first transistor T1 is turned on, causing the signal of the first initial signal line INIT1 to be supplied to the first node N1 to initialize (reset) the first node N1. In the fifth phase A5, before the seventh transistor T7 and the eighth transistor T8 are turned on, the second scan signal line S2 is a low-level signal for a short period of time. The fourth transistor T4 is turned on again, causing the data voltage of the next unit row to reset the second node N2 and the third node N3.

[0350] For example, Figure 33 As shown, the pixel driving circuit includes a storage capacitor and multiple transistors, the storage capacitor may include a first electrode plate and a second electrode plate arranged opposite to each other, the multiple transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor and an eighth transistor T8 as a third initialization transistor, wherein the first transistor T1 and the second transistor T2 are oxide transistors, and the third transistor T3 to the eighth transistor T8 are low-temperature polysilicon transistors.

[0351] For example, Figure 35 This is a schematic diagram of the planar structure of a light shielding layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 35 As shown, the light shielding layer 201 may be a bottom light shielding metal (BSM) layer.

[0352] For example, Figure 35 As shown, the pattern of the light-shielding layer includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and a light-shielding electrode 2013, with the plurality of light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is roughly rectangular, and the corners of the rectangle may be chamfered. The first light-shielding connecting line 2011 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first light-shielding connecting line 2011 may be disposed on either side of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013. The second light-shielding connecting line 2012 may be in the shape of a straight line or a zigzag line extending along the first direction X. The second light-shielding connecting line 2012 may be disposed on either side of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013, thereby forming a mesh-like pattern on the light-shielding layer.

[0353] For example, Figure 35 As shown, in a unit row, the second light-shielding connection lines 2012 in two adjacent circuit units in the first direction X can be connected to form an interconnected integrated structure.

[0354] For example, in other embodiments of the present disclosure, in a unit column, the first shading connection lines 2011 in two adjacent circuit units in the second direction Y can be connected to form an integrated structure that is interconnected, that is, the shading layers in the unit row and the unit column are connected into one, thereby ensuring that the shading layers in the display substrate have the same electric potential, which is beneficial to improving the display uniformity of the subsequently formed display panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.

[0355] For example, forming the pattern of the light shielding layer includes: depositing a light shielding layer thin film on the base substrate, and patterning the light shielding layer thin film through a patterning process to form a light shielding layer pattern. The material of the light shielding layer can be a light shielding metal material.

[0356] It should be noted that the "patterning process" mentioned in the embodiments of the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes; for organic materials, it includes coating of organic materials, mask exposure and development and other processes. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition; coating can be carried out by any one or more of spraying, spin coating and inkjet printing; etching can be carried out by any one or more of dry etching and wet etching, and the embodiments of the present disclosure are not limited to this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". In the embodiments of the present disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the main surface of the display substrate. In the embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B. This will not be further described below.

[0357] For example, Figure 36This is a schematic diagram of the planar structure of the first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 36 As shown, the first semiconductor layer 202 may form the third active layer 23 of the third transistor T3 to the eighth active layer 28 of the eighth transistor T8 .

[0358] For example, Figure 36 As shown, the third active layer 23 , the fourth active layer 24 , the fifth active layer 25 , the sixth active layer 26 and the seventh active layer 27 are interconnected as an integral structure, and the eighth active layer 28 is provided separately.

[0359] For example, the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), and the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor).

[0360] For example, Figure 37 This is a schematic diagram of a planar structure of a stack of a light shielding layer and a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 37 As shown, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the substrate. The light-shielding electrode 2013 serves as a light-shielding layer of the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0361] For example, in an embodiment of the present disclosure, in the pixel driving circuit of the present circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the present circuit unit in the first direction X, and the sixth active layer 26 is located on a side of the third active layer 23 in the present circuit unit in the opposite direction of the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the present circuit unit in the second direction Y.

[0362] For example, Figure 36 and Figure 37 As shown, the shape of the third active layer 23 can be an inverted "Ω" shape, the shapes of the fourth active layer 24, the fifth active layer 25 and the sixth active layer 26 can be strip shapes with the main part extending along the second direction Y, the shape of the seventh active layer 27 can be an inverted "L" shape, and the shape of the eighth active layer 28 can be an "L" shape.

[0363] For example, Figure 36 As shown, the third to eighth active layers 23 to 28 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 25a of the seventh active layer 27, the first region 28a of the eighth active layer 28, and the second region 28b of the eighth active layer 28 may be separately provided.

[0364] For example, Figure 36 As shown, in a unit column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit unit can be set in the circuit unit of the previous unit row, and the third active layer 23, the fourth active layer 24, the sixth active layer 26 and the seventh active layer 27 can be set in this circuit unit.

[0365] For example, Figure 36 As shown, the fifth active layer 25 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the first direction X of the sixth active layer 26 of the pixel driving circuit in the circuit unit of the previous unit row, so that the fifth active layer 25 and the sixth active layer 26 of the pixel driving circuit in the two unit rows can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of the current unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the n-th unit row is arranged in the circuit unit of the n-1-th unit row, so that the fifth active layer 25 of the pixel driving circuit in the n-th unit row and the sixth active layer 26 of the pixel driving circuit in the n-1-th unit row can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the n-th unit row and the sixth transistor T6 of the n-1-th unit row.

[0366] For example, in at least one embodiment of the present disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the seventh active layer 28 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the current unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is arranged in the circuit unit of the n-1th unit row, so that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the n-1th unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the n-1th unit row and the eighth transistor T8 of the nth unit row.

[0367] For example, in at least one embodiment of the present disclosure, the first semiconductor layer 202 is formed of polycrystalline silicon (p-Si), that is, the third transistor T3 to the eighth transistor T8 are LTPS transistors.

[0368] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor film, and then patterning the first semiconductor film through a patterning process. For example, the process of patterning the first semiconductor film through the patterning process includes: first forming an amorphous silicon (A-Si) film, dehydrogenating the A-Si film, crystallizing the dehydrogenated A-Si film to form a polycrystalline silicon film, and then patterning the polycrystalline silicon film to form the pattern of the first semiconductor layer.

[0369] For example, Figure 38 A schematic diagram of the planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 39 This is a schematic planar structural diagram of a stack of a light shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 38 As shown, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scanning signal line 2031, a fourth scanning signal line 3032, a light emitting control signal line 2033, a first initialization signal line 2034 and a first plate 2035 of a storage capacitor.

[0370] For example, Figure 39 As shown, the first electrode plate 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode plate 2035 can simultaneously serve as a plate of the storage capacitor and the gate electrode of the third transistor T3.

[0371] For example, Figure 39 As shown, the orthographic projection of the first electrode plate 2035 on the base substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the base substrate.

[0372] For example, Figure 39 As shown, the shape of the second scanning signal line 2031 is a straight line or a broken line with the main part extending along the first direction X. The second scanning signal line 2031 is located on the side opposite to the second direction Y of the first electrode 2035. The area where the second scanning signal line 2031 overlaps with the fourth active layer 24 can be used as the gate electrode of the fourth transistor T4.

[0373] For example, Figure 39 As shown, the fourth scan signal line 2032 is shaped as a straight line or a zigzag line with its main portion extending along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode 2035 in the second direction Y. The area where the fourth scan signal line 2032 of the current unit row overlaps with the seventh active layer 27 of the pixel driving circuit in the current unit row serves as the gate electrode of the seventh transistor T7 in the current unit row. The area where the fourth scan signal line 2032 of the current unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the (n)th unit row can serve as the gate electrode of the eighth transistor T8 in the (n)th unit row.

[0374] For example, Figure 39 As shown, the light-emitting control signal line 2033 is in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode 2035 and the fourth scanning signal line 2032. The area where the light-emitting control signal line 2033 of the current unit row overlaps with the sixth active layer 26 of the pixel driving circuit in the current unit row can serve as the gate electrode of the sixth transistor T6 of the current unit row, and the area where the light-emitting control signal line 2033 of the current unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can serve as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the n-1th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the n-1th unit row can serve as the gate electrode of the sixth transistor T6 in the n-1th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the fifth transistor T5 in the nth unit row.

[0375] For example, Figure 39 As shown, the shape of the first initialization signal line 2034 is a straight line or a broken line with the main part extending along the first direction X. The first initialization signal line 2034 is located on the side of the second scanning signal line 2031 away from the first electrode 2035. The first initialization signal line 2031 is configured to be connected to the first area of ​​the first active layer mentioned later.

[0376] For example, Figure 39 As shown, the second scanning signal line 2031, the fourth scanning signal line 2032, the light-emitting control signal line 2033 and the first initialization signal line 2034 have different widths in the second direction Y. The second scanning signal line 2031, the fourth scanning signal line 2032, the light-emitting control signal line 2033 and the first initialization signal line 2034 only need to facilitate the layout of the pixel structure and reduce the parasitic capacitance between the signal lines. The embodiments of the present disclosure are not limited to this.

[0377] For example, Figure 39 As shown, the second scanning signal line 2031, the fourth scanning signal line 2032 and the light-emitting control signal line 2033 include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer. The width of the signal line in the area overlapping with the first semiconductor layer can be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.

[0378] For example, Figure 39 As shown, after the pattern of the first gate metal layer is formed, the first gate metal layer can be used as a blocking layer to conduct the first semiconductor layer. The first semiconductor layer in the area blocked by the first gate metal layer forms the channel area of ​​the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not blocked by the first gate metal layer is conducted, that is, the first electrode 2035 and the first and second areas of the third active layer 23 to the eighth active layer 28 are all conducted.

[0379] For example, in an embodiment of the present disclosure, the process of forming a first gate metal layer includes: depositing a second insulating layer film and a first conductive metal film in sequence on a base substrate on which a light-shielding layer and a first semiconductor layer are formed, patterning the first conductive metal film through a patterning process to form a second insulating layer covering the pattern of the first semiconductor layer, and a pattern of the first gate metal layer arranged on the second insulating layer. For example, the first gate metal layer can be referred to as a GATE1 layer.

[0380] For example, in an embodiment of the present disclosure, the material of the first gate metal layer 203 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first gate metal layer 203 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0381] For example, Figure 40 A schematic diagram of the planar structure of a second gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 41 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, and a second gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the second gate metal layer may be referred to as a GATE2 layer.

[0382] For example, in at least one embodiment of the present disclosure, the pattern of the second gate metal layer 204 of each circuit unit includes: a second plate 2041 of the storage capacitor, a first shielding line 2042 and a second shielding line 2043 .

[0383] For example, Figure 40 and 41 As shown, the outline of the second plate 2041 is rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate 2041 on the substrate at least partially overlaps with the orthographic projection of the first plate 2035 on the substrate. The second plate 2041 can serve as another plate of the storage capacitor. The first plate 2035 and the second plate 2041 constitute the storage capacitor of the pixel driving circuit.

[0384] For example, Figure 40 and Figure 41 As shown, the second electrode plate 2041 is provided with an opening 2041a. The opening 2041a can be rectangular in shape and located in the middle region of the second electrode plate 2041, so that the second electrode plate 2041 forms a ring structure. The opening 2041a exposes the third insulating layer covering the first electrode plate 2035, and the orthographic projection of the first electrode plate 2035 on the base substrate covers the orthographic projection of the opening 2041a on the base substrate.

[0385] For example, Figure 40 and Figure 41 As shown, the second electrode plate 2041 includes an electrode block 2041b. The electrode block 2041b may be in the shape of a strip extending along the first direction X.

[0386] For example, Figure 40 and Figure 41As shown, the shape of the first shielding line 2042 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding line 2042 can be located between the first electrode 2035 and the second scanning signal line 2031. The first shielding line 2042 is configured as a light shielding layer of the second transistor T2 mentioned later, shielding the channel region of the second transistor T2, ensuring the electrical performance of the second transistor T2 whose active layer is formed by metal oxide, and is configured as a bottom gate electrode of the second transistor T2.

[0387] For example, Figure 40 and Figure 41 As shown, the shape of the second shielding line 2043 is a straight line or a broken line with the main part extending along the first direction X. The second shielding line 2043 is located between the second scanning signal line 2031 and the first initialization signal line 2034. The second shielding line 2043 is configured as a light shielding layer of the first transistor T1 mentioned later, shielding the channel region of the first transistor T1, ensuring the electrical performance of the first transistor T1 whose active layer is formed by metal oxide, and is also configured as the bottom gate electrode of the first transistor T1.

[0388] For example, Figure 40 and Figure 41 As shown, the first shielding line 2042 and the second shielding line 2043 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.

[0389] For example, the process of forming the pattern of the second gate metal layer includes: depositing a third insulating film and a second metal conductive film in sequence on a base substrate on which a light-shielding layer, a first semiconductor layer and a first gate metal layer are formed with patterns, and patterning the second conductive metal film using a patterning process to form a third insulating layer covering the first gate metal layer, and a pattern of the second gate metal layer arranged on the third insulating layer.

[0390] For example, in an embodiment of the present disclosure, the material of the second gate metal layer 204 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second gate metal layer 204 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0391] For example, Figure 42 A schematic diagram of the planar structure of a second semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 43This is a schematic plan view of the stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer in a display substrate according to at least one embodiment of the present disclosure. For example, the first active layer of a first transistor T1 and the second active layer of a second transistor T2 are disposed on the second semiconductor layer.

[0392] For example, Figure 42 and Figure 43 As shown, the pattern of the second semiconductor layer 205 of each circuit unit includes at least a first active layer 21 of the first transistor T1 and a second active layer 22 of the second transistor T2.

[0393] For example, Figure 42 and Figure 43 As shown, the shape of the first active layer 21 and the second active layer 22 is a strip shape with the main part extending along the second direction Y, the orthographic projection of the first active layer 21 on the substrate at least partially overlaps with the orthographic projection of the second shading line 2043 on the substrate, and the orthographic projection of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the first shading line 2042 on the substrate.

[0394] For example, Figure 42 and Figure 43 As shown, the first region 21a of the first active layer 21 is located on the side of the second shading line 2043 away from the second electrode 2041, the second region 22b of the second active layer 22 is located on the side of the first shading line 2042 close to the second electrode 2041, the second region 21b of the first active layer 21 is connected to the first region 22a of the second active layer 22, and the second region 21b of the first active layer 21 serves as the first region 22a of the second active layer 22.

[0395] For example, Figure 42 and Figure 43 As shown, the first active layer 21 and the second active layer 22 are an integrated structure connected to each other.

[0396] For example, Figure 43 As shown, the second semiconductor layer 205 is formed of a metal oxide material, that is, the first transistor T1 and the second transistor T2 are metal oxide thin film transistors. For example, in the embodiment of the present disclosure, the second semiconductor thin film can be formed of a metal oxide material such as indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0397] For example, the process of forming the pattern of the second semiconductor layer 205 includes: depositing an insulating layer film and a second semiconductor film in sequence on a base substrate having a light-shielding layer, a first semiconductor layer, a first gate metal layer and a second gate metal layer, patterning the second semiconductor film through a patterning process to form an insulating layer covering the base substrate, and a pattern of the second semiconductor layer arranged on the insulating layer.

[0398] For example, Figure 44 A schematic planar structural diagram of a third gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 45 A schematic plan view of a stacked structure of a light shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, and a third gate metal layer in a display substrate according to at least one embodiment of the present disclosure. For example, the third gate metal layer may be referred to as a GATE3 layer.

[0399] For example, Figure 44 and Figure 45 As shown, the pattern of the third gate metal layer 206 of each circuit unit includes at least: a first scanning signal line 2061, a third scanning signal line 2062, a second initialization signal line 2063 and a third initialization signal line 2064. Figure 45 As shown, the third gate metal layer 206 also includes a third scanning signal line 2062 and a first scanning signal line 2061 arranged on the side of the third initialization signal line 2064 close to the second initialization signal line 2063, the orthographic projection of the first scanning signal line 2061 on the substrate overlaps with the orthographic projection of the first shielding line 2042 on the substrate, and the orthographic projection of the third scanning signal line 2062 on the substrate overlaps with the orthographic projection of the second shielding line 2043 on the substrate.

[0400] For example, Figure 44 and Figure 45 As shown, the shape of the first scanning signal line 2061 is a straight line or a broken line with the main part extending along the first direction X. The first scanning signal line 2061 is located on the side of the first electrode 2035 away from the second scanning signal line 2031. The area where the first scanning signal line 2061 overlaps with the first active layer 21 can serve as the gate electrode of the first transistor T1.

[0401] For example, Figure 44 and Figure 45As shown, the orthographic projection of the first scanning signal line 2061 on the substrate at least partially overlaps with the orthographic projection of the first shielding line 2042 on the substrate, and the first scanning signal line 2061 and the first shielding line 2042 are connected to the same signal source, so that the first shielding line 2042 serves as the bottom gate electrode of the first transistor T1, and the first scanning signal line 2061 serves as the top gate electrode of the first transistor T1, so as to form a first transistor T1 with a dual-gate structure.

[0402] For example, Figure 44 and Figure 45 As shown, the shape of the third scanning signal line 2062 is a straight line or a broken line with the main part extending along the first direction X. The third scanning signal line 2062 is located on the side of the second scanning signal line 2031 away from the first scanning signal line 2061, and the area where the third scanning signal line 2062 overlaps with the second active layer serves as the gate electrode of the second transistor T2.

[0403] For example, Figure 44 and Figure 45 As shown, the positive projection of the third scanning signal line 2062 on the substrate substrate at least partially overlaps with the positive projection of the second shielding line 2043 on the substrate substrate. The third scanning signal line 2062 and the second shielding line 2043 can be connected to the same signal source, so that the second shielding line 2043 serves as the bottom gate electrode of the second transistor T2, and the third scanning signal line 2062 serves as the top gate electrode of the second transistor T2, thereby forming a second transistor T2 with a dual-gate structure.

[0404] For example, Figure 44 and Figure 45 As shown, the shape of the second initialization signal line 2063 is a straight line or a broken line with the main part extending along the first direction X. The second initialization signal line 2063 is located on the side of the third scanning signal line 2062 away from the second electrode 2041. The second initialization signal line 2063 of this unit row is configured to be connected to the first area 27a of the seventh active layer 27 of the pixel driving circuit in the circuit unit of this unit row.

[0405] For example, Figure 45 As shown, the positive projection of the third initialization signal line 2064 on the substrate at least partially overlaps with the positive projection of the fourth scanning signal line 2032 on the substrate, so that the third initialization signal line 2064 with a constant potential can effectively shield the influence of the voltage jump of the fourth scanning signal line 2032 on the pixel driving circuit.

[0406] For example, Figure 45As shown, the second initialization signal line 2063 is in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The second initialization signal line 2063 is located between the second electrode plate 2041 and the third initialization signal line 2064. The third initialization signal line 2064 of the current unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the next unit row. For example, the third initialization signal line 2064 of the (n-1)th unit row is configured to connect to the first region of the eighth active layer 28 of the pixel driving circuit in the circuit unit of the nth unit row.

[0407] For example, in an embodiment of the present disclosure, the process of forming a pattern of the third gate metal layer 206 includes: on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, and a second semiconductor layer is formed, depositing an insulating layer film and a third gate metal film in sequence, and patterning the third gate metal film using a patterning process to form an insulating layer covering the second semiconductor layer, and a pattern of the third gate metal layer arranged on the insulating layer.

[0408] For example, in an embodiment of the present disclosure, the material of the third gate metal layer 206 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The third gate metal layer 206 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo.

[0409] For example, Figure 44 and Figure 45 As shown, the third gate metal layer 206 is disposed between the first conductive metal layer mentioned later and the first gate metal layer 203 , and is also disposed on a side of the first conductive metal layer mentioned later away from the second conductive metal layer.

[0410] For example, Figure 46 A schematic diagram of the planar structure of an interlayer insulating layer of a display substrate provided in at least one embodiment of the present disclosure. Figure 47 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer in a display substrate provided in at least one embodiment of the present disclosure.

[0411] For example, Figure 46 and Figure 47 As shown, a plurality of first-type via structures are provided in the interlayer insulating layer 207 , and the first conductive metal layer and the first semiconductor layer 202 involved subsequently are electrically connected through the first-type via structures.

[0412] It should be noted that although the term "interlayer insulating layer" is used to represent multiple first-type via structures, the interlayer insulating layer actually represents a portion of the via structures that pass through multiple insulating layers disposed between adjacent layers among the light-shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the insulating layers between the adjacent layers and the interlayer insulating layer may be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The insulating layers and interlayer insulating layer may be single-layer, multi-layer, or composite layers.

[0413] For example, Figure 46 As shown, the multiple first-class via structures in each circuit unit include at least: a first-class fourth via structure V74, a first-class fifth via structure V75, a first-class sixth via structure V76, a first-class seventh via structure V77, a first-class eighth via structure V78, a first-class ninth via structure V79, a first-class tenth via structure V710, a first-class eleventh via structure V711, a first-class twelfth via structure V712, a first-class thirteenth via structure V713, a first-class fourteenth via structure V714, a first-class fifteenth via structure V715, a first-class sixteenth via structure V716 and a first-class seventeenth via structure V717.

[0414] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type fourth via structure V74 on the substrate is located within the range of the orthographic projection of the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer) on the substrate, and the first-type fourth via structure V74 exposes the surface of the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer), and the first-type fourth via structure V74 is configured to connect the subsequently formed first conductive metal layer with the first area of ​​the third active layer (that is, the second area of ​​the fourth active layer).

[0415] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type fifth via structure V75 on the substrate is located within the range of the orthographic projection of the second area of ​​the third active layer (also the first area of ​​the sixth active layer) on the substrate, and the first-type fifth via structure V75 exposes the surface of the second area of ​​the third active layer (also the first area of ​​the sixth active layer). The first-type fifth via structure V75 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the third active layer (also the first area of ​​the sixth active layer).

[0416] For example, Figure 46 and 47As shown, the orthographic projection of the first type sixth via structure V76 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the first type sixth via structure V76 exposes the surface of the first area of ​​the fourth active layer, and the first type sixth via structure V76 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the fourth active layer.

[0417] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type seventh via structure V77 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the first-type seventh via structure V77 exposes the surface of the first area of ​​the fifth active layer, and the first-type seventh via structure V77 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the fifth active layer.

[0418] For example, Figure 46 and 47 As shown, the pixel driving circuits of two adjacent circuit units in the first direction X can share a first-type seventh via structure V77.

[0419] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type eighth via structure V78 on the main surface of the substrate is located within the range of the orthographic projection of the second area of ​​the fifth active layer on the main surface of the substrate, the first-type eighth via structure V78 exposes the surface of the second area of ​​the fifth active layer, and the first-type eighth via structure V78 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the fifth active layer.

[0420] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type ninth via structure V79 on the main surface of the substrate substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the main surface of the substrate substrate, the first-type ninth via structure V79 exposes the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the first-type ninth via structure V79 is configured to connect the subsequently formed first conductive metal layer with the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer).

[0421] For example, Figure 46 and 47As shown, the orthographic projection of the first type tenth via structure V710 on the main surface of the substrate is located within the range of the orthographic projection of the first area of ​​the seventh active layer on the main surface of the substrate, the first type tenth via structure V710 exposes the surface of the first area of ​​the seventh active layer, and the first type tenth via structure V710 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the seventh active layer.

[0422] For example, Figure 46 and 47 As shown, the orthographic projection of the first-type eleventh via structure V711 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the first-type eleventh via structure V711 exposes the surface of the first region of the eighth active layer, and the first-type eleventh via structure V711 is configured to connect the structure in the subsequently formed first conductive metal layer with the first region of the eighth active layer.

[0423] For example, Figure 46 and 47 As shown, the orthographic projection of the first type twelfth via structure V712 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, the first type twelfth via structure V712 exposes the surface of the second region of the eighth active layer, and the first type twelfth via structure V712 is configured to connect the structure in the subsequently formed first conductive metal layer with the second region of the eighth active layer.

[0424] For example, Figure 46 and 47 As shown, the orthographic projection of the first type fifteenth via structure V715 on the substrate is located within the range of the orthographic projection of the opening 2041a on the substrate, and the first type fifteenth via structure V715 exposes the surface of the first electrode 2035. The first type fifteenth via structure V715 is configured to connect the structure in the subsequently formed first conductive metal layer to the first electrode 2035.

[0425] For example, Figure 46 and 47 As shown, the orthographic projection of the first type sixteenth via structure V716 on the base substrate is located within the range of the orthographic projection of the second electrode 2041 on the base substrate, the first type sixteenth via structure V716 exposes the surface of the second electrode 2041, and the first type sixteenth via structure V716 is configured to connect the structure in the subsequently formed first conductive metal layer to the second electrode 2041.

[0426] For example, Figure 46 and 47As shown, the orthographic projection of the first type seventeenth via structure V717 on the base substrate is located within the range of the orthographic projection of the first initialization signal line 2034 on the base substrate, the first type seventeenth via structure V717 exposes the surface of the first initialization signal line 2034, and the first type seventeenth via structure V717 is configured to connect the structure in the subsequently formed first conductive metal layer to the first initialization signal line 2034.

[0427] For example, Figure 48 A schematic diagram of the planar structure of an etching stop layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 49 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, and an interlayer insulating layer / etching stop layer in a display substrate provided in at least one embodiment of the present disclosure.

[0428] For example, Figure 48 and Figure 49 As shown, a plurality of second-type via structures are provided in the etch stop layer 208 , and the first conductive metal layer and the second semiconductor layer 205 involved subsequently are electrically connected through the second-type via structures.

[0429] It should be noted that although the term "etch stop layer" is used to represent multiple second-type via structures, the etch stop layer actually represents another portion of the via structure that passes through the insulating layer disposed between adjacent layers among the light shielding layer, the first semiconductor layer, the first gate metal layer, the second gate metal layer, the second semiconductor layer, the third gate metal layer, and the first conductive metal layer, as well as the insulating layer between the third gate metal layer and the first conductive metal layer. For example, the insulating layer and the etch stop layer between the adjacent layers can be made of one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). The insulating layer and the etch stop layer can be single-layer, multi-layer, or composite layers. For example, the interlayer insulating layer and the etch stop layer can be disposed on the same layer.

[0430] For example, Figure 48 and 49 As shown, the multiple second-type via structures in each circuit unit include: a second-type first via structure V81, a second-type second via structure V82, a second-type third via structure V83, a second-type eighteenth via structure V818 and a second-type nineteenth via structure V819.

[0431] For example, Figure 48 and 49As shown, the orthographic projection of the second-type first via structure V81 on the substrate is located within the range of the orthographic projection of the first area of ​​the first active layer on the substrate, the second-type first via structure V81 exposes the surface of the first area of ​​the first active layer, and the second-type first via structure V81 is configured to connect the structure in the subsequently formed first conductive metal layer with the first area of ​​the first active layer.

[0432] For example, Figure 48 and 49 As shown, the orthographic projection of the second-type second via structure V82 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, and the second-type second via structure V82 exposes the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second-type second via structure V82 is configured to connect the structure in the subsequently formed first conductive metal layer with the second area of ​​the first active layer (also the first area of ​​the second active layer).

[0433] For example, Figure 48 and 49 As shown, the orthographic projection of the second-type third via structure V83 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the second-type third via structure V83 exposes the surface of the second region of the second active layer, and the second-type third via structure V83 is configured to connect the structure in the subsequently formed first conductive metal layer with the second region of the second active layer.

[0434] For example, Figure 48 and 49 As shown, the orthographic projection of the second type eighteenth via structure V818 on the base substrate is located within the range of the orthographic projection of the second initialization signal line 2063 on the base substrate, the second type eighteenth via structure V818 exposes the surface of the second initialization signal line 2063, and the second type eighteenth via structure V818 is configured to connect the structure in the subsequently formed first conductive metal layer to the second initialization signal line 2063.

[0435] For example, Figure 48 and 49 As shown, the positive projection of the second-type nineteenth via structure V819 on the base substrate is located within the range of the positive projection of the third initialization signal line 2064 on the base substrate, the second-type nineteenth via structure V819 exposes the surface of the third initialization signal line 2064, and the second-type nineteenth via structure V819 is configured to connect the structure in the subsequently formed first conductive metal layer to the third initialization signal line 2064.

[0436] For example, Figure 50A schematic diagram of the planar structure of a first conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 51 A schematic planar structure diagram of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching stop layer, and a first conductive metal layer in a display substrate provided for at least one embodiment of the present disclosure.

[0437] For example, Figure 50 and Figure 51 As shown, the first conductive metal layer 209 of each circuit unit can be referred to as a first source-drain metal layer (SD1). The first conductive metal layer 209 of each circuit unit includes at least a first connection electrode 91, a second connection electrode 92, a third connection electrode 93, a fourth connection electrode 94, a fifth connection electrode 95, a sixth connection electrode 96, a seventh connection electrode 97, an eighth connection electrode 98, a ninth connection electrode 99, a tenth connection electrode 910, and an eleventh connection electrode 911. The first source-drain metal layer also includes a first data fan-out line 51 and a first connection structure 56, a second connection structure 57, and a third connection structure 55.

[0438] For example, in an embodiment of the present disclosure, the material of the first conductive metal layer 209 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The first conductive metal layer 209 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The first conductive metal layer 209 can also be a multi-layer alloy structure, such as a multi-layer TiAlTi structure.

[0439] For example, Figure 50 and Figure 51 As shown, the second connection electrode 92 may be in the shape of a strip with a main portion extending along the second direction Y. The first end of the second connection electrode 92 is connected to the second region of the second active layer via a second-type third via structure V83. The second end of the second connection electrode 92 extends along the second direction Y and is connected to the second region of the third active layer (also the first region of the sixth active layer) via a first-type fifth via structure V75. For example, the second connection electrode 92 causes the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.

[0440] For example, Figure 50 and Figure 51As shown, the third connection electrode 93 is in a block shape, and is connected to the first region of the fourth active layer through the first type sixth via structure V76 . The third connection electrode 93 is configured to be connected to a subsequently formed data signal line.

[0441] For example, Figure 50 and Figure 51 As shown, the first end of the fourth connection electrode 94 is connected to the first region of the fifth active layer through the first-type seventh via structure V77 .

[0442] For example, Figure 50 and Figure 51 As shown, the fourth connection electrodes 94 of two adjacent circuit units in the first direction X are interconnected as an integral structure, and are connected to the first regions of the fifth active layers of the two circuit units through a shared first-type seventh via structure V77 .

[0443] For example, Figure 50 and Figure 51 As shown, since the fifth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the fourth connecting electrode 94 in the current unit row is connected to the first region of the fifth active layer of the pixel driving circuit in the next unit row, and the second end of the fourth connecting electrode 94 is connected to the second electrode plate 2041 of the pixel driving circuit in the current unit row. For example, the fourth connecting electrode 94 in the (n-1)th unit row has a first end connected to the first region of the fifth active layer of the pixel driving circuit in the (n)th unit row, and a second end connected to the second electrode plate 2041 of the pixel driving circuit in the (n-1)th unit row.

[0444] For example, Figure 50 and Figure 51 As shown, the fifth connection electrode 95 is shaped like a strip with a main portion extending along the second direction Y. The first end of the fifth connection electrode 95 is connected to the second region of the fifth active layer via the first-type eighth via structure V78. The second end of the fifth connection electrode 95 extends along the second direction Y and is connected to the second region of the eighth active layer via the first-type eleventh via structure V711. For example, the fifth connection electrode 95 enables the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3 to have the same potential, forming the second node N2 of the pixel driving circuit. In exemplary embodiments, the fifth connection electrode 95 can serve as the second node electrode in the embodiments of the present disclosure.

[0445] For example, Figure 50 and Figure 51As shown, the sixth connection electrode 96 is in the shape of an obliquely extending strip. The sixth connection electrode 96 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via the first-type ninth via structure V79. For example, the sixth connection electrode 96 is configured to connect to a subsequently formed anode connection electrode to form the fourth node N4 of the pixel driving circuit.

[0446] For example, Figure 50 and Figure 51 As shown, the seventh connection electrode 97 is in the shape of a strip with a main portion extending along the first direction X. A first end of the seventh connection electrode 97 is connected to the first region of the first active layer via a first-type via structure V81 of the second type, and a second end of the seventh connection electrode 97 is connected to the first initialization signal line 2034 via a seventeenth-type via structure V717 of the first type. For example, the seventh connection electrode 97 connects the first initialization signal line 2034 to the first electrode of the first transistor T1, and the first initialization signal line 2034 can write the transmitted first initialization signal into the first electrode of the first transistor T1.

[0447] For example, Figure 50 and Figure 51 As shown, the eighth connection electrode 98 is in the shape of a block with a main portion extending along the second direction Y. The first end of the eighth connection electrode 98 is connected to the first region of the seventh active layer via a tenth via structure V710 of the first type, and the second end of the eighth connection electrode 98 is connected to the second initialization signal line 2063 via an eighteenth via structure V818 of the second type. For example, the eighth connection electrode 98 realizes the connection between the second initialization signal line 2063 and the first electrode of the seventh transistor T7, and the second initialization signal line 2063 can write the transmitted second initialization signal into the first electrode of the seventh transistor T7.

[0448] For example, Figure 50 and Figure 51 As shown, the ninth connection electrode 99 is in a strip shape with a main portion extending along the second direction Y. The ninth connection electrode 99 is connected to the third initialization signal line 2064 through a second-type nineteenth via structure V819.

[0449] For example, Figure 50 and Figure 51As shown, since the eighth active layer of the pixel driving circuit in the current unit row is disposed in the circuit unit of the previous unit row, the first end of the ninth connecting electrode 99 in the current unit row is connected to the first region of the eighth active layer of the pixel driving circuit in the next unit row, and the second end of the ninth connecting electrode 99 is connected to the third initialization signal line 2064 in the current unit row. For example, for the ninth connecting electrode 99 in the (n-1)th unit row, its first end is connected to the first region of the eighth active layer of the pixel driving circuit in the (n)th unit row, and its second end is connected to the third initialization signal line 2064 in the (n-1)th unit row.

[0450] For example, Figure 50 and Figure 51 As shown, the shape of the tenth connecting electrode 910 is a strip shape with the main part extending along the second direction Y, presenting an inverted S shape, and the first end of the tenth connecting electrode 910 is connected to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the second type second via structure V82.

[0451] For example, Figure 50 and Figure 51 As shown, in the structure of the display substrate, the first conductive metal layer 209 includes a first data fan-out line 51, a first connection structure 56, a second connection structure 57 and a third connection structure 55. The first data fan-out line 51 extends along a first direction X, and the first connection structure 56 extends along a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is a horizontal direction, and the second direction Y is a vertical direction.

[0452] For example, Figure 50 and Figure 51 As shown, in the structure of the display substrate, the first connection structure 56 is provided between the first data fan-out line 51 and the first initialization signal line 2034 .

[0453] For example, Figure 50 and Figure 51 As shown, the first data fan-out line 51 is a whole structure without any break in the middle.

[0454] For example, in other embodiments, the first data fan-out line 51 extends along the first direction X, and the first data fan-out line 51 may also include two or more breaks, which are arranged under the power supply voltage signal line or the anode to be shielded.

[0455] For example, Figure 50 and Figure 51 As shown, the third connection structure 55 can serve as a first initialization signal transfer line. The initialization signal connection line and the first initialization signal line 2034 provided on the second conductive metal layer 212 mentioned later are electrically connected via the first initialization signal transfer line 55.

[0456] For example, Figure 50 and Figure 51 As shown, the first conductive metal layer 209 further includes a second initialization signal adapter line 913 , and the initialization signal connection line and the second initialization signal line 2063 provided on the second conductive metal layer 212 mentioned later are electrically connected via the second initialization signal adapter line 913 .

[0457] For example, the initialization signal connection line is also electrically connected to the third initialization signal line 2064 , so that the initialization signal connection line and the first initialization signal line 2034 , the second initialization signal line 2063 , and the third initialization signal line 2064 are electrically connected to form a mesh initialization signal structure.

[0458] For example, Figure 50 and Figure 51 As shown, the orthographic projection of the first data fan-out line 51 on the base substrate and the orthographic projections of the first initialization signal line 2034 and the second initialization signal line 2063 on the base substrate are spaced apart from each other.

[0459] For example, Figure 50 and Figure 51 As shown, the first data fan-out line 51 covers the active layer of the seventh transistor T7 and the active layer of the eighth transistor T8. The orthographic projection of the first data fan-out line 51 on the substrate overlaps with the orthographic projection of the third initialization signal line 2064 on the substrate. Therefore, the third initialization signal line 2064 can be used to shield the first data fan-out line 51. This routing method avoids the overlap of the first data fan-out line 51 with the first scanning signal line, the light-emitting control signal line, the first initialization signal line, etc., and can reduce the influence of signal jumps on these signal lines on the data signal. Although this routing method has the phenomenon of the third initialization signal line 2064 and the first data fan-out line 51 overlapping, the third initialization signal line 2064 will be used to shield the first data fan-out line 51, thereby minimizing the influence of signal jumps on the third initialization signal line 2064 on the data signal.

[0460] For example, Figure 51 As shown, the fourth scan signal line 2032 is also the first reset control signal line, and the positive projection of the first data fan-out line 51 on the base substrate, the positive projection of the third initialization signal line 2064 on the base substrate and the first reset control signal line 2032 overlap.

[0461] For example, Figure 51As shown, the orthographic projections of the second plate 2041 of the storage capacitor, the first shielding line 2042 and the second shielding line 2043 on the substrate are spaced apart from the orthographic projection of the first data fan-out line 51 on the substrate, thereby avoiding the first shielding line 2042 and the second shielding line 2043 from affecting the jump of the data signal.

[0462] For example, Figure 52 A schematic diagram of the planar structure of a passivation layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 53 A schematic diagram of the planar structure of a first planarization layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 54 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, and a first planarization layer in a display substrate provided for at least one embodiment of the present disclosure.

[0463] For example, Figure 52 and Figure 53 As shown, a plurality of third-type via structures are provided in the passivation layer 210 and the first planarization layer 211 , and the second conductive metal layer and the first conductive metal layer involved subsequently are electrically connected through the third-type via structures.

[0464] For example, Figures 52-54 As shown, the multiple third-type via structures in each circuit unit include: the third-type twenty-second via structure V922, the third-type twenty-third via structure V923, the third-type twenty-fourth via structure V924, the third-type twenty-fifth via structure V925, the third-type twenty-sixth via structure V926 and the third-type twenty-eighth via structure V928.

[0465] For example, Figures 52-54 As shown, the orthographic projection of the third type twenty-second via structure V922 on the base substrate is located within the range of the orthographic projection of the fourth connecting electrode 94 on the base substrate, the first flat layer of the passivation layer in the third type twenty-second via structure V922 is etched away to expose the surface of the fourth connecting electrode 94, and the third type twenty-second via structure V922 is configured to connect the subsequently formed power supply voltage signal line to the fourth connecting electrode 94.

[0466] For example, Figures 52-54As shown, the orthographic projection of the twenty-third via structure V923 of the third type on the substrate is located within the range of the orthographic projection of the third connecting electrode 93 on the substrate, the passivation layer and the first flat layer in the twenty-third via structure V923 of the third type are etched away to expose the surface of the third connecting electrode 93, and the twenty-third via structure V923 of the third type is configured to connect the subsequently formed data signal line to the third connecting electrode 93.

[0467] For example, Figures 52-54 As shown, the orthographic projections of the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category on the substrate are located within the range of the orthographic projections of the second connection structure 57 on the substrate, the passivation layer and the first flat layer within the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category are etched away to expose the surface of the second connection structure 57, and the twenty-fourth via structure V924 of the third category and the twenty-fifth via structure V925 of the third category are configured to connect the subsequently formed second conductive metal layer to the second connection structure 57.

[0468] For example, Figures 52-54 As shown, the orthographic projection of the twenty-sixth via structure V926 of the third type on the substrate is located within the range of the orthographic projection of the third connection structure 55 on the substrate, the passivation layer and the first flat layer in the twenty-sixth via structure V926 of the third type are etched away to expose the surface of the third connection structure 55, and the twenty-sixth via structure V926 of the third type is configured to connect the subsequently formed second conductive metal layer to the third connection structure 55.

[0469] For example, Figures 52-54 As shown, the orthographic projection of the twenty-eighth via structure V928 of the third type on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 96 on the substrate, the passivation layer and the first flat layer within the twenty-eighth via structure V928 of the third type are etched away to expose the surface of the sixth connecting electrode 96, and the twenty-eighth via structure V928 of the third type is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 96.

[0470] For example, the process of forming the pattern of the passivation layer and the first planarization layer includes: coating a passivation layer film and a first planarization layer film on a substrate substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer and a first conductive metal layer is formed, patterning the passivation layer film and the first planarization layer film using a patterning process to form a passivation layer and a first planarization layer covering the pattern of the first conductive metal layer, and a plurality of third-type via structures are arranged on the passivation layer and the first planarization layer.

[0471] For example, the first planarization layer may be formed of an organic material, such as resin, etc. The passivation layer may be formed of an inorganic insulating material, such as silicon nitride, silicon oxynitride, or silicon dioxide.

[0472] For example, Figure 55 A schematic diagram of the planar structure of a second conductive metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 56 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, and a second conductive metal layer in a display substrate provided for at least one embodiment of the present disclosure.

[0473] For example, Figure 55 and Figure 56 As shown, the second conductive metal layer 212 of each circuit unit includes: a power supply voltage signal line 212a, a data signal line 212b, an anode connection electrode 212c, an initialization signal connection line 212d and a second data fan-out line 212e. The second conductive metal layer 212 can serve as a second source and drain metal (SD2) layer.

[0474] For example, Figure 55 and Figure 56 As shown, the shape of the power supply voltage signal line 212a is a straight line or a broken line with the main part extending along the second direction Y. The power supply voltage signal line 212a is connected to the fourth connection electrode 94 through the third type twenty-second via structure V922. The fourth connection electrode 94 is respectively connected to the first electrode of the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor, thereby realizing that the power supply voltage signal line 212a writes the first power supply signal into the fifth transistor T5 and the second electrode plate 2041 of the storage capacitor.

[0475] For example, Figure 55 and Figure 56 As shown, the power supply voltage signal line 212a can be a zigzag line with non-uniform width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the power supply voltage signal line and the data signal line.

[0476] For example, Figure 55 and Figure 56As shown, the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate, and the orthographic projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, so that the power supply voltage signal line 212a can block the first active layer and the second active layer, and can block the light emitted by the light-emitting element and the light reflected by the film layer from irradiating the first transistor T1 and the second transistor T2 of the oxide, thereby preventing the characteristics of the oxide transistor from drifting due to light, and improving the electrical characteristics of the oxide transistor.

[0477] For example, Figure 55 and Figure 56 As shown, the positive projection of the power supply voltage signal line 212a on the base substrate at least partially overlaps with the positive projection of the first connection electrode 91 on the base substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby avoiding the influence of data voltage jumps and other signals on the potential of the first node N1, and improving the driving performance of the pixel driving circuit.

[0478] For example, Figure 55 and Figure 56 As shown, the positive projection of the power supply voltage signal line 212a on the substrate at least partially overlaps with the positive projections of the second connection electrode 92 and the tenth connection electrode 910 on the substrate. The power supply voltage signal line 212a with a constant potential can effectively shield the influence of data voltage jumps and other signals on various nodes in the pixel driving circuit, avoid the influence of data voltage jumps and other signals on the node potential, and improve the driving performance of the pixel driving circuit.

[0479] For example, Figure 55 and Figure 56 As shown, the data signal line 212b can be in the shape of a straight line or a broken line, with the main portion extending along the second direction Y. The data signal line 212b is connected to the third connection electrode 93 via a twenty-third via structure V923 of the third type. Since the third connection electrode 93 is connected to the first region of the fourth active layer through the via, the data signal line 212b is connected to the first electrode of the fourth transistor T4. The data signal line 212b can write a data signal into the first electrode of the fourth transistor T4.

[0480] For example, Figure 55 and Figure 56As shown, the anode connection electrode 212c is shaped like an elongated strip extending in the second direction Y. The anode connection electrode 212c is connected to the sixth connection electrode 96 via a third-type twenty-eighth via structure V928. The anode connection electrode 212c is configured to be connected to a subsequently formed anode. Because the sixth connection electrode 96 is connected to the second region of the sixth active layer and the second region of the seventh active layer, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting element to emit light.

[0481] For example, the process of forming the second conductive metal layer includes: depositing a second conductive metal film on a substrate on which a pattern of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer and a first planarization layer is formed, and patterning the second conductive metal film using a patterning process to form a second conductive metal layer arranged on the first planarization layer.

[0482] For example, the material of the first conductive metal layer 212 is any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). The second conductive metal layer 212 can be a single metal layer or a composite structure of multiple metal layers, such as Mo / Cu / Mo. The second conductive metal layer 212 can also be a multi-layer alloy structure, such as a multi-layer TiAlTi structure.

[0483] For example, Figure 55 and Figure 56 As shown, the initialization signal connection line 212d is electrically connected to the first initialization signal transfer line 55 through a second via structure V926 provided in the first insulating layer, and is electrically connected to the second initialization signal transfer line 913 through another second via structure V926 provided in the first insulating layer. For example, the first insulating layer includes a passivation layer and a first planarization layer, and the second via structure is a hole structure that penetrates the passivation layer and the first planarization layer. For example, in the second direction Y, the second via structure V926 and the first via structure V928 mentioned later are respectively provided on both sides of the first data fan-out line 51. This can increase the distance between the first via structure V928 and the second via structure V926, thereby reducing the length of the connection line connecting the first initialization signal line and the second initialization signal line to the network, which is beneficial to reducing the load of the first initialization signal line and the second initialization signal line. In addition, due to the downward position of the first via structure, the first via structure corresponding to the N4 node can be moved outward, thereby increasing the distance between the first via structure and the corresponding anode, thereby improving the flatness of the anode in the corresponding sub-pixel.

[0484] For example, Figure 55 and Figure 56 As shown, the second data fan-out line 212e is disposed between two adjacent data signal lines 212b.

[0485] For example, Figure 55 and Figure 56 As shown, two adjacent initialization signal connection lines 212d, two adjacent anode connection electrodes 212c, two adjacent power supply voltage signal lines 212a, and two adjacent data signal lines 212b are all axially symmetrical about the second data fan-out line 212e.

[0486] For example, Figure 57 A schematic diagram of the planar structure of a second planarization layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 58 A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, and a second planarization layer in a display substrate provided for at least one embodiment of the present disclosure.

[0487] For example, Figure 57 and Figure 58 As shown, a second planarization layer 213 is disposed over the entire substrate. The second planarization layer 213 has a plurality of fourth-type via structures 213a / 213b / 213c / 213d. The fourth-type via structures 213a / 213b / 213c / 213d expose anode connection electrodes. These fourth-type via structures 213a / 213b / 213c / 213d enable subsequent anodes to be connected to the anode connection electrodes in the second conductive metal layer.

[0488] For example, the second planarization layer may be formed of an organic material, such as a resin.

[0489] For example, the fourth type via structure 213 a / 213 b / 213 c / 213 d may serve as an anode connection hole. The first insulating layer includes the second planarization layer 212 , and the fourth type via structure 213 a / 213 b / 213 c / 213 d is disposed in the second planarization layer 212 .

[0490] For example, Figure 59 A schematic diagram of the planar structure of an anode layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 60A schematic diagram of the planar structure of a stack of a light-shielding layer, a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, an interlayer insulating layer / etching barrier layer, a first conductive metal layer, a passivation layer, a first planarization layer, a second conductive metal layer, a second planarization layer and an anode layer in a display substrate provided for at least one embodiment of the present disclosure.

[0491] For example, Figure 59 and Figure 60 As shown, an anode layer 214 is disposed on the second planarization layer 213. The anode layer 214 includes a plurality of anode electrodes 214a / 214b / 214c / 214d. Anode electrode 214a may be an electrode corresponding to the first subpixel P1, anode electrode 214b may be an electrode corresponding to the second subpixel P2, anode electrode 214c may be an electrode corresponding to the third subpixel P3, and anode electrode 214d may be an electrode corresponding to the fourth subpixel P4. Anode electrode 214a, anode electrode 214b, anode electrode 214c, and anode electrode 214d are connected to the anode connection electrode in the second conductive metal layer through fourth-type via structures 213a, 213b, 213c, and 213d, respectively.

[0492] For example, in one example, the first sub-pixel P1 is a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 are green sub-pixels (G) that emit green light, and the third sub-pixel P3 is a blue sub-pixel (B) that emits blue light. The embodiments of the present disclosure are not limited to this.

[0493] For example, combined with Figures 33 to 60 The display substrate includes: a base substrate 101, a driving circuit layer 102 on the base substrate 101, the driving circuit layer 102 including a pixel driving circuit, and a plurality of light-emitting elements are arranged on the side of the pixel driving circuit away from the base substrate 101; the pixel driving circuit includes a first conductive metal layer 209, a first insulating layer 210 / 211, and a second conductive metal layer 212 arranged in a stacked manner, the second conductive metal layer 212 including an initialization signal connection line 212d, an anode connection electrode 212c, and a power supply electrode arranged in a first direction X. The voltage signal line 212a, the initialization signal connection line 212d, the anode connection electrode 212c and the power supply voltage signal line 212a all extend along the second direction Y intersecting the first direction X, and the anode connection electrode 212c is electrically connected to the first conductive metal layer 209 through a first via structure provided in the first insulating layer 210 / 211; the plurality of light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and the orthographic projection of the first anode on the base substrate 101 does not overlap with the orthographic projection of the first via structure on the base substrate 101. The first via structure is Figure 25The twenty-eighth via structure V928 of the third type in the third type via structure in the first planarization layer.

[0494] For example, the first anode can be the anode corresponding to the red sub-pixel, and the orthographic projection of the anode corresponding to the red sub-pixel on the base substrate 101 does not overlap with the orthographic projection of the first via structure V928 on the base substrate 101, that is, the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the red sub-pixel.

[0495] For example, in one embodiment, the plurality of light-emitting elements includes a second light-emitting element, the second light-emitting element includes a second anode, and the orthographic projection of the second anode on the base substrate partially overlaps with the orthographic projection of the first via structure V928 on the base substrate. For example, the second anode may be the anode corresponding to the blue sub-pixel, and the orthographic projection of the anode corresponding to the blue sub-pixel on the base substrate 101 partially overlaps with the orthographic projection of the first via structure V928 on the base substrate 101, that is, a portion of the third type twenty-eighth via structure V928 is located outside the area covered by the anode corresponding to the blue sub-pixel.

[0496] For example, in one example, the area where the orthographic projection of the second anode on the substrate overlaps with the orthographic projection of the first via structure V928 on the substrate is 5% to 20% of the area of ​​the first via structure, that is, the area covered by the second anode on the first via structure V928 does not exceed 1 / 5 of the area of ​​the first via structure V928.

[0497] For example, the second conductive metal layer 212 also includes a second data fan-out line 212e, which extends along the second direction Y and has a break in the middle area. The second data fan-out line 212e is connected to the eleventh connecting electrode 911 at one end of the break through the third type twenty-fourth via structure V924 and the eleventh connecting electrode 911 at the other end of the break through the third type twenty-fifth via structure V925 and the eleventh connecting electrode 911.

[0498] Figure 61 This is a schematic diagram of an equivalent circuit of another pixel driving circuit provided by at least one embodiment of the present disclosure, as shown in FIG. Figure 61 As shown, the pixel driving circuit has an 8T1C structure and may include 8 transistors (a first transistor T1 to an eighth transistor T8) and a storage capacitor C. Each pixel driving circuit is respectively connected to 12 signal lines (a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, a fourth scanning signal line S4, a fifth scanning signal line S5, a first light-emitting signal line EM1, a second light-emitting signal line EM2, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a data signal line DATA, and a power supply voltage signal line VDD).

[0499] For example, in an embodiment of the present disclosure, Figure 61 The connection structure of the first transistor T1 to the eighth transistor T8 and the storage capacitor C in the pixel driving circuit shown is similar to Figure 33 The structure of the pixel driving circuit shown is different in that: Figure 61 In the pixel driving circuit shown, the first transistor T1 is connected to the third node, and the N3 node is between the first transistor T1 and the second transistor T2.

[0500] also, Figure 61 In the pixel driving circuit shown, the material of the active layer of the first transistor T1 is low-temperature polysilicon, and the first transistor T1 can be a low-temperature polysilicon transistor (P-type transistor); the material of the active layer of the second transistor T2 is a conductive metal oxide, and the second transistor T2 can be an oxide transistor (N-type transistor), that is, the active layer of the first transistor T1 and the active layer of the second transistor T2 are located in different layers.

[0501] For example, Figure 61 As shown, the pixel driving circuit includes a storage capacitor and multiple transistors, the storage capacitor may include a first electrode plate and a second electrode plate arranged opposite to each other, the multiple transistors may include a first transistor T1 as a first initialization transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, a sixth transistor T6 as a second light-emitting control transistor, a seventh transistor T7 as a second initialization transistor and an eighth transistor T8 as a third initialization transistor, wherein the second transistor T2 is an oxide transistor, and the first transistor T1 and the third transistor T3 to the eighth transistor T8 are low-temperature polysilicon transistors.

[0502] For example, Figure 62 A schematic diagram of a planar structure of a light shielding layer in a display substrate provided in at least one embodiment of the present disclosure is shown in FIG. Figure 62 As shown, the light shielding layer 201 may be a bottom light shielding metal (BSM) layer.

[0503] For example, Figure 62As shown, the pattern of the light-shielding layer 201 includes at least a first light-shielding connecting line 2011, a second light-shielding connecting line 2012, and a light-shielding electrode 2013, with the plurality of light-shielding electrodes 2013 arranged in an array. For example, the planar shape of the light-shielding electrode 2013 is roughly rectangular, and the corners of the rectangle may be chamfered. The first light-shielding connecting line 2011 may be in the shape of a straight line or a zigzag line extending along the second direction Y. The first light-shielding connecting line 2011 may be disposed on either side of the light-shielding electrode 2013 along the second direction Y and connected to the light-shielding electrode 2013. The second light-shielding connecting line 2012 may be in the shape of a straight line or a zigzag line extending along the first direction X. The second light-shielding connecting line 2012 may be disposed on either side of the light-shielding electrode 2013 along the first direction X and connected to the light-shielding electrode 2013, thereby forming a mesh-like pattern on the light-shielding layer.

[0504] For example, Figure 62 As shown, in a unit row, the second light-shielding connection lines 2012 in two adjacent circuit units in the first direction X can be connected to form an interconnected integrated structure.

[0505] For example, in other embodiments of the present disclosure, in a unit column, the first shading connection lines 2011 in two adjacent circuit units in the second direction Y can be connected to form an integrated structure that is interconnected, that is, the shading layers in the unit row and the unit column are connected into one, thereby ensuring that the shading layers in the display substrate have the same electric potential, which is beneficial to improving the display uniformity of the subsequently formed display panel, avoiding poor display of the display panel, and ensuring the display effect of the display panel.

[0506] For example, forming the pattern of the light shielding layer includes: depositing a light shielding layer thin film on the base substrate, and patterning the light shielding layer thin film through a patterning process to form a light shielding layer pattern. The material of the light shielding layer can be a light shielding metal material.

[0507] It should be noted that the "patterning process" mentioned in the embodiments of the present disclosure includes, for metal materials, inorganic materials or transparent conductive materials, deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes; for organic materials, it includes coating of organic materials, mask exposure and development and other processes. Deposition can be carried out by any one or more of sputtering, evaporation and chemical vapor deposition; coating can be carried out by any one or more of spraying, spin coating and inkjet printing; etching can be carried out by any one or more of dry etching and wet etching, and the embodiments of the present disclosure are not limited to this. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". In the embodiments of the present disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the main surface of the display substrate. In the embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B. This will not be further described below.

[0508] For example, Figure 63 This is a schematic diagram of the planar structure of the first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 63 As shown, the first semiconductor layer 202 may form the first active layer 21 of the first transistor T1 , the third active layer 23 of the third transistor T3 , to the eighth active layer 28 of the eighth transistor T8 .

[0509] For example, Figure 63 As shown, the third active layer 23 , the fourth active layer 24 , the fifth active layer 25 , the sixth active layer 26 and the seventh active layer 27 are interconnected as an integral structure, and the first active layer 21 and the eighth active layer 28 are separately provided.

[0510] For example, the first active layer 21 is the channel region of the first transistor T1 (first initialization transistor), the third active layer 23 is the channel region of the third transistor T3 (driving transistor), the fourth active layer 24 is the channel region of the fourth transistor T4 (data writing transistor), the fifth active layer 25 is the channel region of the fifth transistor T5 (first light-emitting control transistor), the sixth active layer 26 is the channel region of the sixth transistor T6 (second light-emitting control transistor), the seventh active layer 27 is the channel region of the seventh transistor T7 (second initialization transistor), and the eighth active layer 28 is the channel region of the eighth transistor T8 (third initialization transistor).

[0511] For example, Figure 64 This is a schematic diagram of a planar structure of a stack of a light shielding layer and a first semiconductor layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 64 As shown, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the substrate. The light-shielding electrode 2013 serves as a light-shielding layer of the third transistor T3, shielding the channel region of the third transistor T3 to ensure the electrical performance of the third transistor T3.

[0512] For example, in an embodiment of the present disclosure, in the pixel driving circuit of the present circuit unit, in the first direction X, the fourth active layer 24, the fifth active layer 25, and the eighth active layer 28 may be located on one side of the third active layer 23 in the present circuit unit in the first direction X, and the sixth active layer 26 is located on a side of the third active layer 23 in the present circuit unit in the opposite direction of the first direction X. In the second direction Y, the sixth active layer 26 and the seventh active layer 27 may be located on one side of the third active layer 23 in the present circuit unit in the second direction Y.

[0513] For example, Figure 63 and Figure 64 As shown, the shape of the third active layer 23 can be an inverted "Ω" shape, the shapes of the fourth active layer 24, the fifth active layer 25 and the sixth active layer 26 can be strip shapes with the main part extending along the second direction Y, the shape of the seventh active layer 27 can be an inverted "L" shape, and the shape of the eighth active layer 28 can be an inverted "S" shape.

[0514] For example, Figure 63As shown, the first active layer 21 and the third active layer 23 to the eighth active layer 28 may each include a first region, a second region, and a channel region located between the first and second regions. For example, the first region 23a of the third active layer 23 is connected to the second region 24b of the fourth active layer 24, and the first region 23a of the third active layer 23 can serve as the second region 24b of the fourth active layer 24. The second region 23b of the third active layer 23 is connected to the first region 26a of the sixth active layer 26, and the second region 23b of the third active layer 23 can serve as the first region 26a of the sixth active layer 26. The second region 26b of the sixth active layer 26 is connected to the second region 27b of the seventh active layer 27, and the second region 26b of the sixth active layer 26 can serve as the second region 27b of the seventh active layer 27. The first region 21a of the first active layer 21, the second region 21b of the first active layer 21, the first region 24a of the fourth active layer 24, the first region 25a of the fifth active layer 25, the second region 25b of the fifth active layer 25, the first region 27a of the seventh active layer 27, the first region 28a of the eighth active layer 28, and the second region 28b of the eighth active layer 28 can be set separately.

[0515] For example, Figure 63 As shown, in a unit column, the fifth active layer 25 and the eighth active layer 28 of the pixel driving circuit in this circuit unit can be set in the circuit unit of the previous unit row, and the first active layer 21, the third active layer 23, the fourth active layer 24, the sixth active layer 26 and the seventh active layer 27 can be set in this circuit unit.

[0516] For example, Figure 63 As shown, the fifth active layer 25 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the first direction X of the sixth active layer 26 of the pixel driving circuit in the circuit unit of the previous unit row, so that the fifth active layer 25 and the sixth active layer 26 of the pixel driving circuit in the two unit rows can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the sixth transistor T6 of the current unit row and the fifth transistor T5 of the next unit row. For example, the fifth active layer 25 of the pixel driving circuit in the n-th unit row is arranged in the circuit unit of the n-1-th unit row, so that the fifth active layer 25 of the pixel driving circuit in the n-th unit row and the sixth active layer 26 of the pixel driving circuit in the n-1-th unit row can share a light-emitting control signal line, and the light-emitting control signal line can simultaneously control the conduction and disconnection of the fifth transistor T5 of the n-th unit row and the sixth transistor T6 of the n-1-th unit row.

[0517] For example, in at least one embodiment of the present disclosure, the eighth active layer 28 of the pixel driving circuit in the circuit unit of the current unit row is located on one side of the seventh active layer 27 of the pixel driving circuit in the circuit unit of the previous unit row in the first direction X, so that the seventh active layer 27 and the eighth active layer 28 of the two unit rows can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the current unit row and the eighth transistor T8 of the next unit row. For example, the eighth active layer 28 of the pixel driving circuit in the nth unit row is arranged in the circuit unit of the n-1th unit row, so that the eighth active layer 28 of the pixel driving circuit in the nth unit row and the seventh active layer 27 of the pixel driving circuit in the n-1th unit row can share a scan signal line, and the scan signal line can simultaneously control the conduction and disconnection of the seventh transistor T7 of the n-1th unit row and the eighth transistor T8 of the nth unit row.

[0518] For example, in at least one embodiment of the present disclosure, the first semiconductor layer 202 is formed of polycrystalline silicon (p-Si), that is, the first transistor T1 and the third transistor T3 to the eighth transistor T8 are LTPS transistors.

[0519] For example, forming the pattern of the first semiconductor layer includes: depositing a first semiconductor film, and then patterning the first semiconductor film through a patterning process. For example, the process of patterning the first semiconductor film through the patterning process includes: first forming an amorphous silicon (A-Si) film, dehydrogenating the A-Si film, crystallizing the dehydrogenated A-Si film to form a polycrystalline silicon film, and then patterning the polycrystalline silicon film to form the pattern of the first semiconductor layer.

[0520] For example, Figure 65 A schematic diagram of the planar structure of a first gate metal layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 66 This is a schematic planar structural diagram of a stack of a light shielding layer, a first semiconductor layer, and a first gate metal layer in a display substrate provided by at least one embodiment of the present disclosure. Figure 65 As shown, the first gate metal layer 203 corresponding to each circuit unit includes at least: a second scanning signal line 2031, a fourth scanning signal line 2032, a light emitting control signal line 2033, a third scanning signal line 2062 and a first plate 2035 of a storage capacitor.

[0521] For example, Figure 66As shown, the first electrode plate 2035 is rectangular in shape, and the corners of the rectangle may be chamfered. The orthographic projection of the first electrode plate 2035 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. For example, the first electrode plate 2035 can simultaneously serve as a plate of the storage capacitor and the gate electrode of the third transistor T3.

[0522] For example, Figure 66 As shown, the orthographic projection of the first electrode plate 2035 on the base substrate at least partially overlaps with the orthographic projection of the light-shielding electrode 2013 on the base substrate.

[0523] For example, Figure 66 As shown, the shape of the second scanning signal line 2031 is a straight line or a broken line with the main part extending along the first direction X. The second scanning signal line 2031 is located on the side of the first electrode 2035 in the opposite direction of the second direction Y. The area where the second scanning signal line 2031 overlaps with the fourth active layer 24 can be used as the gate electrode of the fourth transistor T4.

[0524] For example, Figure 66 As shown, the fourth scan signal line 2032 is shaped as a straight line or a zigzag line with its main portion extending along the first direction X. The fourth scan signal line 2032 is located on one side of the first electrode 2035 in the second direction Y. The area where the fourth scan signal line 2032 of the current unit row overlaps with the seventh active layer 27 of the pixel driving circuit in the current unit row serves as the gate electrode of the seventh transistor T7 in the current unit row. The area where the fourth scan signal line 2032 of the current unit row overlaps with the eighth active layer 28 of the pixel driving circuit in the next unit row can serve as the gate electrode of the eighth transistor T8 in the next unit row. For example, for the fourth scan signal line 2032 of the (n-1)th unit row, the area where it overlaps with the seventh active layer 27 of the pixel driving circuit in the (n-1)th unit row serves as the gate electrode of the seventh transistor T7 in the (n-1)th unit row, and the area where it overlaps with the eighth active layer 28 of the pixel driving circuit in the (n)th unit row can serve as the gate electrode of the eighth transistor T8 in the (n)th unit row.

[0525] For example, Figure 66As shown, the light-emitting control signal line 2033 is in the shape of a straight line or a broken line, with the main portion extending along the first direction X. The light-emitting control signal line 2033 is located between the first electrode 2035 and the fourth scanning signal line 2032. The area where the light-emitting control signal line 2033 of the current unit row overlaps with the sixth active layer 26 of the pixel driving circuit in the current unit row can serve as the gate electrode of the sixth transistor T6 of the current unit row, and the area where the light-emitting control signal line 2033 of the current unit row overlaps with the fifth active layer 25 of the pixel driving circuit in the next unit row can serve as the gate electrode of the fifth transistor T5 of the next unit row. For example, for the light-emitting control signal line 2033 of the n-1th unit row, the area where it overlaps with the sixth active layer 26 of the pixel driving circuit in the n-1th unit row can serve as the gate electrode of the sixth transistor T6 in the n-1th unit row, and the area where it overlaps with the fifth active layer 25 of the pixel driving circuit in the nth unit row can serve as the gate electrode of the fifth transistor T5 in the nth unit row.

[0526] For example, Figure 66 As shown, the shape of the first scanning signal line 2061 is a straight line or a broken line with the main part extending along the first direction X. The third scanning signal line 2062 is located on the side of the second scanning signal line 2031 away from the first electrode 2035. The area where the third scanning signal line 2062 of this unit row overlaps with the first active layer 21 of the pixel driving circuit in this unit row can be used as the gate electrode of the first transistor T1 of this unit row.

[0527] For example, Figure 66 As shown, the second scanning signal line 2031, the fourth scanning ...

Claims

1. A display substrate, characterized in that: include: substrate; a pixel driving circuit on the base substrate, and a plurality of light emitting elements located on a side of the pixel driving circuit away from the base substrate; The pixel driving circuit includes a first conductive metal layer, a first insulating layer, and a second conductive metal layer stacked together, the second conductive metal layer including an initialization signal connection line, an anode connection electrode, and a power supply voltage signal line arranged in a first direction, the initialization signal connection line, the anode connection electrode, and the power supply voltage signal line all extending along a second direction intersecting the first direction, the anode connection electrode being electrically connected to the second conductive metal layer via a first via structure provided in the first insulating layer; The plurality of light-emitting elements include a first light-emitting element, the first light-emitting element includes a first anode, and an orthographic projection of the first anode on the base substrate and an orthographic projection of the first via structure on the base substrate do not overlap.

2. The display substrate according to claim 1, wherein: The plurality of light-emitting elements include a second light-emitting element, the second light-emitting element includes a second anode, and an orthographic projection of the second anode on the base substrate partially overlaps with an orthographic projection of the first via structure on the base substrate.

3. The display substrate according to claim 2, wherein: An overlapping area of ​​an orthographic projection of the second anode on the base substrate and an orthographic projection of the first via structure on the base substrate is 0% to 20% of an area of ​​the first via structure.

4. The display substrate according to any one of claims 1 to 3, wherein , further comprising a third gate metal layer disposed on a side of the first conductive metal layer away from the second conductive metal layer, wherein the first conductive metal layer includes a first data fan-out line extending along the first direction, and the second conductive metal layer includes a second data fan-out line extending along the second direction; The third gate metal layer includes a third initialization signal line extending along the first direction; An orthographic projection of the first data fan-out line on the base substrate overlaps with an orthographic projection of the third initialization signal line on the base substrate.

5. The display substrate according to claim 4, characterized in that , also includes a first gate metal layer arranged on a side of the third gate metal layer away from the first conductive metal layer, wherein the first gate metal layer includes a first initialization signal line extending along the first direction, and the third gate metal layer also includes a second initialization signal line spaced apart from the third initialization signal line and extending along the second direction, and the orthographic projection of the first data fan-out line on the base substrate and the orthographic projections of the first initialization signal line and the second initialization signal line on the base substrate are spaced apart from each other.

6. The display substrate according to claim 5, wherein: The first conductive metal layer includes a first initialization signal patch line and a second initialization signal patch line; The initialization signal connection line is electrically connected to the first initialization signal transfer line through a second via structure provided in the first insulation layer, and is electrically connected to the second initialization signal transfer line through another second via structure provided in the first insulation layer.

7. The display substrate according to claim 6, wherein: In the second direction, the second via structure and the first via structure are respectively arranged on two sides of the first data fan-out line.

8. The display substrate according to claim 6 or 7, wherein: The initialization signal connection line and the first initialization signal line are electrically connected through the first initialization signal adapter line, the initialization signal connection line and the second initialization signal line are electrically connected through the second initialization signal adapter line, and the initialization signal connection line and the third initialization signal line are electrically connected to each form a meshed initialization signal structure.

9. The display substrate according to claim 8, wherein: The second conductive metal layer further includes a data signal line extending in the second direction, and the second data fan-out line is disposed between two adjacent data signal lines.

10. The display substrate according to claim 9, wherein: Two adjacent initialization signal connection lines, two adjacent anode connection electrodes, two adjacent power supply voltage signal lines, and two adjacent data signal lines are all axially symmetrical with respect to the second data fan-out line.

11. The display substrate according to claim 10, wherein: The first gate metal layer further includes a first reset control signal line, and an orthographic projection of the first data fan-out line on the base substrate, an orthographic projection of the third initialization signal line on the base substrate, and the first reset control signal line overlap.

12. The display substrate according to claim 5, wherein , also includes a second gate metal layer arranged between the third gate metal layer and the first gate metal layer, wherein the second gate metal layer includes a second plate of a storage capacitor extending in the first direction, a first shielding line and a second shielding line, and the orthographic projections of the second plate of the storage capacitor, the first shielding line and the second shielding line on the base substrate are spaced apart from the orthographic projections of the first data fan-out line on the base substrate.

13. The display substrate according to claim 12, wherein: The third gate metal layer also includes a third scanning signal line and a first scanning signal line arranged on a side of the third initialization signal line close to the second initialization signal line, the orthographic projection of the third scanning signal line on the base substrate and the orthographic projection of the second shielding line on the base substrate overlap, and the orthographic projection of the first scanning signal line on the base substrate and the orthographic projection of the first shielding line on the base substrate overlap.

14. The display substrate according to claim 9 or 10, characterized in that: The pixel driving circuit includes a driving transistor, a seventh transistor, and an eighth transistor, wherein a first electrode of the eighth transistor is connected to the third initialization signal line, a second electrode of the eighth transistor is connected to the first electrode of the driving transistor, a first electrode of the seventh transistor is connected to the second initialization signal line, and a second electrode of the seventh transistor is connected to the first electrode of the first light-emitting element; The display substrate further includes: a first active layer located between the base substrate and the first gate metal layer, the first active layer including a seventh active portion and an eighth active portion, the seventh active portion being used to form a channel region of the seventh transistor, and the eighth active portion being used to form a channel region of the eighth transistor; The orthographic projection of the first reset control signal line on the base substrate covers the orthographic projection of the eighth active portion on the base substrate and the orthographic projection of the seventh active portion on the base substrate, and a partial structure of the first reset control signal line is used to form the gate of the seventh transistor, and a partial structure of the first reset control signal line is used to form the gate of the eighth transistor.

15. The display substrate according to claim 14, wherein: The pixel driving circuit further includes a fourth transistor and a sixth transistor, wherein a first electrode of the fourth transistor is connected to the data signal line, a second electrode of the fourth transistor is electrically connected to the second electrode of the eighth transistor; and a first electrode of the sixth transistor is electrically connected to the second electrode of the seventh transistor. The first active layer further includes a third active portion, a fourth active portion, and a sixth active portion. The third active portion is configured to form a channel region of the driving transistor. The fourth active portion is connected to the eighth active portion. The sixth active portion is connected to the seventh active portion.

16. The display substrate according to claim 15, wherein: The pixel driving circuit further includes a first transistor and a second transistor, wherein a first electrode of the first transistor is connected to the first initialization signal line, a second electrode of the first transistor is connected to the second electrode of the driving transistor, a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the driving transistor; The display substrate further includes a second active layer between the first active layer and the third gate metal layer, the second active layer including a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

17. The display substrate according to claim 15, wherein: The pixel driving circuit further includes a first transistor, a second transistor, and a ninth transistor, wherein a first electrode of the first transistor is connected to the first initialization signal line, a second electrode of the first transistor is connected to the second electrode of the ninth transistor, a first electrode of the second transistor is connected to the second electrode of the driving transistor, and a second electrode of the second transistor is connected to the second electrode of the ninth transistor; The display substrate further includes a second active layer between the first active layer and the third gate metal layer, the second active layer including a first active portion and a second active portion, the first active portion is used to form a channel region of the first transistor, and the second active portion is used to form a channel region of the second transistor.

18. A display device, characterized in that , comprising the display substrate according to any one of claims 1 to 17.

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